| /openbmc/linux/Documentation/devicetree/bindings/gpio/ |
| H A D | gpio-mmio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/gpio-mmio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
11 - Bartosz Golaszewski <brgl@bgdev.pl>
15 of set/clear-bit registers. Such controllers are common for glue logic in
16 FPGAs or ASICs. Commonly, these controllers are accessed over memory-mapped
17 NAND-style parallel busses.
22 - brcm,bcm6345-gpio
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| /openbmc/u-boot/drivers/net/ |
| H A D | pic32_eth.c | 1 // SPDX-License-Identifier: GPL-2.0+
41 if (!dm_gpio_is_valid(&priv->rst_gpio)) in board_netphy_reset()
45 dm_gpio_set_value(&priv->rst_gpio, 0); in board_netphy_reset()
47 dm_gpio_set_value(&priv->rst_gpio, 1); in board_netphy_reset()
56 struct pic32_ectl_regs *ectl_p = priv->ectl_regs; in pic32_mii_init()
57 struct pic32_emac_regs *emac_p = priv->emac_regs; in pic32_mii_init()
63 writel(ETHCON_ON | ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr); in pic32_mii_init()
66 wait_for_bit_le32(&ectl_p->stat.raw, ETHSTAT_BUSY, false, in pic32_mii_init()
70 writel(ETHCON_ON, &ectl_p->con1.set); in pic32_mii_init()
75 writel(EMAC_SOFTRESET, &emac_p->cfg1.set); /* reset assert */ in pic32_mii_init()
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| H A D | mtk_eth.c | 1 // SPDX-License-Identifier: GPL-2.0
6 * Author: Mark Lee <mark-mc.lee@mediatek.com>
185 writel(val, priv->fe_base + PDMA_BASE + reg); in mtk_pdma_write()
188 static void mtk_pdma_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, in mtk_pdma_rmw() argument
191 clrsetbits_le32(priv->fe_base + PDMA_BASE + reg, clr, set); in mtk_pdma_rmw()
204 writel(val, priv->fe_base + gdma_base + reg); in mtk_gdma_write()
209 return readl(priv->gmac_base + reg); in mtk_gmac_read()
214 writel(val, priv->gmac_base + reg); in mtk_gmac_write()
217 static void mtk_gmac_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, u32 set) in mtk_gmac_rmw() argument
219 clrsetbits_le32(priv->gmac_base + reg, clr, set); in mtk_gmac_rmw()
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| /openbmc/linux/drivers/gpio/ |
| H A D | gpio-mmio.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Generic driver for memory-mapped GPIO controllers.
22 * . big-endian notation, just`. .. A bit more sophisticated controllers ,
23 * . register the device with -be`. .with a pair of set/clear-bit registers ,
29 * .. The expectation is that in at least some cases . ,-~~~-,
30 * .this will be used with roll-your-own ASIC/FPGA .` \ /
38 * . the number of GPIOs is determined by the width of ~
129 if (gc->be_bits) in bgpio_line2mask()
130 return BIT(gc->bgpio_bits - 1 - line); in bgpio_line2mask()
137 bool dir = !!(gc->bgpio_dir & pinmask); in bgpio_get_set()
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| /openbmc/linux/drivers/pinctrl/ |
| H A D | pinctrl-microchip-sgpio.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
138 addr->port = pin / priv->bitcount; in sgpio_pin_to_addr()
139 addr->bit = pin % priv->bitcount; in sgpio_pin_to_addr()
144 return bit + port * priv->bitcount; in sgpio_addr_to_pin()
149 return (priv->properties->regoff[rno] + off) * in sgpio_get_addr()
150 regmap_get_reg_stride(priv->regs); in sgpio_get_addr()
159 ret = regmap_read(priv->regs, addr, &val); in sgpio_readl()
171 ret = regmap_write(priv->regs, addr, val); in sgpio_writel()
181 ret = regmap_update_bits(priv->regs, addr, clear | set, set); in sgpio_clrsetbits()
187 int width = priv->bitcount - 1; in sgpio_configure_bitstream()
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| /openbmc/linux/Documentation/devicetree/bindings/iio/dac/ |
| H A D | adi,ltc2688.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nuno Sá <nuno.sa@analog.com>
13 Analog Devices LTC2688 16 channel, 16 bit, +-15V DAC
14 https://www.analog.com/media/en/technical-documentation/data-sheets/ltc2688.pdf
19 - adi,ltc2688
24 vcc-supply:
27 iovcc-supply:
30 vref-supply:
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| /openbmc/u-boot/drivers/spi/ |
| H A D | pic32_spi.c | 1 // SPDX-License-Identifier: GPL-2.0+
19 #include <dt-bindings/clock/microchip,clock.h>
67 u32 speed_hz; /* spi-clk rate */
84 writel(PIC32_SPI_CTRL_ON, &priv->regs->ctrl.set); in pic32_spi_enable()
89 writel(PIC32_SPI_CTRL_ON, &priv->regs->ctrl.clr); in pic32_spi_disable()
94 u32 sr = readl(&priv->regs->status.raw); in pic32_spi_rx_fifo_level()
101 u32 sr = readl(&priv->regs->status.raw); in pic32_spi_tx_fifo_level()
111 tx_left = (priv->tx_end - priv->tx) / n_bytes; in pic32_tx_max()
112 tx_room = priv->fifo_n_word - pic32_spi_tx_fifo_level(priv); in pic32_tx_max()
114 rxtx_gap = (priv->rx_end - priv->rx) - (priv->tx_end - priv->tx); in pic32_tx_max()
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| /openbmc/linux/arch/m68k/include/asm/ |
| H A D | mcfgpio.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
28 return -EINVAL; in __gpio_get_value()
39 return -EINVAL; in __gpio_to_irq()
47 return -EINVAL; in gpio_direction_input()
55 return -EINVAL; in gpio_direction_output()
63 return -EINVAL; in gpio_request()
80 * input; some require a read-modify-write access to change an output, others
82 * GPIOs in a single control area, others have some GPIOs implemented in
130 * read-modify-write to change an output and a GPIO module which has separate
131 * set/clr registers to directly change outputs with a single write access.
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| /openbmc/linux/include/linux/gpio/ |
| H A D | driver.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
10 #include <linux/pinctrl/pinconf-generic.h>
46 * struct gpio_irq_chip - GPIO interrupt controller
76 * If non-NULL, will be set as the parent of this GPIO interrupt
88 * hardware IRQs correspond to the GPIO index 0..ngpio-1 (see the
96 * HWIRQ, return -EINVAL, but also make sure to fill in @valid_mask and
111 * &gpiochip_populate_parent_fwspec_twocell will be used. A four-cell
268 * bits from 0..(ngpios-1) set to "1" as in valid. The callback can
279 * If not %NULL, holds bitmask of GPIOs which are valid to be included
321 * struct gpio_chip - abstract a GPIO controller
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| /openbmc/linux/drivers/spi/ |
| H A D | spi-lantiq-ssc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2011-2015 Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
4 * Copyright (C) 2016 Hauke Mehrtens <hauke@hauke-m.de>
142 #define LTQ_SPI_RXCNT_TODO_M 0xFFFF /* Recevie to-do value */
191 return __raw_readl(spi->regbase + reg); in lantiq_ssc_readl()
197 __raw_writel(val, spi->regbase + reg); in lantiq_ssc_writel()
200 static void lantiq_ssc_maskl(const struct lantiq_ssc_spi *spi, u32 clr, in lantiq_ssc_maskl() argument
203 u32 val = __raw_readl(spi->regbase + reg); in lantiq_ssc_maskl()
205 val &= ~clr; in lantiq_ssc_maskl()
207 __raw_writel(val, spi->regbase + reg); in lantiq_ssc_maskl()
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