| /openbmc/linux/Documentation/devicetree/bindings/mmc/ |
| H A D | sdhci-sprd.txt | 1 * Spreadtrum SDHCI controller (sdhci-sprd)
7 and the properties used by the sdhci-sprd driver.
10 - compatible: Should contain "sprd,sdhci-r11".
11 - reg: physical base address of the controller and length.
12 - interrupts: Interrupts used by the SDHCI controller.
13 - clocks: Should contain phandle for the clock feeding the SDHCI controller
14 - clock-names: Should contain the following:
15 "sdio" - SDIO source clock (required)
16 "enable" - gate clock which used for enabling/disabling the device (required)
17 "2x_enable" - gate clock controlling the device for some special platforms (optional)
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| H A D | mtk-sd.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mtk-sd.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chaotian Jing <chaotian.jing@mediatek.com>
11 - Wenbin Mei <wenbin.mei@mediatek.com>
16 - enum:
17 - mediatek,mt2701-mmc
18 - mediatek,mt2712-mmc
19 - mediatek,mt6779-mmc
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| /openbmc/u-boot/board/xes/xpedite537x/ |
| H A D | ddr.c | 1 // SPDX-License-Identifier: GPL-2.0+
20 * There are four board-specific SDRAM timing parameters which must be
22 * 1.) CPO (Read Capture Delay)
23 * - TIMING_CFG_2 register
25 * chip-specific internal delays.
26 * 2.) WR_DATA_DELAY (Write Command to Data Strobe Delay)
27 * - TIMING_CFG_2 register
29 * Unless clock and DQ lanes are very different
31 * of 1/2 clock delay.
32 * 3.) CLK_ADJUST (Clock and Addr/Cmd alignment control)
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| /openbmc/linux/Documentation/devicetree/bindings/net/ |
| H A D | amlogic,meson-dwmac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/amlogic,meson-dwmac.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Neil Armstrong <neil.armstrong@linaro.org>
12 - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
20 - amlogic,meson6-dwmac
21 - amlogic,meson8b-dwmac
22 - amlogic,meson8m2-dwmac
23 - amlogic,meson-gxbb-dwmac
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| H A D | motorcomm,yt8xxx.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Sae <frank.sae@motor-comm.com>
13 - $ref: ethernet-phy.yaml#
18 - ethernet-phy-id4f51.e91a
19 - ethernet-phy-id4f51.e91b
21 rx-internal-delay-ps:
23 RGMII RX Clock Delay used only when PHY operates in RGMII mode with
24 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
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| H A D | adi,adin.yaml | 1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandru Tachici <alexandru.tachici@analog.com>
16 - $ref: ethernet-phy.yaml#
19 adi,rx-internal-delay-ps:
21 RGMII RX Clock Delay used only when PHY operates in RGMII mode with
22 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
26 adi,tx-internal-delay-ps:
28 RGMII TX Clock Delay used only when PHY operates in RGMII mode with
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| /openbmc/u-boot/board/freescale/mpc8548cds/ |
| H A D | ddr.c | 1 // SPDX-License-Identifier: GPL-2.0
16 * Factors to consider for clock adjust: in fsl_ddr_board_options()
17 * - number of chips on bus in fsl_ddr_board_options()
18 * - position of slot in fsl_ddr_board_options()
19 * - DDR1 vs. DDR2? in fsl_ddr_board_options()
20 * - ??? in fsl_ddr_board_options()
22 * This needs to be determined on a board-by-board basis. in fsl_ddr_board_options()
26 popts->clk_adjust = 7; in fsl_ddr_board_options()
30 * - frequency in fsl_ddr_board_options()
31 * - ddr1 vs. ddr2 in fsl_ddr_board_options()
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| /openbmc/u-boot/board/socrates/ |
| H A D | ddr.c | 1 // SPDX-License-Identifier: GPL-2.0
16 * Factors to consider for clock adjust: in fsl_ddr_board_options()
17 * - number of chips on bus in fsl_ddr_board_options()
18 * - position of slot in fsl_ddr_board_options()
19 * - DDR1 vs. DDR2? in fsl_ddr_board_options()
20 * - ??? in fsl_ddr_board_options()
22 * This needs to be determined on a board-by-board basis. in fsl_ddr_board_options()
26 popts->clk_adjust = 7; in fsl_ddr_board_options()
30 * - frequency in fsl_ddr_board_options()
31 * - ddr1 vs. ddr2 in fsl_ddr_board_options()
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| /openbmc/u-boot/board/freescale/mpc8555cds/ |
| H A D | ddr.c | 1 // SPDX-License-Identifier: GPL-2.0
16 * Factors to consider for clock adjust: in fsl_ddr_board_options()
17 * - number of chips on bus in fsl_ddr_board_options()
18 * - position of slot in fsl_ddr_board_options()
19 * - DDR1 vs. DDR2? in fsl_ddr_board_options()
20 * - ??? in fsl_ddr_board_options()
22 * This needs to be determined on a board-by-board basis. in fsl_ddr_board_options()
26 popts->clk_adjust = 6; in fsl_ddr_board_options()
30 * - frequency in fsl_ddr_board_options()
31 * - ddr1 vs. ddr2 in fsl_ddr_board_options()
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| /openbmc/u-boot/board/freescale/mpc8541cds/ |
| H A D | ddr.c | 1 // SPDX-License-Identifier: GPL-2.0
16 * Factors to consider for clock adjust: in fsl_ddr_board_options()
17 * - number of chips on bus in fsl_ddr_board_options()
18 * - position of slot in fsl_ddr_board_options()
19 * - DDR1 vs. DDR2? in fsl_ddr_board_options()
20 * - ??? in fsl_ddr_board_options()
22 * This needs to be determined on a board-by-board basis. in fsl_ddr_board_options()
26 popts->clk_adjust = 6; in fsl_ddr_board_options()
30 * - frequency in fsl_ddr_board_options()
31 * - ddr1 vs. ddr2 in fsl_ddr_board_options()
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| /openbmc/u-boot/board/freescale/mpc8568mds/ |
| H A D | ddr.c | 1 // SPDX-License-Identifier: GPL-2.0
16 * Factors to consider for clock adjust: in fsl_ddr_board_options()
17 * - number of chips on bus in fsl_ddr_board_options()
18 * - position of slot in fsl_ddr_board_options()
19 * - DDR1 vs. DDR2? in fsl_ddr_board_options()
20 * - ??? in fsl_ddr_board_options()
22 * This needs to be determined on a board-by-board basis. in fsl_ddr_board_options()
26 popts->clk_adjust = 6; in fsl_ddr_board_options()
30 * - frequency in fsl_ddr_board_options()
31 * - ddr1 vs. ddr2 in fsl_ddr_board_options()
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| /openbmc/u-boot/board/sbc8641d/ |
| H A D | ddr.c | 1 // SPDX-License-Identifier: GPL-2.0
16 * Factors to consider for clock adjust: in fsl_ddr_board_options()
17 * - number of chips on bus in fsl_ddr_board_options()
18 * - position of slot in fsl_ddr_board_options()
19 * - DDR1 vs. DDR2? in fsl_ddr_board_options()
20 * - ??? in fsl_ddr_board_options()
22 * This needs to be determined on a board-by-board basis. in fsl_ddr_board_options()
26 popts->clk_adjust = 7; in fsl_ddr_board_options()
30 * - frequency in fsl_ddr_board_options()
31 * - ddr1 vs. ddr2 in fsl_ddr_board_options()
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| /openbmc/linux/Documentation/timers/ |
| H A D | timekeeping.rst | 2 Clock sources, Clock events, sched_clock() and delay timers
10 If you grep through the kernel source you will find a number of architecture-
11 specific implementations of clock sources, clockevents and several likewise
12 architecture-specific overrides of the sched_clock() function and some
13 delay timers.
15 To provide timekeeping for your platform, the clock source provides
16 the basic timeline, whereas clock events shoot interrupts on certain points
17 on this timeline, providing facilities such as high-resolution timers.
18 sched_clock() is used for scheduling and timestamping, and delay timers
19 provide an accurate delay source using hardware counters.
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| /openbmc/u-boot/board/freescale/mpc8544ds/ |
| H A D | ddr.c | 1 // SPDX-License-Identifier: GPL-2.0
16 * Factors to consider for clock adjust: in fsl_ddr_board_options()
17 * - number of chips on bus in fsl_ddr_board_options()
18 * - position of slot in fsl_ddr_board_options()
19 * - DDR1 vs. DDR2? in fsl_ddr_board_options()
20 * - ??? in fsl_ddr_board_options()
22 * This needs to be determined on a board-by-board basis. in fsl_ddr_board_options()
26 popts->clk_adjust = 7; in fsl_ddr_board_options()
30 * - frequency in fsl_ddr_board_options()
31 * - ddr1 vs. ddr2 in fsl_ddr_board_options()
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| /openbmc/u-boot/board/freescale/mpc8610hpcd/ |
| H A D | ddr.c | 1 // SPDX-License-Identifier: GPL-2.0
16 * Factors to consider for clock adjust: in fsl_ddr_board_options()
17 * - number of chips on bus in fsl_ddr_board_options()
18 * - position of slot in fsl_ddr_board_options()
19 * - DDR1 vs. DDR2? in fsl_ddr_board_options()
20 * - ??? in fsl_ddr_board_options()
22 * This needs to be determined on a board-by-board basis. in fsl_ddr_board_options()
26 popts->clk_adjust = 7; in fsl_ddr_board_options()
30 * - frequency in fsl_ddr_board_options()
31 * - ddr1 vs. ddr2 in fsl_ddr_board_options()
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| /openbmc/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/ |
| H A D | fsl,cpm1-tsa.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PowerQUICC CPM Time-slot assigner (TSA) controller
10 - Herve Codina <herve.codina@bootlin.com>
13 The TSA is the time-slot assigner that can be found on some PowerQUICC SoC.
14 Its purpose is to route some TDM time-slots to other internal serial
20 - enum:
21 - fsl,mpc885-tsa
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| /openbmc/u-boot/board/freescale/mpc8536ds/ |
| H A D | ddr.c | 1 // SPDX-License-Identifier: GPL-2.0
16 * Factors to consider for clock adjust: in fsl_ddr_board_options()
17 * - number of chips on bus in fsl_ddr_board_options()
18 * - position of slot in fsl_ddr_board_options()
19 * - DDR1 vs. DDR2? in fsl_ddr_board_options()
20 * - ??? in fsl_ddr_board_options()
22 * This needs to be determined on a board-by-board basis. in fsl_ddr_board_options()
26 popts->clk_adjust = 7; in fsl_ddr_board_options()
30 * - frequency in fsl_ddr_board_options()
31 * - ddr1 vs. ddr2 in fsl_ddr_board_options()
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| /openbmc/u-boot/board/freescale/mpc8569mds/ |
| H A D | ddr.c | 1 // SPDX-License-Identifier: GPL-2.0
16 * Factors to consider for clock adjust: in fsl_ddr_board_options()
17 * - number of chips on bus in fsl_ddr_board_options()
18 * - position of slot in fsl_ddr_board_options()
19 * - DDR1 vs. DDR2? in fsl_ddr_board_options()
20 * - ??? in fsl_ddr_board_options()
22 * This needs to be determined on a board-by-board basis. in fsl_ddr_board_options()
26 popts->clk_adjust = 4; in fsl_ddr_board_options()
30 * - frequency in fsl_ddr_board_options()
31 * - ddr1 vs. ddr2 in fsl_ddr_board_options()
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| /openbmc/linux/Documentation/devicetree/bindings/sound/ |
| H A D | rt5682.txt | 7 - compatible : "realtek,rt5682" or "realtek,rt5682i"
9 - reg : The I2C address of the device.
11 - AVDD-supply: phandle to the regulator supplying analog power through the
14 - MICVDD-supply: phandle to the regulator supplying power for the microphone
17 - VBAT-supply: phandle to the regulator supplying battery power through the
20 - DBVDD-supply: phandle to the regulator supplying I/O power through the DBVDD
23 - LDO1-IN-supply: phandle to the regulator supplying power to the digital core
28 - interrupts : The CODEC's interrupt output.
30 - realtek,dmic1-data-pin
35 - realtek,dmic1-clk-pin
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| /openbmc/linux/Documentation/devicetree/bindings/memory-controllers/ |
| H A D | arm,pl172.txt | 5 - compatible: Must be "arm,primecell" and exactly one from
8 - reg: Must contains offset/length value for controller.
10 - #address-cells: Must be 2. The partition number has to be encoded in the
11 first address cell and it may accept values 0..N-1
12 (N - total number of partitions). The second cell is the
15 - #size-cells: Must be set to 1.
17 - ranges: Must contain one or more chip select memory regions.
19 - clocks: Must contain references to controller clocks.
21 - clock-names: Must contain "mpmcclk" and "apb_pclk".
23 - clock-ranges: Empty property indicating that child nodes can inherit
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| /openbmc/u-boot/board/xes/xpedite520x/ |
| H A D | ddr.c | 1 // SPDX-License-Identifier: GPL-2.0
19 * as a standard unregistered SO-DIMM. */ in get_spd()
20 if (spd->dimm_type == 0) { in get_spd()
21 spd->dimm_type = 0x4; in get_spd()
31 * Factors to consider for clock adjust: in fsl_ddr_board_options()
32 * - number of chips on bus in fsl_ddr_board_options()
33 * - position of slot in fsl_ddr_board_options()
34 * - DDR1 vs. DDR2? in fsl_ddr_board_options()
35 * - ??? in fsl_ddr_board_options()
37 * This needs to be determined on a board-by-board basis. in fsl_ddr_board_options()
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| /openbmc/linux/Documentation/devicetree/bindings/spi/ |
| H A D | renesas,sh-msiof.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/renesas,sh-msiof.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 - $ref: spi-controller.yaml#
18 - items:
19 - const: renesas,msiof-sh73a0 # SH-Mobile AG5
20 - const: renesas,sh-mobile-msiof # generic SH-Mobile compatible
22 - items:
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| /openbmc/linux/arch/arm64/boot/dts/qcom/ |
| H A D | ipq9574.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
5 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
9 #include <dt-bindings/clock/qcom,apss-ipq.h>
10 #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/reset/qcom,ipq9574-gcc.h>
13 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&intc>;
17 #address-cells = <2>;
18 #size-cells = <2>;
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| H A D | ipq8074.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-ipq8074.h>
10 #address-cells = <2>;
11 #size-cells = <2>;
15 interrupt-parent = <&intc>;
19 compatible = "fixed-clock";
20 clock-frequency = <32768>;
21 #clock-cells = <0>;
25 compatible = "fixed-clock";
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| /openbmc/linux/include/linux/amba/ |
| H A D | pl022.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Copyright (C) 2008-2009 ST-Ericsson AB
11 * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c
30 * enum ssp_interface - interfaces allowed for this SSP Controller
47 * enum ssp_hierarchy - whether SSP is configured as Master or Slave
55 * enum ssp_clock_params - clock parameters, to set SSP clock at a
64 * enum ssp_rx_endian - endianess of Rx FIFO Data
73 * enum ssp_tx_endian - endianess of Tx FIFO Data
81 * enum ssp_data_size - number of bits in one data element
97 * enum ssp_mode - SSP mode of operation (Communication modes)
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