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/openbmc/linux/arch/arm64/boot/dts/intel/
H A Dsocfpga_agilex5.dtsi11 #include <dt-bindings/clock/intel,agilex5-clkmgr.h>
144 clkmgr: clock-controller@10d10000 { label
145 compatible = "intel,agilex5-clkmgr";
157 clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
168 clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
179 clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
190 clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
201 clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
211 clocks = <&clkmgr AGILEX5_L4_MP_CLK>;
221 clocks = <&clkmgr AGILEX5_L4_MP_CLK>;
[all …]
H A Dsocfpga_agilex.dtsi148 clkmgr: clock-controller@ffd10000 { label
149 compatible = "intel,agilex-clkmgr";
167 clocks = <&clkmgr AGILEX_EMAC0_CLK>, <&clkmgr AGILEX_EMAC_PTP_CLK>;
185 clocks = <&clkmgr AGILEX_EMAC1_CLK>, <&clkmgr AGILEX_EMAC_PTP_CLK>;
203 clocks = <&clkmgr AGILEX_EMAC2_CLK>, <&clkmgr AGILEX_EMAC_PTP_CLK>;
255 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
266 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
277 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
288 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
299 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
[all …]
H A Dsocfpga_n5x_socdk.dts38 &clkmgr {
39 compatible = "intel,easic-n5x-clkmgr";
/openbmc/linux/arch/arm64/boot/dts/altera/
H A Dsocfpga_stratix10.dtsi143 clkmgr: clock-controller@ffd10000 { label
144 compatible = "intel,stratix10-clkmgr";
157 clocks = <&clkmgr STRATIX10_EMAC0_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>;
175 clocks = <&clkmgr STRATIX10_EMAC1_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>;
193 clocks = <&clkmgr STRATIX10_EMAC2_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>;
250 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
261 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
272 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
283 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
294 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
[all …]
H A Dsocfpga_stratix10_swvp.dts100 clocks = <&clkmgr STRATIX10_L4_MP_CLK>;
105 clocks = <&clkmgr STRATIX10_L4_MP_CLK>;
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dintel,agilex5-clkmgr.yaml4 $id: http://devicetree.org/schemas/clock/intel,agilex5-clkmgr.yaml#
18 const: intel,agilex5-clkmgr
35 clkmgr: clock-controller@10d10000 {
36 compatible = "intel,agilex5-clkmgr";
H A Dintel,easic-n5x.yaml18 const: intel,easic-n5x-clkmgr
40 clkmgr: clock-controller@ffd10000 {
41 compatible = "intel,easic-n5x-clkmgr";
H A Dintel,agilex.yaml18 const: intel,agilex-clkmgr
40 clkmgr: clock-controller@ffd10000 {
41 compatible = "intel,agilex-clkmgr";
H A Dintel,stratix10.yaml14 const: intel,stratix10-clkmgr
32 compatible = "intel,stratix10-clkmgr";
/openbmc/linux/Documentation/devicetree/bindings/arm/altera/
H A Dsocfpga-clk-manager.yaml28 clkmgr@ffd04000 {
/openbmc/u-boot/arch/arm/dts/
H A Dsocfpga_arria5.dtsi13 clkmgr@ffd04000 {
H A Dsocfpga_cyclone5.dtsi13 clkmgr@ffd04000 {
H A Dsocfpga_stratix10.dtsi85 clkmgr@ffd1000 {
H A Dsocfpga_arria10.dtsi99 clkmgr@ffd04000 {
H A Dsocfpga.dtsi114 clkmgr@ffd04000 {
/openbmc/linux/arch/arm/boot/dts/intel/socfpga/
H A Dsocfpga_arria5.dtsi13 clkmgr@ffd04000 {
H A Dsocfpga_cyclone5.dtsi13 clkmgr@ffd04000 {
H A Dsocfpga_vt.dts24 clkmgr@ffd04000 {
H A Dsocfpga_arria10_socdk.dtsi59 clkmgr@ffd04000 {
H A Dsocfpga_arria10.dtsi91 clkmgr@ffd04000 {
/openbmc/linux/drivers/clk/socfpga/
H A Dclk-agilex.c546 { .compatible = "intel,agilex-clkmgr",
548 { .compatible = "intel,easic-n5x-clkmgr",
556 .name = "agilex-clkmgr",
H A Dclk-s10.c433 { .compatible = "intel,stratix10-clkmgr",
441 .name = "stratix10-clkmgr",
/openbmc/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dclock_manager_arria10.h74 /* clkmgr */
/openbmc/u-boot/include/configs/
H A Dsocfpga_stratix10_socdk.h111 "fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency " \
/openbmc/qemu/hw/riscv/
H A Dopentitan.c273 create_unimplemented_device("riscv.lowrisc.ibex.clkmgr", in lowrisc_ibex_soc_realize()

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