1*d5f0942bSNiravkumar L Rabara# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*d5f0942bSNiravkumar L Rabara%YAML 1.2 3*d5f0942bSNiravkumar L Rabara--- 4*d5f0942bSNiravkumar L Rabara$id: http://devicetree.org/schemas/clock/intel,agilex5-clkmgr.yaml# 5*d5f0942bSNiravkumar L Rabara$schema: http://devicetree.org/meta-schemas/core.yaml# 6*d5f0942bSNiravkumar L Rabara 7*d5f0942bSNiravkumar L Rabaratitle: Intel SoCFPGA Agilex5 clock manager 8*d5f0942bSNiravkumar L Rabara 9*d5f0942bSNiravkumar L Rabaramaintainers: 10*d5f0942bSNiravkumar L Rabara - Dinh Nguyen <dinguyen@kernel.org> 11*d5f0942bSNiravkumar L Rabara 12*d5f0942bSNiravkumar L Rabaradescription: 13*d5f0942bSNiravkumar L Rabara The Intel Agilex5 Clock Manager is an integrated clock controller, which 14*d5f0942bSNiravkumar L Rabara generates and supplies clock to all the modules. 15*d5f0942bSNiravkumar L Rabara 16*d5f0942bSNiravkumar L Rabaraproperties: 17*d5f0942bSNiravkumar L Rabara compatible: 18*d5f0942bSNiravkumar L Rabara const: intel,agilex5-clkmgr 19*d5f0942bSNiravkumar L Rabara 20*d5f0942bSNiravkumar L Rabara reg: 21*d5f0942bSNiravkumar L Rabara maxItems: 1 22*d5f0942bSNiravkumar L Rabara 23*d5f0942bSNiravkumar L Rabara '#clock-cells': 24*d5f0942bSNiravkumar L Rabara const: 1 25*d5f0942bSNiravkumar L Rabara 26*d5f0942bSNiravkumar L Rabararequired: 27*d5f0942bSNiravkumar L Rabara - compatible 28*d5f0942bSNiravkumar L Rabara - reg 29*d5f0942bSNiravkumar L Rabara - '#clock-cells' 30*d5f0942bSNiravkumar L Rabara 31*d5f0942bSNiravkumar L RabaraadditionalProperties: false 32*d5f0942bSNiravkumar L Rabara 33*d5f0942bSNiravkumar L Rabaraexamples: 34*d5f0942bSNiravkumar L Rabara - | 35*d5f0942bSNiravkumar L Rabara clkmgr: clock-controller@10d10000 { 36*d5f0942bSNiravkumar L Rabara compatible = "intel,agilex5-clkmgr"; 37*d5f0942bSNiravkumar L Rabara reg = <0x10d10000 0x1000>; 38*d5f0942bSNiravkumar L Rabara #clock-cells = <1>; 39*d5f0942bSNiravkumar L Rabara }; 40*d5f0942bSNiravkumar L Rabara... 41