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Searched full:clk_div (Results 1 – 25 of 123) sorted by relevance

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/openbmc/linux/drivers/pwm/
H A Dpwm-crc.c44 int clk_div; in crc_pwm_calc_clk_div() local
46 clk_div = PWM_BASE_CLK_MHZ * period_ns / (256 * NSEC_PER_USEC); in crc_pwm_calc_clk_div()
47 /* clk_div 1 - 128, maps to register values 0-127 */ in crc_pwm_calc_clk_div()
48 if (clk_div > 0) in crc_pwm_calc_clk_div()
49 clk_div--; in crc_pwm_calc_clk_div()
51 return clk_div; in crc_pwm_calc_clk_div()
102 int clk_div = crc_pwm_calc_clk_div(state->period); in crc_pwm_apply() local
106 clk_div | pwm_output_enable); in crc_pwm_apply()
129 unsigned int clk_div, clk_div_reg, duty_cycle_reg; in crc_pwm_get_state() local
144 clk_div = (clk_div_reg & ~PWM_OUTPUT_ENABLE) + 1; in crc_pwm_get_state()
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H A Dpwm-mtk-disp.c74 u32 clk_div, period, high_width, value; in mtk_disp_pwm_apply() local
109 * Find period, high_width and clk_div to suit duty_ns and period_ns. in mtk_disp_pwm_apply()
112 * period_ns = 10^9 * (clk_div + 1) * (period + 1) / PWM_CLK_RATE in mtk_disp_pwm_apply()
113 * duty_ns = 10^9 * (clk_div + 1) * high_width / PWM_CLK_RATE in mtk_disp_pwm_apply()
115 * period = (PWM_CLK_RATE * period_ns) / (10^9 * (clk_div + 1)) - 1 in mtk_disp_pwm_apply()
116 * high_width = (PWM_CLK_RATE * duty_ns) / (10^9 * (clk_div + 1)) in mtk_disp_pwm_apply()
119 clk_div = mul_u64_u64_div_u64(state->period, rate, NSEC_PER_SEC) >> in mtk_disp_pwm_apply()
121 if (clk_div > PWM_CLKDIV_MAX) { in mtk_disp_pwm_apply()
129 div = NSEC_PER_SEC * (clk_div + 1); in mtk_disp_pwm_apply()
152 clk_div << PWM_CLKDIV_SHIFT); in mtk_disp_pwm_apply()
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/openbmc/linux/drivers/clk/mxs/
H A Dclk-div.c12 * struct clk_div - mxs integer divider clock
21 struct clk_div { struct
28 static inline struct clk_div *to_clk_div(struct clk_hw *hw) in to_clk_div() argument
32 return container_of(divider, struct clk_div, divider); in to_clk_div()
38 struct clk_div *div = to_clk_div(hw); in clk_div_recalc_rate()
46 struct clk_div *div = to_clk_div(hw); in clk_div_round_rate()
54 struct clk_div *div = to_clk_div(hw); in clk_div_set_rate()
73 struct clk_div *div; in mxs_clk_div()
/openbmc/linux/drivers/net/ethernet/xilinx/
H A Dxilinx_axienet_mdio.c162 u32 clk_div; in axienet_mdio_enable() local
198 /* clk_div can be calculated by deriving it from the equation: in axienet_mdio_enable()
199 * fMDIO = fHOST / ((1 + clk_div) * 2) in axienet_mdio_enable()
202 * fHOST / ((1 + clk_div) * 2) <= 2500000 in axienet_mdio_enable()
205 * 1 / ((1 + clk_div) * 2) <= (2500000 / fHOST) in axienet_mdio_enable()
208 * 1 / (1 + clk_div) <= ((2500000 * 2) / fHOST) in axienet_mdio_enable()
211 * 1 / (1 + clk_div) <= (5000000 / fHOST) in axienet_mdio_enable()
214 * (1 + clk_div) >= (fHOST / 5000000) in axienet_mdio_enable()
217 * clk_div >= (fHOST / 5000000) - 1 in axienet_mdio_enable()
223 clk_div = (host_clock / (mdio_freq * 2)) - 1; in axienet_mdio_enable()
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H A Dll_temac_mdio.c70 int clk_div; in temac_mdio_setup() local
82 clk_div = 0x3f; /* worst-case default setting */ in temac_mdio_setup()
84 clk_div = bus_hz / (2500 * 1000 * 2) - 1; in temac_mdio_setup()
85 if (clk_div < 1) in temac_mdio_setup()
86 clk_div = 1; in temac_mdio_setup()
87 if (clk_div > 0x3f) in temac_mdio_setup()
88 clk_div = 0x3f; in temac_mdio_setup()
94 temac_indirect_out32(lp, XTE_MC_OFFSET, 1 << 6 | clk_div); in temac_mdio_setup()
/openbmc/linux/drivers/mfd/
H A Dfsl-imx25-tsadc.c103 unsigned clk_div; in mx25_tsadc_setup_clk() local
115 clk_div = DIV_ROUND_UP(clk_get_rate(tsadc->clk), 1750000); in mx25_tsadc_setup_clk()
116 dev_dbg(&pdev->dev, "Setting up ADC clock divider to %u\n", clk_div); in mx25_tsadc_setup_clk()
119 clk_div -= 2; in mx25_tsadc_setup_clk()
120 clk_div /= 2; in mx25_tsadc_setup_clk()
126 clk_div = max_t(unsigned, 4, clk_div); in mx25_tsadc_setup_clk()
129 clk_get_rate(tsadc->clk) / (2 * clk_div + 2)); in mx25_tsadc_setup_clk()
133 MX25_TGCR_ADCCLKCFG(clk_div)); in mx25_tsadc_setup_clk()
/openbmc/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dclock.h64 uint clk_div; in clk_get_divisor() local
66 clk_div = input_rate / output_rate; in clk_get_divisor()
67 clk_div = (clk_div + 1) & 0xfffe; in clk_get_divisor()
69 return clk_div; in clk_get_divisor()
/openbmc/linux/drivers/spi/
H A Dspi-axi-spi-engine.c143 unsigned int clk_div; in spi_engine_get_clk_div() local
145 clk_div = DIV_ROUND_UP(clk_get_rate(spi_engine->ref_clk), in spi_engine_get_clk_div()
147 if (clk_div > 255) in spi_engine_get_clk_div()
148 clk_div = 255; in spi_engine_get_clk_div()
149 else if (clk_div > 0) in spi_engine_get_clk_div()
150 clk_div -= 1; in spi_engine_get_clk_div()
152 return clk_div; in spi_engine_get_clk_div()
176 struct spi_engine *spi_engine, unsigned int clk_div, in spi_engine_gen_sleep() argument
191 t = DIV_ROUND_UP(delay * spi_clk, (clk_div + 1) * 2); in spi_engine_gen_sleep()
216 int clk_div, new_clk_div; in spi_engine_compile_message() local
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H A Dspi-hisi-kunpeng.c117 u16 clk_div; /* baud rate divider */ member
119 /* clk_div = (1 + div_post) * div_pre */
280 if (chip->clk_div % chip->div_pre == 0) in __hisi_calc_div_reg()
286 if (chip->div_pre > chip->clk_div) in __hisi_calc_div_reg()
287 chip->div_pre = chip->clk_div; in __hisi_calc_div_reg()
289 chip->div_post = (chip->clk_div / chip->div_pre) - 1; in __hisi_calc_div_reg()
298 chip->clk_div = DIV_ROUND_UP(host->max_speed_hz, speed_hz) + 1; in hisi_calc_effective_speed()
299 chip->clk_div &= 0xfffe; in hisi_calc_effective_speed()
300 if (chip->clk_div > CLK_DIV_MAX) in hisi_calc_effective_speed()
301 chip->clk_div = CLK_DIV_MAX; in hisi_calc_effective_speed()
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/openbmc/linux/arch/mips/ath25/
H A Dar2315.c208 unsigned int clk_div; in ar2315_sys_clk() local
221 clk_div = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_CLKM_DIV); in ar2315_sys_clk()
222 clk_div = pllc_divide_table[clk_div]; in ar2315_sys_clk()
225 clk_div = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_CLKC_DIV); in ar2315_sys_clk()
226 clk_div = pllc_divide_table[clk_div]; in ar2315_sys_clk()
230 clk_div = 1; in ar2315_sys_clk()
237 return pllc_out / (clk_div * cpu_div); in ar2315_sys_clk()
/openbmc/linux/include/linux/dma/
H A Dqcom-gpi-dma.h26 * @clk_div: source clock divider
43 u32 clk_div; member
61 * @clk_div: source clock divider
77 u16 clk_div; member
/openbmc/linux/sound/soc/ti/
H A Ddavinci-i2s.c161 int clk_div; member
372 dev->clk_div = div; in davinci_i2s_dai_set_clkdiv()
383 unsigned int rcr, xcr, srgr, clk_div, freq, framesize; in davinci_i2s_hw_params() local
410 clk_div = 256; in davinci_i2s_hw_params()
412 framesize = (freq / (--clk_div)) / in davinci_i2s_hw_params()
416 (clk_div)); in davinci_i2s_hw_params()
417 clk_div--; in davinci_i2s_hw_params()
421 clk_div = freq / (mcbsp_word_length * 16) / in davinci_i2s_hw_params()
426 clk_div &= 0xFF; in davinci_i2s_hw_params()
427 srgr |= clk_div; in davinci_i2s_hw_params()
[all …]
/openbmc/linux/drivers/i2c/busses/
H A Di2c-sun6i-p2wi.c192 int clk_div; in p2wi_probe() local
286 clk_div = parent_clk_freq / clk_freq; in p2wi_probe()
287 if (!clk_div) { in p2wi_probe()
291 clk_div = 1; in p2wi_probe()
292 } else if (clk_div > P2WI_CCR_MAX_CLK_DIV) { in p2wi_probe()
296 clk_div = P2WI_CCR_MAX_CLK_DIV; in p2wi_probe()
299 writel(P2WI_CCR_SDA_OUT_DELAY(1) | P2WI_CCR_CLK_DIV(clk_div), in p2wi_probe()
H A Di2c-mt7621.c65 u32 clk_div; member
96 iowrite32(((i2c->clk_div << 16) & SM0CTL0_CLK_DIV_MASK) | SM0CTL0_EN | in mtk_i2c_reset()
263 i2c->clk_div = clk_get_rate(i2c->clk) / i2c->bus_freq - 1; in mtk_i2c_init()
264 if (i2c->clk_div < 99) in mtk_i2c_init()
265 i2c->clk_div = 99; in mtk_i2c_init()
266 if (i2c->clk_div > SM0CTL0_CLK_DIV_MAX) in mtk_i2c_init()
267 i2c->clk_div = SM0CTL0_CLK_DIV_MAX; in mtk_i2c_init()
H A Di2c-pasemi-platform.c32 data->smbus.clk_div = DIV_ROUND_UP(clk_rate, 16 * frequency); in pasemi_platform_i2c_calc_clk_div()
33 if (data->smbus.clk_div < 4) in pasemi_platform_i2c_calc_clk_div()
37 if (data->smbus.clk_div > 0xff) in pasemi_platform_i2c_calc_clk_div()
/openbmc/linux/drivers/clk/
H A Dclk-versaclock3.c601 static struct vc3_hw_data clk_div[5]; variable
605 { .hw = &clk_div[VC3_DIV2].hw }
805 static struct vc3_hw_data clk_div[] = { variable
908 &clk_div[VC3_DIV5].hw,
909 &clk_div[VC3_DIV4].hw
924 &clk_div[VC3_DIV5].hw,
925 &clk_div[VC3_DIV4].hw
940 &clk_div[VC3_DIV2].hw,
941 &clk_div[VC3_DIV4].hw
956 &clk_div[VC3_DIV1].hw,
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/openbmc/u-boot/drivers/spi/
H A Drk_spi.c83 uint clk_div = DIV_ROUND_UP(priv->input_rate, speed); in rkspi_set_clk() local
92 if (clk_div > 0xfffe) { in rkspi_set_clk()
93 clk_div = 0xfffe; in rkspi_set_clk()
95 __func__, speed, priv->input_rate / clk_div); in rkspi_set_clk()
99 clk_div = (clk_div + 1) & 0xfffe; in rkspi_set_clk()
101 debug("spi speed %u, div %u\n", speed, clk_div); in rkspi_set_clk()
103 clrsetbits_le32(&priv->regs->baudr, 0xffff, clk_div); in rkspi_set_clk()
H A Ddesignware_spi.c484 u16 clk_div; in dw_spi_set_speed() local
492 /* clk_div doesn't support odd number */ in dw_spi_set_speed()
493 clk_div = priv->bus_clk_rate / speed; in dw_spi_set_speed()
494 clk_div = (clk_div + 1) & 0xfffe; in dw_spi_set_speed()
495 dw_write(priv, DW_SPI_BAUDR, clk_div); in dw_spi_set_speed()
501 debug("%s: regs=%p speed=%d clk_div=%d\n", __func__, priv->regs, in dw_spi_set_speed()
502 priv->freq, clk_div); in dw_spi_set_speed()
H A Dti_qspi.c118 uint clk_div; in ti_spi_set_speed() local
121 clk_div = 0; in ti_spi_set_speed()
123 clk_div = DIV_ROUND_UP(priv->fclk, hz) - 1; in ti_spi_set_speed()
125 /* truncate clk_div value to QSPI_CLK_DIV_MAX */ in ti_spi_set_speed()
126 if (clk_div > QSPI_CLK_DIV_MAX) in ti_spi_set_speed()
127 clk_div = QSPI_CLK_DIV_MAX; in ti_spi_set_speed()
129 debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div); in ti_spi_set_speed()
135 writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl); in ti_spi_set_speed()
/openbmc/linux/sound/soc/sti/
H A Duniperif_player.c316 int clk_div; in uni_player_prepare_iec958() local
318 clk_div = player->mclk / runtime->rate; in uni_player_prepare_iec958()
321 if ((clk_div % 128) || (clk_div <= 0)) { in uni_player_prepare_iec958()
322 dev_err(player->dev, "%s: invalid clk_div %d\n", in uni_player_prepare_iec958()
323 __func__, clk_div); in uni_player_prepare_iec958()
398 SET_UNIPERIF_CTRL_DIVIDER(player, clk_div / 128); in uni_player_prepare_iec958()
419 int output_frame_size, slot_width, clk_div; in uni_player_prepare_pcm() local
430 clk_div = player->mclk / runtime->rate; in uni_player_prepare_pcm()
432 * For 32 bits subframe clk_div must be a multiple of 128, in uni_player_prepare_pcm()
435 if ((slot_width == 32) && (clk_div % 128)) { in uni_player_prepare_pcm()
[all …]
/openbmc/u-boot/drivers/video/sunxi/
H A Dsunxi_lcd.c46 int clk_div, clk_double, ret; in sunxi_lcd_enable() local
56 &clk_div, &clk_double, false); in sunxi_lcd_enable()
57 lcdc_tcon0_mode_set(lcdc, edid, clk_div, false, in sunxi_lcd_enable()
/openbmc/u-boot/drivers/led/
H A Dled_bcm6358.c119 unsigned int clk_div; in bcm6358_led_probe() local
128 clk_div = dev_read_u32_default(dev, "brcm,clk-div", in bcm6358_led_probe()
130 switch (clk_div) { in bcm6358_led_probe()
/openbmc/linux/sound/soc/codecs/
H A Dlpass-va-macro.c602 u8 clk_div; in va_dmic_clk_enable() local
640 clk_div = va->dmic_clk_div; in va_dmic_clk_enable()
649 clk_div << CDC_VA_DMIC_CLK_SEL_SHFT); in va_dmic_clk_enable()
654 if (*dmic_clk_div > clk_div) { in va_dmic_clk_enable()
661 clk_div << CDC_VA_DMIC_CLK_SEL_SHFT); in va_dmic_clk_enable()
667 clk_div = *dmic_clk_div; in va_dmic_clk_enable()
670 *dmic_clk_div = clk_div; in va_dmic_clk_enable()
676 clk_div = 0; in va_dmic_clk_enable()
679 clk_div << CDC_VA_DMIC_CLK_SEL_SHFT); in va_dmic_clk_enable()
681 clk_div = va->dmic_clk_div; in va_dmic_clk_enable()
[all …]
/openbmc/linux/drivers/bus/
H A Dsunxi-rsb.c655 int clk_div, ret; in sunxi_rsb_hw_init() local
682 clk_div = p_clk_freq / rsb->clk_freq / 2; in sunxi_rsb_hw_init()
683 if (!clk_div) in sunxi_rsb_hw_init()
684 clk_div = 1; in sunxi_rsb_hw_init()
685 else if (clk_div > RSB_CCR_MAX_CLK_DIV + 1) in sunxi_rsb_hw_init()
686 clk_div = RSB_CCR_MAX_CLK_DIV + 1; in sunxi_rsb_hw_init()
688 clk_delay = clk_div >> 1; in sunxi_rsb_hw_init()
692 dev_info(dev, "RSB running at %lu Hz\n", p_clk_freq / clk_div / 2); in sunxi_rsb_hw_init()
693 writel(RSB_CCR_SDA_OUT_DELAY(clk_delay) | RSB_CCR_CLK_DIV(clk_div - 1), in sunxi_rsb_hw_init()
/openbmc/linux/drivers/leds/
H A Dleds-bcm6358.c154 u32 clk_div; in bcm6358_leds_probe() local
170 of_property_read_u32(np, "brcm,clk-div", &clk_div); in bcm6358_leds_probe()
171 switch (clk_div) { in bcm6358_leds_probe()

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