Lines Matching full:clk_div
74 u32 clk_div, period, high_width, value; in mtk_disp_pwm_apply() local
109 * Find period, high_width and clk_div to suit duty_ns and period_ns. in mtk_disp_pwm_apply()
112 * period_ns = 10^9 * (clk_div + 1) * (period + 1) / PWM_CLK_RATE in mtk_disp_pwm_apply()
113 * duty_ns = 10^9 * (clk_div + 1) * high_width / PWM_CLK_RATE in mtk_disp_pwm_apply()
115 * period = (PWM_CLK_RATE * period_ns) / (10^9 * (clk_div + 1)) - 1 in mtk_disp_pwm_apply()
116 * high_width = (PWM_CLK_RATE * duty_ns) / (10^9 * (clk_div + 1)) in mtk_disp_pwm_apply()
119 clk_div = mul_u64_u64_div_u64(state->period, rate, NSEC_PER_SEC) >> in mtk_disp_pwm_apply()
121 if (clk_div > PWM_CLKDIV_MAX) { in mtk_disp_pwm_apply()
129 div = NSEC_PER_SEC * (clk_div + 1); in mtk_disp_pwm_apply()
152 clk_div << PWM_CLKDIV_SHIFT); in mtk_disp_pwm_apply()
179 u32 clk_div, pwm_en, con0, con1; in mtk_disp_pwm_get_state() local
210 clk_div = FIELD_GET(PWM_CLKDIV_MASK, con0); in mtk_disp_pwm_get_state()
213 * period has 12 bits, clk_div 11 and NSEC_PER_SEC has 30, in mtk_disp_pwm_get_state()
214 * so period * (clk_div + 1) * NSEC_PER_SEC doesn't overflow. in mtk_disp_pwm_get_state()
216 state->period = DIV64_U64_ROUND_UP(period * (clk_div + 1) * NSEC_PER_SEC, rate); in mtk_disp_pwm_get_state()
218 state->duty_cycle = DIV64_U64_ROUND_UP(high_width * (clk_div + 1) * NSEC_PER_SEC, in mtk_disp_pwm_get_state()