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/openbmc/u-boot/arch/arm/dts/
H A Dexynos5250.dtsi1 // SPDX-License-Identifier: GPL-2.0+
8 #include "exynos5250-pinctrl.dtsi"
9 #include "exynos5250-pinctrl-uboot.dtsi"
20 compatible = "samsung,exynos5250-pinctrl";
24 wakup_eint: wakeup-interrupt-controller {
25 compatible = "samsung,exynos4210-wakeup-eint";
26 interrupt-parent = <&gic>;
32 compatible = "samsung,exynos5250-pinctrl";
38 compatible = "samsung,exynos5250-pinctrl";
44 compatible = "samsung,exynos5250-pinctrl";
[all …]
H A Dfsl-imx8mq.dtsi16 #include "fsl-imx8-ca53.dtsi"
17 #include <dt-bindings/clock/imx8mq-clock.h>
18 #include <dt-bindings/gpio/gpio.h>
19 #include <dt-bindings/input/input.h>
20 #include <dt-bindings/interrupt-controller/arm-gic.h>
21 #include <dt-bindings/pinctrl/pins-imx8mq.h>
22 #include <dt-bindings/thermal/thermal.h>
26 interrupt-parent = <&gpc>;
27 #address-cells = <2>;
28 #size-cells = <2>;
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H A Dstm32f429.dtsi2 * Copyright (C) 2015, STMicroelectronics - All Rights Reserved
5 * This file is dual-licensed: you can use it either under the terms
45 #include "armv7-m.dtsi"
46 #include <dt-bindings/clock/stm32fx-clock.h>
47 #include <dt-bindings/mfd/stm32f4-rcc.h>
51 clk_hse: clk-hse {
52 #clock-cells = <0>;
53 compatible = "fixed-clock";
54 clock-frequency = <0>;
57 clk_lse: clk-lse {
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H A Dstm32mp157c.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/stm32mp1-clks.h>
8 #include <dt-bindings/reset/stm32mp1-resets.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "arm,cortex-a7";
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H A Dexynos54xx.dtsi1 // SPDX-License-Identifier: GPL-2.0+
8 #include "exynos54xx-pinctrl.dtsi"
12 machine-arch-id = <4151>;
45 compatible = "samsung,exynos-adc-v2";
52 #address-cells = <1>;
53 #size-cells = <0>;
54 compatible = "samsung,exynos5-hsi2c";
60 #address-cells = <1>;
61 #size-cells = <0>;
62 compatible = "samsung,exynos5-hsi2c";
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H A Dam335x-brppt1-nand.dts1 // SPDX-License-Identifier: GPL-2.0+
4 * http://www.br-automation.com
7 /dts-v1/;
15 fset: factory-settings {
16 bl-version = "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456890";
18 order-no = "6PPT30 (NAND)";
19 hw-revision = "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456890";
20 serial-no = "0";
21 device-id = <0x0>;
22 parent-id = <0x0>;
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H A Dat91sam9n12.dtsi2 * at91sam9n12.dtsi - Device Tree include file for AT91SAM9N12 SoC
11 #include <dt-bindings/dma/at91.h>
12 #include <dt-bindings/pinctrl/at91.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/clock/at91.h>
20 interrupt-parent = <&aic>;
42 compatible = "arm,arm926ej-s";
53 compatible = "fixed-clock";
54 #clock-cells = <0>;
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H A Drk3128.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/pinctrl/rockchip.h>
10 #include <dt-bindings/clock/rk3128-cru.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <1>;
42 arm-pmu {
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H A Drk3368.dtsi4 * This file is dual-licensed: you can use it either under the terms
43 #include <dt-bindings/clock/rk3368-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/irq.h>
46 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/thermal/thermal.h>
49 #include <dt-bindings/memory/rk3368-dmc.h>
53 interrupt-parent = <&gic>;
54 #address-cells = <2>;
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H A Dmeson-gxbb-odroidc2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include "meson-gxbb.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
14 compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb";
15 model = "Hardkernel ODROID-C2";
23 stdout-path = "serial0:115200n8";
31 usb_otg_pwr: regulator-usb-pwrs {
32 compatible = "regulator-fixed";
34 regulator-name = "USB_OTG_PWR";
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H A Dat91sam9rl.dtsi2 * at91sam9rl.dtsi - Device Tree Include file for AT91SAM9RL family SoC
4 * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
10 #include <dt-bindings/pinctrl/at91.h>
11 #include <dt-bindings/clock/at91.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/pwm/pwm.h>
19 interrupt-parent = <&aic>;
42 compatible = "arm,arm926ej-s";
53 compatible = "fixed-clock";
[all …]
H A Drk322x.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/pinctrl/rockchip.h>
10 #include <dt-bindings/clock/rk3228-cru.h>
11 #include <dt-bindings/thermal/thermal.h>
14 #address-cells = <1>;
15 #size-cells = <1>;
17 interrupt-parent = <&gic>;
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/openbmc/u-boot/drivers/pwm/
H A Drk_pwm.c1 // SPDX-License-Identifier: GPL-2.0+
8 #include <clk.h>
11 #include <pwm.h>
15 #include <asm/arch/pwm.h>
29 priv->enable_conf &= ~(PWM_DUTY_MASK | PWM_INACTIVE_MASK); in rk_pwm_set_invert()
31 priv->enable_conf |= PWM_DUTY_NEGATIVE | PWM_INACTIVE_POSTIVE; in rk_pwm_set_invert()
33 priv->enable_conf |= PWM_DUTY_POSTIVE | PWM_INACTIVE_NEGATIVE; in rk_pwm_set_invert()
42 struct rk3288_pwm *regs = priv->regs; in rk_pwm_set_config()
47 PWM_CONTINUOUS | priv->enable_conf | in rk_pwm_set_config()
49 &regs->ctrl); in rk_pwm_set_config()
[all …]
H A Dexynos_pwm.c1 // SPDX-License-Identifier: GPL-2.0+
8 #include <pwm.h>
10 #include <asm/arch/clk.h>
12 #include <asm/arch/pwm.h>
22 struct s5p_timer *regs = priv->regs; in exynos_pwm_set_config()
29 return -EINVAL; in exynos_pwm_set_config()
31 __func__, dev->name, channel, period_ns, duty_ns); in exynos_pwm_set_config()
33 val = readl(&regs->tcfg0); in exynos_pwm_set_config()
35 div = (readl(&regs->tcfg1) >> MUX_DIV_SHIFT(channel)) & 0xf; in exynos_pwm_set_config()
46 writel(tcnt, &regs->tcntb0 + offset); in exynos_pwm_set_config()
[all …]
/openbmc/qemu/tests/qtest/
H A Dnpcm7xx_pwm-test.c2 * QTests for Nuvoton NPCM7xx PWM Modules.
39 /* CLK module related */
58 /* MFT (PWM fan) related */
106 typedef struct PWM { struct
111 } PWM; typedef
115 const PWM *pwm; member
129 static const PWM pwm_list[] = {
201 /* Returns the index of the PWM module. */
204 ptrdiff_t diff = module - pwm_module_list; in pwm_module_index()
211 /* Returns the index of the PWM entry. */
[all …]
/openbmc/u-boot/arch/arm/cpu/armv7/s5p-common/
H A Dpwm.c1 // SPDX-License-Identifier: GPL-2.0+
10 #include <pwm.h>
12 #include <asm/arch/pwm.h>
13 #include <asm/arch/clk.h>
17 const struct s5p_timer *pwm = in pwm_enable() local
21 tcon = readl(&pwm->tcon); in pwm_enable()
24 writel(tcon, &pwm->tcon); in pwm_enable()
31 const struct s5p_timer *pwm = in pwm_disable() local
35 tcon = readl(&pwm->tcon); in pwm_disable()
38 writel(tcon, &pwm->tcon); in pwm_disable()
[all …]
H A Dtimer.c1 // SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/pwm.h>
13 #include <asm/arch/clk.h>
15 /* Use the old PWM interface for now */
17 #include <pwm.h>
42 return readl(&timer->tcnto4); in timer_get_us_down()
47 /* PWM Timer 4 */ in timer_init()
53 gd->arch.timer_reset_value = 0; in timer_init()
56 gd->arch.lastinc = timer_get_us_down(); in timer_init()
76 gd->arch.timer_reset_value += gd->arch.lastinc - now; in get_timer()
[all …]
/openbmc/u-boot/arch/arc/dts/
H A Dhsdk.dts1 // SPDX-License-Identifier: GPL-2.0+
5 /dts-v1/;
8 #include "dt-bindings/clock/snps,hsdk-cgu.h"
13 #address-cells = <1>;
14 #size-cells = <1>;
23 #clock-cells = <0>;
24 compatible = "fixed-clock";
25 clock-frequency = <500000000>;
26 u-boot,dm-pre-reloc;
30 clk-fmeas {
[all …]
/openbmc/qemu/hw/arm/
H A Dnpcm8xx.c23 #include "hw/char/serial-mm.h"
27 #include "hw/qdev-clock.h"
28 #include "hw/qdev-properties.h"
84 * Interrupt lines going into the GIC. This does not include internal Cortex-A35
119 NPCM8XX_PWM0_IRQ = 93, /* PWM module 0 */
120 NPCM8XX_PWM1_IRQ, /* PWM module 1 */
175 /* Total number of GIC interrupts, including internal Cortex-A35 interrupts. */
178 ((NPCM8XX_NUM_IRQ - GIC_INTERNAL) + (cpu) * GIC_INTERNAL)
198 /* Direct memory-mapped access to SPI0 CS0-1. */
204 /* Direct memory-mapped access to SPI1 CS0-3. */
[all …]
H A Dnpcm7xx.c21 #include "hw/char/serial-mm.h"
24 #include "hw/qdev-clock.h"
25 #include "hw/qdev-properties.h"
30 #include "target/arm/cpu-qom.h"
79 * Interrupt lines going into the GIC. This does not include internal Cortex-A9
131 NPCM7XX_PWM0_IRQ = 93, /* PWM module 0 */
132 NPCM7XX_PWM1_IRQ, /* PWM module 1 */
153 /* Total number of GIC interrupts, including internal Cortex-A9 interrupts. */
171 /* Direct memory-mapped access to SPI0 CS0-1. */
177 /* Direct memory-mapped access to SPI3 CS0-3. */
[all …]
/openbmc/u-boot/arch/sandbox/dts/
H A Dtest.dts1 /dts-v1/;
6 #address-cells = <1>;
7 #size-cells = <1>;
27 testfdt6 = "/e-test";
28 testbus3 = "/some-bus";
29 testfdt0 = "/some-bus/c-test@0";
30 testfdt1 = "/some-bus/c-test@1";
31 testfdt3 = "/b-test";
32 testfdt5 = "/some-bus/c-test@5";
33 testfdt8 = "/a-test";
[all …]
/openbmc/qemu/include/hw/arm/
H A Dnpcm8xx.h20 #include "hw/core/split-irq.h"
37 #include "hw/usb/hcd-ehci.h"
38 #include "hw/usb/hcd-ohci.h"
60 * PWM fan splitter. each splitter connects to one PWM output and
90 NPCMCLKState clk; member
93 NPCM7xxPWMState pwm[NPCM8XX_NR_PWM_MODULES]; member
122 * npcm8xx_load_kernel - Loads memory with everything needed to boot
123 * @machine - The machine containing the SoC to be booted.
124 * @soc - The SoC containing the CPU to be booted.
H A Dnpcm7xx.h21 #include "hw/core/split-irq.h"
37 #include "hw/usb/hcd-ehci.h"
38 #include "hw/usb/hcd-ohci.h"
60 * PWM fan splitter. each splitter connects to one PWM output and
93 NPCMCLKState clk; member
96 NPCM7xxPWMState pwm[NPCM7XX_NR_PWM_MODULES]; member
129 * npcm7xx_load_kernel - Loads memory with everything needed to boot
130 * @machine - The machine containing the SoC to be booted.
131 * @soc - The SoC containing the CPU to be booted.
/openbmc/qemu/hw/timer/
H A Dstellaris-gptm.c15 #include "hw/qdev-clock.h"
16 #include "hw/timer/stellaris-gptm.h"
21 level = (s->state & s->mask) != 0; in gptm_update_irq()
22 qemu_set_irq(s->irq, level); in gptm_update_irq()
27 timer_del(s->timer[n]); in gptm_stop()
36 tick = s->tick[n]; in gptm_reload()
39 if (s->config == 0) { in gptm_reload()
40 /* 32-bit CountDown. */ in gptm_reload()
42 count = s->load[0] | (s->load[1] << 16); in gptm_reload()
43 tick += clock_ticks_to_ns(s->clk, count); in gptm_reload()
[all …]
/openbmc/u-boot/arch/m68k/include/asm/coldfire/
H A Dpwm.h1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
12 /* Pulse Width Modulation (PWM) */
28 u8 en; /* 0x00 PWM Enable */
30 u8 clk; /* 0x02 Clock Select */
34 u16 res1; /* 0x06 - 0x07 */
37 u16 res2; /* 0x0A - 0x0B */
40 u16 res3; /* 0x10 - 0x11 */
42 u16 res4; /* 0x16 - 0x17 */
[all …]

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