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/openbmc/linux/drivers/clk/bcm/
H A Dclk-iproc-asiu.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
13 #include "clk-iproc.h"
22 struct iproc_asiu_div div; member
38 struct iproc_asiu_clk *clk = to_asiu_clk(hw); in iproc_asiu_clk_enable() local
39 struct iproc_asiu *asiu = clk->asiu; in iproc_asiu_clk_enable()
43 if (clk->gate.offset == IPROC_CLK_INVALID_OFFSET) in iproc_asiu_clk_enable()
46 val = readl(asiu->gate_base + clk->gate.offset); in iproc_asiu_clk_enable()
47 val |= (1 << clk->gate.en_shift); in iproc_asiu_clk_enable()
48 writel(val, asiu->gate_base + clk->gate.offset); in iproc_asiu_clk_enable()
[all …]
/openbmc/linux/drivers/clk/meson/
H A Dclk-regmap.c1 // SPDX-License-Identifier: GPL-2.0
8 #include "clk-regmap.h"
12 struct clk_regmap *clk = to_clk_regmap(hw); in clk_regmap_gate_endisable() local
13 struct clk_regmap_gate_data *gate = clk_get_regmap_gate_data(clk); in clk_regmap_gate_endisable()
14 int set = gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0; in clk_regmap_gate_endisable()
18 return regmap_update_bits(clk->map, gate->offset, BIT(gate->bit_idx), in clk_regmap_gate_endisable()
19 set ? BIT(gate->bit_idx) : 0); in clk_regmap_gate_endisable()
34 struct clk_regmap *clk = to_clk_regmap(hw); in clk_regmap_gate_is_enabled() local
35 struct clk_regmap_gate_data *gate = clk_get_regmap_gate_data(clk); in clk_regmap_gate_is_enabled()
38 regmap_read(clk->map, gate->offset, &val); in clk_regmap_gate_is_enabled()
[all …]
H A Dclk-cpu-dyndiv.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <linux/clk-provider.h>
10 #include "clk-regmap.h"
11 #include "clk-cpu-dyndiv.h"
14 meson_clk_cpu_dyndiv_data(struct clk_regmap *clk) in meson_clk_cpu_dyndiv_data() argument
16 return (struct meson_clk_cpu_dyndiv_data *)clk->data; in meson_clk_cpu_dyndiv_data()
22 struct clk_regmap *clk = to_clk_regmap(hw); in meson_clk_cpu_dyndiv_recalc_rate() local
23 struct meson_clk_cpu_dyndiv_data *data = meson_clk_cpu_dyndiv_data(clk); in meson_clk_cpu_dyndiv_recalc_rate()
26 meson_parm_read(clk->map, &data->div), in meson_clk_cpu_dyndiv_recalc_rate()
27 NULL, 0, data->div.width); in meson_clk_cpu_dyndiv_recalc_rate()
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H A Dsclk-div.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
15 * hi = [0 - val]
19 #include <linux/clk-provider.h>
22 #include "clk-regmap.h"
23 #include "sclk-div.h"
26 meson_sclk_div_data(struct clk_regmap *clk) in meson_sclk_div_data() argument
28 return (struct meson_sclk_div_data *)clk->data; in meson_sclk_div_data()
33 return (1 << sclk->div.width) - 1; in sclk_div_maxval()
44 int div = DIV_ROUND_CLOSEST_ULL((u64)prate, rate); in sclk_div_getdiv() local
46 return clamp(div, 2, maxdiv); in sclk_div_getdiv()
[all …]
/openbmc/linux/drivers/clk/spear/
H A Dspear1340_clock.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/mach-spear13xx/spear1340_clock.c
12 #include <linux/clk/spear.h>
16 #include "clk.h"
175 /* vco-pll4 rate configuration table, in ascending order of rates */
188 {.div = 0x073A8}, /* for vco1div2 = 600 MHz */
189 {.div = 0x06062}, /* for vco1div2 = 500 MHz */
190 {.div = 0x04D1B}, /* for vco1div2 = 400 MHz */
191 {.div = 0x04000}, /* for vco1div2 = 332 MHz */
192 {.div = 0x03031}, /* for vco1div2 = 250 MHz */
[all …]
/openbmc/linux/drivers/clk/mxs/
H A Dclk-div.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <linux/clk-provider.h>
9 #include "clk.h"
12 * struct clk_div - mxs integer divider clock
38 struct clk_div *div = to_clk_div(hw); in clk_div_recalc_rate() local
40 return div->ops->recalc_rate(&div->divider.hw, parent_rate); in clk_div_recalc_rate()
46 struct clk_div *div = to_clk_div(hw); in clk_div_round_rate() local
48 return div->ops->round_rate(&div->divider.hw, rate, prate); in clk_div_round_rate()
54 struct clk_div *div = to_clk_div(hw); in clk_div_set_rate() local
57 ret = div->ops->set_rate(&div->divider.hw, rate, parent_rate); in clk_div_set_rate()
[all …]
/openbmc/linux/drivers/clk/sunxi/
H A Dclk-sunxi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
14 #include <linux/reset-controller.h>
19 #include "clk-factors.h"
27 * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
35 u8 div; in sun4i_get_pll1_factors() local
38 div = req->rate / 6000000; in sun4i_get_pll1_factors()
39 req->rate = 6000000 * div; in sun4i_get_pll1_factors()
42 req->m = 0; in sun4i_get_pll1_factors()
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H A Dclk-sun9i-cpus.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2015 Chen-Yu Tsai
5 * Chen-Yu Tsai <wens@csie.org>
11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
22 * sun9i_a80_cpus_clk_setup() - Setup function for a80 cpus composite clk
36 #define SUN9I_CPUS_DIV_SET(reg, div) ((reg & ~SUN9I_CPUS_DIV_MASK) | \ argument
37 (div << SUN9I_CPUS_DIV_SHIFT))
42 #define SUN9I_CPUS_PLL4_DIV_SET(reg, div) ((reg & ~SUN9I_CPUS_PLL4_DIV_MASK) | \ argument
43 (div << SUN9I_CPUS_PLL4_DIV_SHIFT))
[all …]
H A Dclk-sun8i-mbus.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2014 Chen-Yu Tsai
5 * Chen-Yu Tsai <wens@csie.org>
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
28 const char *clk_name = node->name; in sun8i_a23_mbus_setup()
30 struct clk_divider *div; in sun8i_a23_mbus_setup() local
33 struct clk *clk; in sun8i_a23_mbus_setup() local
43 pr_err("Could not get registers for sun8i-mbus-clk\n"); in sun8i_a23_mbus_setup()
47 div = kzalloc(sizeof(*div), GFP_KERNEL); in sun8i_a23_mbus_setup()
[all …]
/openbmc/u-boot/drivers/clk/renesas/
H A Dclk-rcar-gen2.c1 // SPDX-License-Identifier: GPL-2.0+
14 #include <clk-uclass.h>
19 #include <dt-bindings/clock/renesas-cpg-mssr.h>
21 #include "renesas-cpg-mssr.h"
22 #include "rcar-gen2-cpg.h"
31 u8 div; member
50 if (!(*table).div) in gen2_clk_get_sdh_div()
54 return (*table).div; in gen2_clk_get_sdh_div()
60 static int gen2_clk_enable(struct clk *clk) in gen2_clk_enable() argument
62 struct gen2_clk_priv *priv = dev_get_priv(clk->dev); in gen2_clk_enable()
[all …]
H A Dclk-rcar-gen3.c1 // SPDX-License-Identifier: GPL-2.0+
14 #include <clk-uclass.h>
20 #include <dt-bindings/clock/renesas-cpg-mssr.h>
22 #include "renesas-cpg-mssr.h"
23 #include "rcar-gen3-cpg.h"
51 .div = (sd_div), \
56 unsigned int div; member
60 * sd_srcfc sd_fc div
61 * stp_hck stp_ck (div) (div) = sd_srcfc x sd_fc
62 *-------------------------------------------------------------------
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/openbmc/linux/drivers/mmc/host/
H A Dmeson-mx-sdhc-clkc.c1 // SPDX-License-Identifier: GPL-2.0+
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
13 #include "meson-mx-sdhc.h"
17 struct clk_divider div; member
32 { .div = 6, .val = 5, },
33 { .div = 8, .val = 7, },
34 { .div = 9, .val = 8, },
35 { .div = 10, .val = 9, },
36 { .div = 12, .val = 11, },
[all …]
/openbmc/u-boot/arch/arm/mach-s5pc1xx/
H A Dclock.c1 // SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/clk.h>
27 struct s5pc100_clock *clk = in s5pc100_get_pll_clk() local
34 r = readl(&clk->apll_con); in s5pc100_get_pll_clk()
37 r = readl(&clk->mpll_con); in s5pc100_get_pll_clk()
40 r = readl(&clk->epll_con); in s5pc100_get_pll_clk()
43 r = readl(&clk->hpll_con); in s5pc100_get_pll_clk()
78 struct s5pc110_clock *clk = in s5pc110_get_pll_clk() local
85 r = readl(&clk->apll_con); in s5pc110_get_pll_clk()
88 r = readl(&clk->mpll_con); in s5pc110_get_pll_clk()
[all …]
/openbmc/u-boot/drivers/clk/rockchip/
H A Dclk_rk3368.c1 // SPDX-License-Identifier: GPL-2.0
4 * Author: Andy Yan <andy.yan@rock-chips.com>
9 #include <clk-uclass.h>
11 #include <dt-structs.h>
21 #include <dt-bindings/clock/rk3368-cru.h>
41 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
58 static ulong rk3368_clk_get_rate(struct clk *clk);
66 struct rk3368_pll *pll = &cru->pll[pll_id]; in rkclk_pll_get_rate()
68 con = readl(&pll->con3); in rkclk_pll_get_rate()
74 con = readl(&pll->con0); in rkclk_pll_get_rate()
[all …]
H A Dclk_rk3328.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <clk-uclass.h>
18 #include <dt-bindings/clock/rk3328-cru.h>
29 ((input_rate) / (output_rate) - 1);
30 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
185 * the div restructions of pll in integer mode, these are defined in
198 * FOUTVCO = Fractional PLL non-divided output frequency
207 const struct pll_div *div) in rkclk_set_pll() argument
216 pll_con = cru->apll_con; in rkclk_set_pll()
220 pll_con = cru->dpll_con; in rkclk_set_pll()
[all …]
/openbmc/linux/drivers/clk/rockchip/
H A Dclk.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Author: Xing Zheng <zhengxing@rock-chips.com>
11 * samsung/clk.c
18 #include <linux/clk.h>
19 #include <linux/clk-provider.h>
25 #include "../clk-fractional-divider.h"
26 #include "clk.h"
32 * src1 --|--\
33 * |M |--[GATE]-[DIV]-
34 * src2 --|--/
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/openbmc/linux/drivers/clk/tegra/
H A Dclk-divider.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk-provider.h>
12 #include "clk.h"
14 #define pll_out_override(p) (BIT((p->shift - 6)))
15 #define div_mask(d) ((1 << (d->width)) - 1)
16 #define get_mul(d) (1 << d->frac_width)
24 int div; in get_div() local
26 div = div_frac_get(rate, parent_rate, divider->width, in get_div()
27 divider->frac_width, divider->flags); in get_div()
29 if (div < 0) in get_div()
[all …]
H A Dclk-tegra20-emc.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Based on drivers/clk/tegra/clk-emc.c
7 * Copyright (C) 2019 GRATE-DRIVER project
10 #define pr_fmt(fmt) "tegra-emc-clk: " fmt
13 #include <linux/clk-provider.h>
14 #include <linux/clk/tegra.h>
21 #include "clk.h"
58 u32 val, div; in emc_recalc_rate() local
60 val = readl_relaxed(emc->reg); in emc_recalc_rate()
61 div = val & CLK_SOURCE_EMC_2X_CLK_DIVISOR_MASK; in emc_recalc_rate()
[all …]
/openbmc/linux/drivers/clk/
H A Dclk-fixed-factor.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
16 * prepare - clk_prepare only ensures that parents are prepared
17 * enable - clk_enable only ensures that parents are enabled
18 * rate - rate is fixed. clk->rate = parent->rate / div * mult
19 * parent - fixed parent. No clk_set_parent support
28 rate = (unsigned long long int)parent_rate * fix->mult; in clk_factor_recalc_rate()
29 do_div(rate, fix->div); in clk_factor_recalc_rate()
41 best_parent = (rate / fix->mult) * fix->div; in clk_factor_round_rate()
45 return (*prate / fix->div) * fix->mult; in clk_factor_round_rate()
[all …]
H A Dclk-qoriq.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <linux/clk.h>
13 #include <linux/clk-provider.h>
33 #define CGA_PLL4 4 /* only on clockgen-1.0, which lacks CGB */
39 struct clk *clk; member
44 struct clockgen_pll_div div[MAX_PLL_DIV]; member
53 int div; /* PLL_DIVn */ member
82 int cmux_to_group[NUM_CMUX + 1]; /* array should be -1 terminated */
91 struct clk *sysclk, *coreclk;
[all …]
/openbmc/u-boot/arch/arm/mach-exynos/
H A Dclock.c1 // SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/clk.h>
17 * This structure is to store the src bit, div bit and prediv bit
18 * positions of the peripheral clocks of the src and div registers
32 {PERIPH_ID_UART0, 0xf, 0xf, -1, 0, 0, -1},
33 {PERIPH_ID_UART1, 0xf, 0xf, -1, 4, 4, -1},
34 {PERIPH_ID_UART2, 0xf, 0xf, -1, 8, 8, -1},
35 {PERIPH_ID_UART3, 0xf, 0xf, -1, 12, 12, -1},
36 {PERIPH_ID_I2C0, -1, 0x7, 0x7, -1, 24, 0},
37 {PERIPH_ID_I2C1, -1, 0x7, 0x7, -1, 24, 0},
[all …]
/openbmc/u-boot/arch/arm/cpu/armv7/bcm235xx/
H A Dclk-core.c1 // SPDX-License-Identifier: GPL-2.0+
17 #include <asm/kona-common/clk.h>
18 #include "clk-core.h"
29 struct clk *c; in clk_get_and_enable()
40 return -EINVAL; in clk_get_and_enable()
73 return -ETIMEDOUT; in wait_bit()
77 static int peri_clk_enable(struct clk *c, int enable) in peri_clk_enable()
82 struct peri_clk_data *cd = peri_clk->data; in peri_clk_enable()
83 struct bcm_clk_gate *gate = &cd->gate; in peri_clk_enable()
84 void *base = (void *)c->ccu_clk_mgr_base; in peri_clk_enable()
[all …]
/openbmc/u-boot/arch/arm/cpu/armv7/bcm281xx/
H A Dclk-core.c1 // SPDX-License-Identifier: GPL-2.0+
17 #include <asm/kona-common/clk.h>
18 #include "clk-core.h"
29 struct clk *c; in clk_get_and_enable()
40 return -EINVAL; in clk_get_and_enable()
73 return -ETIMEDOUT; in wait_bit()
77 static int peri_clk_enable(struct clk *c, int enable) in peri_clk_enable()
82 struct peri_clk_data *cd = peri_clk->data; in peri_clk_enable()
83 struct bcm_clk_gate *gate = &cd->gate; in peri_clk_enable()
84 void *base = (void *)c->ccu_clk_mgr_base; in peri_clk_enable()
[all …]
/openbmc/linux/drivers/clk/starfive/
H A Dclk-starfive-jh71x0.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2021-2022 Emil Renner Berthing <kernel@esmil.dk>
8 #include <linux/clk-provider.h>
13 #include "clk-starfive-jh71x0.h"
20 static struct jh71x0_clk_priv *jh71x0_priv_from(struct jh71x0_clk *clk) in jh71x0_priv_from() argument
22 return container_of(clk, struct jh71x0_clk_priv, reg[clk->idx]); in jh71x0_priv_from()
25 static u32 jh71x0_clk_reg_get(struct jh71x0_clk *clk) in jh71x0_clk_reg_get() argument
27 struct jh71x0_clk_priv *priv = jh71x0_priv_from(clk); in jh71x0_clk_reg_get()
28 void __iomem *reg = priv->base + 4 * clk->idx; in jh71x0_clk_reg_get()
33 static void jh71x0_clk_reg_rmw(struct jh71x0_clk *clk, u32 mask, u32 value) in jh71x0_clk_reg_rmw() argument
[all …]
/openbmc/linux/drivers/clk/renesas/
H A Drcar-gen2-cpg.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Gen2 Clock Pulse Generator
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
18 #include "renesas-cpg-mssr.h"
19 #include "rcar-gen2-cpg.h"
39 * prepare - clk_prepare only ensures that parents are prepared
40 * enable - clk_enable only ensures that parents are enabled
41 * rate - rate is adjustable. clk->rate = parent->rate * mult / 32
42 * parent - fixed parent. No clk_set_parent support
[all …]

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