| /openbmc/linux/drivers/hwmon/ |
| H A D | npcm750-pwm-fan.c | 1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2014-2018 Nuvoton Technology corporation.
7 #include <linux/hwmon-sysfs.h>
8 #include <linux/interrupt.h>
19 #define NPCM7XX_PWM_REG_BASE(base, n) ((base) + ((n) * 0x1000L)) argument
21 #define NPCM7XX_PWM_REG_PR(base, n) (NPCM7XX_PWM_REG_BASE(base, n) + 0x00) argument
22 #define NPCM7XX_PWM_REG_CSR(base, n) (NPCM7XX_PWM_REG_BASE(base, n) + 0x04) argument
23 #define NPCM7XX_PWM_REG_CR(base, n) (NPCM7XX_PWM_REG_BASE(base, n) + 0x08) argument
24 #define NPCM7XX_PWM_REG_CNRx(base, n, ch) \ argument
25 (NPCM7XX_PWM_REG_BASE(base, n) + 0x0C + (12 * (ch)))
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| /openbmc/linux/drivers/irqchip/ |
| H A D | irq-mbigen.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/interrupt.h>
19 /* Interrupt numbers per mbigen node supported */
22 /* 64 irqs (Pin0-pin63) are reserved for each mbigen chip */
45 * of interrupt
50 * offset of interrupt type register
51 * This register is used to configure interrupt
57 * struct mbigen_device - holds the information of mbigen device.
60 * @base: mapped address of this mbigen chip.
64 void __iomem *base; member
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| H A D | irq-gic-v2m.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * ARM GIC v2m MSI(-X) support
5 * implement ARM Generic Interrupt Controller: GICv2m.
26 #include <linux/irqchip/arm-gic.h>
27 #include <linux/irqchip/arm-gic-common.h>
50 /* APM X-Gene with GICv2m MSI_IIDR register value */
67 void __iomem *base; /* GICv2m virt address */ member
102 if (v2m->flags & GICV2M_GRAVITON_ADDRESS_ONLY) in gicv2m_get_msi_addr()
103 return v2m->res.start | ((hwirq - 32) << 3); in gicv2m_get_msi_addr()
105 return v2m->res.start + V2M_MSI_SETSPI_NS; in gicv2m_get_msi_addr()
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| /openbmc/linux/Documentation/devicetree/bindings/display/ |
| H A D | st,stih4xx.txt | 3 - sti-vtg: video timing generator
5 - compatible: "st,vtg"
6 - reg: Physical base address of the IP registers and length of memory mapped region.
8 - interrupts : VTG interrupt number to the CPU.
9 - st,slave: phandle on a slave vtg
11 - sti-vtac: video timing advanced inter dye communication Rx and TX
13 - compatible: "st,vtac-main" or "st,vtac-aux"
14 - reg: Physical base address of the IP registers and length of memory mapped region.
15 - clocks: from common clock binding: handle hardware IP needed clocks, the
17 See ../clocks/clock-bindings.txt for details.
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| /openbmc/linux/arch/mips/pci/ |
| H A D | pci-rt3883.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
15 #include <linux/interrupt.h>
22 #include <asm/mach-ralink/rt3883.h>
23 #include <asm/mach-ralink/ralink_regs.h>
60 void __iomem *base; member
77 hose = (struct pci_controller *) bus->sysdata; in pci_bus_to_rt3883_controller()
84 return ioread32(rpc->base + reg); in rt3883_pci_r32()
90 iowrite32(val, rpc->base + reg); in rt3883_pci_w32()
143 generic_handle_domain_irq(rpc->irq_domain, bit); in rt3883_pci_irq_handler()
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| /openbmc/linux/drivers/pinctrl/starfive/ |
| H A D | pinctrl-starfive-jh7100.c | 1 // SPDX-License-Identifier: GPL-2.0
26 #include <dt-bindings/pinctrl/pinctrl-starfive-jh7100.h>
29 #include "../pinctrl-utils.h"
33 #define DRIVER_NAME "pinctrl-starfive"
37 * https://github.com/starfive-tech/JH7100_Docs
48 * The following 32-bit registers come in pairs, but only the offset of the
49 * first register is defined. The first controls (interrupts for) GPIO 0-31 and
50 * the second GPIO 32-63.
54 * Interrupt Type. If set to 1 the interrupt is edge-triggered. If set to 0 the
55 * interrupt is level-triggered.
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| /openbmc/linux/Documentation/devicetree/bindings/soc/dove/ |
| H A D | pmu.txt | 4 - compatible: value should be "marvell,dove-pmu".
5 May also include "simple-bus" if there are child devices, in which
7 - reg: two base addresses and sizes of the PM controller and PMU.
8 - interrupts: single interrupt number for the PMU interrupt
9 - interrupt-controller: must be specified as the PMU itself is an
10 interrupt controller.
11 - #interrupt-cells: must be 1.
12 - #reset-cells: must be 1.
13 - domains: sub-node containing domain descriptions
16 - ranges: defines the address mapping for child devices, as per the
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| /openbmc/linux/drivers/pci/controller/ |
| H A D | pci-mvebu.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Author: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
27 #include "../pci-bridge-emul.h"
40 #define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4))
94 phys_addr_t base; member
102 void __iomem *base; member
130 writel(val, port->base + reg); in mvebu_writel()
135 return readl(port->base + reg); in mvebu_readl()
140 return port->io_target != -1 && port->io_attr != -1; in mvebu_has_ioport()
199 * BAR[0] -> internal registers (needed for MSI)
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| H A D | vmd.c | 1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/interrupt.h>
14 #include <linux/pci-acpi.h>
15 #include <linux/pci-ecam.h>
53 * vendor-specific capability space
58 * Device may use MSI-X vector 0 for software triggering and will not
64 * Device can bypass remapping MSI-X transactions into its MSI-X table,
65 * avoiding the requirement of a VMD MSI domain for child device
66 * interrupt handling.
94 * struct vmd_irq - private data to map driver IRQ to the VMD shared vector
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| /openbmc/linux/include/linux/gpio/ |
| H A D | driver.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
10 #include <linux/pinctrl/pinconf-generic.h>
46 * struct gpio_irq_chip - GPIO interrupt controller
59 * Interrupt translation domain; responsible for mapping between GPIO
76 * If non-NULL, will be set as the parent of this GPIO interrupt
77 * controller's IRQ domain to establish a hierarchical interrupt
79 * interrupt support.
86 * This callback translates a child hardware IRQ offset to a parent
87 * hardware IRQ offset on a hierarchical interrupt chip. The child
88 * hardware IRQs correspond to the GPIO index 0..ngpio-1 (see the
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| /openbmc/linux/Documentation/devicetree/bindings/soc/ti/ |
| H A D | keystone-navigator-qmss.txt | 5 multi-core Navigator. QMSS consist of queue managers, packed-data structure
9 management of the packet queues. Packets are queued/de-queued by writing or
20 - compatible : Must be "ti,keystone-navigator-qmss".
21 : Must be "ti,66ak2g-navss-qm" for QMSS on K2G SoC.
22 - clocks : phandle to the reference clock for this device.
23 - queue-range : <start number> total range of queue numbers for the device.
24 - linkram0 : <address size> for internal link ram, where size is the total
26 - linkram1 : <address size> for external link ram, where size is the total
29 - qmgrs : child node describing the individual queue managers on the
32 -- managed-queues : the actual queues managed by each queue manager
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| /openbmc/linux/Documentation/devicetree/bindings/usb/ |
| H A D | octeon-usb.txt | 7 - compatible: must be "cavium,octeon-5750-usbn"
9 - reg: specifies the physical base address of the USBN block and
12 - #address-cells: specifies the number of cells needed to encode an
15 - #size-cells: specifies the number of cells used to represent the size
18 - ranges: specifies the translation between child address space and parent
21 - clock-frequency: speed of the USB reference clock. Allowed values are
24 - cavium,refclk-type: type of the USB reference clock. Allowed values are
27 - refclk-frequency: deprecated, use "clock-frequency".
29 - refclk-type: deprecated, use "cavium,refclk-type".
31 2) Child node
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| /openbmc/linux/drivers/iio/adc/ |
| H A D | xilinx-ams.c | 1 // SPDX-License-Identifier: GPL-2.0
15 #include <linux/devm-helpers.h>
16 #include <linux/interrupt.h>
123 #define AMS_ALARM_THR_MAX (BIT(16) - 1)
164 #define AMS_TEMP_OFFSET -((280230LL << 16) / 509314)
263 * struct ams - This structure contains necessary state for xilinx-ams to operate
264 * @base: physical base address of device
265 * @ps_base: physical base address of PS device
266 * @pl_base: physical base address of PL device
270 * @intr_lock: to protect interrupt mask values
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| /openbmc/linux/drivers/pinctrl/ |
| H A D | pinctrl-st.c | 1 // SPDX-License-Identifier: GPL-2.0-only
100 * (direction, retime-type, retime-clk, retime-delay)
102 * +----------------+
103 *[31:28]| reserved-3 |
104 * +----------------+-------------
106 * +----------------+ v
108 * +----------------+ ^
110 * +----------------+-------------
111 *[24] | reserved-2 |
112 * +----------------+-------------
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| /openbmc/linux/drivers/mfd/ |
| H A D | mfd-core.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/mfd/mfd-core.c
46 if (!acpi_match_device_ids(adev, wd->ids)) { in match_device_ids()
47 wd->adev = adev; in match_device_ids()
57 const struct mfd_cell_acpi_match *match = cell->acpi_match; in mfd_acpi_add_device()
61 parent = ACPI_COMPANION(pdev->dev.parent); in mfd_acpi_add_device()
66 * MFD child device gets its ACPI handle either from the ACPI device in mfd_acpi_add_device()
75 if (match->pnpid) { in mfd_acpi_add_device()
82 strscpy(ids[0].id, match->pnpid, sizeof(ids[0].id)); in mfd_acpi_add_device()
86 adev = acpi_find_child_device(parent, match->adr, false); in mfd_acpi_add_device()
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| /openbmc/linux/drivers/usb/cdns3/ |
| H A D | core.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2017-2018 NXP
6 * Copyright (C) 2018-2019 Cadence.
20 * struct cdns_role_driver - host/gadget role driver
51 * struct cdns - Representation of Cadence USB3 DRD controller.
53 * @xhci_regs: pointer to base of xhci registers
55 * @dev_regs: pointer to base of dev registers
57 * @otg_v0_regs: pointer to base of v0 otg registers
58 * @otg_v1_regs: pointer to base of v1 otg registers
59 * @otg_cdnsp_regs: pointer to base of CDNSP otg registers
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| /openbmc/linux/Documentation/devicetree/bindings/pci/ |
| H A D | ralink,rt3883-pci.txt | 7 - compatible: must be "ralink,rt3883-pci"
9 - reg: specifies the physical base address of the controller and
12 - #address-cells: specifies the number of cells needed to encode an
15 - #size-cells: specifies the number of cells used to represent the size
18 - ranges: specifies the translation between child address space and parent
23 - status: indicates the operational status of the device.
26 2) Child nodes
28 The main node must have two child nodes which describes the built-in
29 interrupt controller and the PCI host bridge.
31 a) Interrupt controller:
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| /openbmc/linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | brcm,nsp-gpio.txt | 4 - compatible:
5 Must be "brcm,nsp-gpio-a"
7 - reg:
9 GPIO base, IO control registers
11 - #gpio-cells:
16 - gpio-controller:
19 - ngpios:
23 - interrupts:
24 Interrupt ID
26 - interrupt-controller:
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| H A D | brcm,iproc-gpio.txt | 5 - compatible:
6 "brcm,iproc-gpio" for the generic iProc based GPIO controller IP that
7 supports full-featured pinctrl and GPIO functions used in various iProc
10 May contain an SoC-specific compatibility string to accommodate any
11 SoC-specific features
13 "brcm,cygnus-ccm-gpio", "brcm,cygnus-asiu-gpio", or
14 "brcm,cygnus-crmu-gpio" for Cygnus SoCs
16 "brcm,iproc-nsp-gpio" for the iProc NSP SoC that has drive strength support
19 "brcm,iproc-stingray-gpio" for the iProc Stingray SoC that has the general
23 - reg:
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| /openbmc/linux/drivers/gpio/ |
| H A D | gpio-ixp4xx.c | 1 // SPDX-License-Identifier: GPL-2.0
6 // based on previous work and know-how from:
28 * The hardware uses 3 bits to indicate interrupt "style".
42 * struct ixp4xx_gpio - IXP4 GPIO state container
46 * @base: remapped I/O-memory base
47 * @irq_edge: Each bit represents an IRQ: 1: edge-triggered,
54 void __iomem *base; member
63 __raw_writel(BIT(d->hwirq), g->base + IXP4XX_REG_GPIS); in ixp4xx_gpio_irq_ack()
71 gpiochip_disable_irq(gc, d->hwirq); in ixp4xx_gpio_mask_irq()
79 /* ACK when unmasking if not edge-triggered */ in ixp4xx_gpio_irq_unmask()
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| H A D | gpio-visconti.c | 1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/interrupt.h>
32 void __iomem *base; member
49 spin_lock_irqsave(&priv->lock, flags); in visconti_gpio_irq_set_type()
51 odata = readl(priv->base + GPIO_ODATA); in visconti_gpio_irq_set_type()
52 intmode = readl(priv->base + GPIO_INTMODE); in visconti_gpio_irq_set_type()
77 ret = -EINVAL; in visconti_gpio_irq_set_type()
81 writel(odata, priv->base + GPIO_ODATA); in visconti_gpio_irq_set_type()
82 writel(intmode, priv->base + GPIO_INTMODE); in visconti_gpio_irq_set_type()
87 spin_unlock_irqrestore(&priv->lock, flags); in visconti_gpio_irq_set_type()
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| /openbmc/linux/Documentation/devicetree/bindings/mmc/ |
| H A D | amlogic,meson-mx-sdio.txt | 13 - compatible : must be one of
14 - "amlogic,meson8-sdio"
15 - "amlogic,meson8b-sdio"
16 along with the generic "amlogic,meson-mx-sdio"
17 - reg : mmc controller base registers
18 - interrupts : mmc controller interrupt
19 - #address-cells : must be 1
20 - size-cells : must be 0
21 - clocks : phandle to clock providers
22 - clock-names : must contain "core" and "clkin"
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| /openbmc/qemu/hw/i386/ |
| H A D | microvm-dt.c | 19 * ----------------------------------------------------------------------
37 #include "hw/char/serial-isa.h"
41 #include "hw/virtio/virtio-mmio.h"
44 #include "microvm-dt.h"
54 irq -= IO_APIC_SECONDARY_IRQBASE; in dt_add_microvm_irq()
58 qemu_fdt_setprop_cell(mms->fdt, nodename, "interrupt-parent", in dt_add_microvm_irq()
59 mms->ioapic_phandle[index]); in dt_add_microvm_irq()
60 qemu_fdt_setprop_cells(mms->fdt, nodename, "interrupts", irq, 0); in dt_add_microvm_irq()
66 VirtioBusState *mmio_virtio_bus = &mmio->bus; in dt_add_virtio()
67 BusState *mmio_bus = &mmio_virtio_bus->parent_obj; in dt_add_virtio()
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| /openbmc/linux/Documentation/devicetree/bindings/net/dsa/ |
| H A D | marvell.txt | 2 ---------------------------------------
11 placed as a child node of an mdio device.
17 which is at a different MDIO base address in different switch families.
18 - "marvell,mv88e6085" : Switch has base address 0x10. Use with models:
22 - "marvell,mv88e6190" : Switch has base address 0x00. Use with models:
24 - "marvell,mv88e6250" : Switch has base address 0x08 or 0x18. Use with model:
28 - compatible : Should be one of "marvell,mv88e6085",
31 - reg : Address on the MII bus for the switch.
35 - reset-gpios : Should be a gpio specifier for a reset line
36 - interrupts : Interrupt from the switch
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| /openbmc/linux/Documentation/devicetree/bindings/crypto/ |
| H A D | fsl-sec6.txt | 4 -SEC 6 Node
5 -Job Ring Node
6 -Full Example
13 Node defines the base address of the SEC 6 block.
20 - compatible
23 Definition: Must include "fsl,sec-v6.0".
25 - fsl,sec-era
31 - #address-cells
35 for representing physical addresses in child nodes.
37 - #size-cells
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