1caab277bSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
2717c3dbcSMa Jun /*
364ec2ad3SHao Fang * Copyright (C) 2015 HiSilicon Limited, All Rights Reserved.
4717c3dbcSMa Jun * Author: Jun Ma <majun258@huawei.com>
5717c3dbcSMa Jun * Author: Yun Wu <wuyun.wu@huawei.com>
6717c3dbcSMa Jun */
7717c3dbcSMa Jun
8f907c515SHanjun Guo #include <linux/acpi.h>
99650c60eSMa Jun #include <linux/interrupt.h>
109650c60eSMa Jun #include <linux/irqchip.h>
11717c3dbcSMa Jun #include <linux/module.h>
129650c60eSMa Jun #include <linux/msi.h>
13717c3dbcSMa Jun #include <linux/of_address.h>
14717c3dbcSMa Jun #include <linux/of_irq.h>
15717c3dbcSMa Jun #include <linux/of_platform.h>
16717c3dbcSMa Jun #include <linux/platform_device.h>
17717c3dbcSMa Jun #include <linux/slab.h>
18717c3dbcSMa Jun
199650c60eSMa Jun /* Interrupt numbers per mbigen node supported */
209650c60eSMa Jun #define IRQS_PER_MBIGEN_NODE 128
219650c60eSMa Jun
229650c60eSMa Jun /* 64 irqs (Pin0-pin63) are reserved for each mbigen chip */
239650c60eSMa Jun #define RESERVED_IRQ_PER_MBIGEN_CHIP 64
249650c60eSMa Jun
259650c60eSMa Jun /* The maximum IRQ pin number of mbigen chip(start from 0) */
269650c60eSMa Jun #define MAXIMUM_IRQ_PIN_NUM 1407
279650c60eSMa Jun
28b9994883SRandy Dunlap /*
299650c60eSMa Jun * In mbigen vector register
309650c60eSMa Jun * bit[21:12]: event id value
319650c60eSMa Jun * bit[11:0]: device id
329650c60eSMa Jun */
339650c60eSMa Jun #define IRQ_EVENT_ID_SHIFT 12
349650c60eSMa Jun #define IRQ_EVENT_ID_MASK 0x3ff
359650c60eSMa Jun
369650c60eSMa Jun /* register range of each mbigen node */
379650c60eSMa Jun #define MBIGEN_NODE_OFFSET 0x1000
389650c60eSMa Jun
399650c60eSMa Jun /* offset of vector register in mbigen node */
409650c60eSMa Jun #define REG_MBIGEN_VEC_OFFSET 0x200
419650c60eSMa Jun
42b9994883SRandy Dunlap /*
43a6c2f87bSMa Jun * offset of clear register in mbigen node
44a6c2f87bSMa Jun * This register is used to clear the status
45a6c2f87bSMa Jun * of interrupt
46a6c2f87bSMa Jun */
47a6c2f87bSMa Jun #define REG_MBIGEN_CLEAR_OFFSET 0xa000
48a6c2f87bSMa Jun
49b9994883SRandy Dunlap /*
50a6c2f87bSMa Jun * offset of interrupt type register
51a6c2f87bSMa Jun * This register is used to configure interrupt
52a6c2f87bSMa Jun * trigger type
53a6c2f87bSMa Jun */
54a6c2f87bSMa Jun #define REG_MBIGEN_TYPE_OFFSET 0x0
55a6c2f87bSMa Jun
56a6c2f87bSMa Jun /**
57717c3dbcSMa Jun * struct mbigen_device - holds the information of mbigen device.
58717c3dbcSMa Jun *
59717c3dbcSMa Jun * @pdev: pointer to the platform device structure of mbigen chip.
60717c3dbcSMa Jun * @base: mapped address of this mbigen chip.
61717c3dbcSMa Jun */
62717c3dbcSMa Jun struct mbigen_device {
63717c3dbcSMa Jun struct platform_device *pdev;
64717c3dbcSMa Jun void __iomem *base;
65717c3dbcSMa Jun };
66717c3dbcSMa Jun
get_mbigen_vec_reg(irq_hw_number_t hwirq)679650c60eSMa Jun static inline unsigned int get_mbigen_vec_reg(irq_hw_number_t hwirq)
689650c60eSMa Jun {
699650c60eSMa Jun unsigned int nid, pin;
709650c60eSMa Jun
719650c60eSMa Jun hwirq -= RESERVED_IRQ_PER_MBIGEN_CHIP;
729650c60eSMa Jun nid = hwirq / IRQS_PER_MBIGEN_NODE + 1;
739650c60eSMa Jun pin = hwirq % IRQS_PER_MBIGEN_NODE;
749650c60eSMa Jun
759650c60eSMa Jun return pin * 4 + nid * MBIGEN_NODE_OFFSET
769650c60eSMa Jun + REG_MBIGEN_VEC_OFFSET;
779650c60eSMa Jun }
789650c60eSMa Jun
get_mbigen_type_reg(irq_hw_number_t hwirq,u32 * mask,u32 * addr)79a6c2f87bSMa Jun static inline void get_mbigen_type_reg(irq_hw_number_t hwirq,
80a6c2f87bSMa Jun u32 *mask, u32 *addr)
81a6c2f87bSMa Jun {
82a6c2f87bSMa Jun unsigned int nid, irq_ofst, ofst;
83a6c2f87bSMa Jun
84a6c2f87bSMa Jun hwirq -= RESERVED_IRQ_PER_MBIGEN_CHIP;
85a6c2f87bSMa Jun nid = hwirq / IRQS_PER_MBIGEN_NODE + 1;
86a6c2f87bSMa Jun irq_ofst = hwirq % IRQS_PER_MBIGEN_NODE;
87a6c2f87bSMa Jun
88a6c2f87bSMa Jun *mask = 1 << (irq_ofst % 32);
89a6c2f87bSMa Jun ofst = irq_ofst / 32 * 4;
90a6c2f87bSMa Jun
91a6c2f87bSMa Jun *addr = ofst + nid * MBIGEN_NODE_OFFSET
92a6c2f87bSMa Jun + REG_MBIGEN_TYPE_OFFSET;
93a6c2f87bSMa Jun }
94a6c2f87bSMa Jun
get_mbigen_clear_reg(irq_hw_number_t hwirq,u32 * mask,u32 * addr)95a6c2f87bSMa Jun static inline void get_mbigen_clear_reg(irq_hw_number_t hwirq,
96a6c2f87bSMa Jun u32 *mask, u32 *addr)
97a6c2f87bSMa Jun {
989459a04bSMaJun unsigned int ofst = (hwirq / 32) * 4;
99a6c2f87bSMa Jun
100a6c2f87bSMa Jun *mask = 1 << (hwirq % 32);
101a6c2f87bSMa Jun *addr = ofst + REG_MBIGEN_CLEAR_OFFSET;
102a6c2f87bSMa Jun }
103a6c2f87bSMa Jun
mbigen_eoi_irq(struct irq_data * data)104a6c2f87bSMa Jun static void mbigen_eoi_irq(struct irq_data *data)
105a6c2f87bSMa Jun {
106a6c2f87bSMa Jun void __iomem *base = data->chip_data;
107a6c2f87bSMa Jun u32 mask, addr;
108a6c2f87bSMa Jun
109a6c2f87bSMa Jun get_mbigen_clear_reg(data->hwirq, &mask, &addr);
110a6c2f87bSMa Jun
111a6c2f87bSMa Jun writel_relaxed(mask, base + addr);
112a6c2f87bSMa Jun
113a6c2f87bSMa Jun irq_chip_eoi_parent(data);
114a6c2f87bSMa Jun }
115a6c2f87bSMa Jun
mbigen_set_type(struct irq_data * data,unsigned int type)116a6c2f87bSMa Jun static int mbigen_set_type(struct irq_data *data, unsigned int type)
117a6c2f87bSMa Jun {
118a6c2f87bSMa Jun void __iomem *base = data->chip_data;
119a6c2f87bSMa Jun u32 mask, addr, val;
120a6c2f87bSMa Jun
121a6c2f87bSMa Jun if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING)
122a6c2f87bSMa Jun return -EINVAL;
123a6c2f87bSMa Jun
124a6c2f87bSMa Jun get_mbigen_type_reg(data->hwirq, &mask, &addr);
125a6c2f87bSMa Jun
126a6c2f87bSMa Jun val = readl_relaxed(base + addr);
127a6c2f87bSMa Jun
128a6c2f87bSMa Jun if (type == IRQ_TYPE_LEVEL_HIGH)
129a6c2f87bSMa Jun val |= mask;
130a6c2f87bSMa Jun else
131a6c2f87bSMa Jun val &= ~mask;
132a6c2f87bSMa Jun
133a6c2f87bSMa Jun writel_relaxed(val, base + addr);
134a6c2f87bSMa Jun
135a6c2f87bSMa Jun return 0;
136a6c2f87bSMa Jun }
137a6c2f87bSMa Jun
1389650c60eSMa Jun static struct irq_chip mbigen_irq_chip = {
1399650c60eSMa Jun .name = "mbigen-v2",
140a6c2f87bSMa Jun .irq_mask = irq_chip_mask_parent,
141a6c2f87bSMa Jun .irq_unmask = irq_chip_unmask_parent,
142a6c2f87bSMa Jun .irq_eoi = mbigen_eoi_irq,
143a6c2f87bSMa Jun .irq_set_type = mbigen_set_type,
144a6c2f87bSMa Jun .irq_set_affinity = irq_chip_set_affinity_parent,
1459650c60eSMa Jun };
1469650c60eSMa Jun
mbigen_write_msg(struct msi_desc * desc,struct msi_msg * msg)1479650c60eSMa Jun static void mbigen_write_msg(struct msi_desc *desc, struct msi_msg *msg)
1489650c60eSMa Jun {
1499650c60eSMa Jun struct irq_data *d = irq_get_irq_data(desc->irq);
1509650c60eSMa Jun void __iomem *base = d->chip_data;
1519650c60eSMa Jun u32 val;
1529650c60eSMa Jun
153fca269f2SJianguo Chen if (!msg->address_lo && !msg->address_hi)
154fca269f2SJianguo Chen return;
155fca269f2SJianguo Chen
1569650c60eSMa Jun base += get_mbigen_vec_reg(d->hwirq);
1579650c60eSMa Jun val = readl_relaxed(base);
1589650c60eSMa Jun
1599650c60eSMa Jun val &= ~(IRQ_EVENT_ID_MASK << IRQ_EVENT_ID_SHIFT);
1609650c60eSMa Jun val |= (msg->data << IRQ_EVENT_ID_SHIFT);
1619650c60eSMa Jun
1629650c60eSMa Jun /* The address of doorbell is encoded in mbigen register by default
1639650c60eSMa Jun * So,we don't need to program the doorbell address at here
1649650c60eSMa Jun */
1659650c60eSMa Jun writel_relaxed(val, base);
1669650c60eSMa Jun }
1679650c60eSMa Jun
mbigen_domain_translate(struct irq_domain * d,struct irq_fwspec * fwspec,unsigned long * hwirq,unsigned int * type)1689650c60eSMa Jun static int mbigen_domain_translate(struct irq_domain *d,
1699650c60eSMa Jun struct irq_fwspec *fwspec,
1709650c60eSMa Jun unsigned long *hwirq,
1719650c60eSMa Jun unsigned int *type)
1729650c60eSMa Jun {
173f907c515SHanjun Guo if (is_of_node(fwspec->fwnode) || is_acpi_device_node(fwspec->fwnode)) {
1749650c60eSMa Jun if (fwspec->param_count != 2)
1759650c60eSMa Jun return -EINVAL;
1769650c60eSMa Jun
1779650c60eSMa Jun if ((fwspec->param[0] > MAXIMUM_IRQ_PIN_NUM) ||
1789650c60eSMa Jun (fwspec->param[0] < RESERVED_IRQ_PER_MBIGEN_CHIP))
1799650c60eSMa Jun return -EINVAL;
1809650c60eSMa Jun else
1819650c60eSMa Jun *hwirq = fwspec->param[0];
1829650c60eSMa Jun
1839650c60eSMa Jun /* If there is no valid irq type, just use the default type */
1849650c60eSMa Jun if ((fwspec->param[1] == IRQ_TYPE_EDGE_RISING) ||
1859650c60eSMa Jun (fwspec->param[1] == IRQ_TYPE_LEVEL_HIGH))
1869650c60eSMa Jun *type = fwspec->param[1];
1879650c60eSMa Jun else
1889650c60eSMa Jun return -EINVAL;
1899650c60eSMa Jun
1909650c60eSMa Jun return 0;
1919650c60eSMa Jun }
1929650c60eSMa Jun return -EINVAL;
1939650c60eSMa Jun }
1949650c60eSMa Jun
mbigen_irq_domain_alloc(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs,void * args)1959650c60eSMa Jun static int mbigen_irq_domain_alloc(struct irq_domain *domain,
1969650c60eSMa Jun unsigned int virq,
1979650c60eSMa Jun unsigned int nr_irqs,
1989650c60eSMa Jun void *args)
1999650c60eSMa Jun {
2009650c60eSMa Jun struct irq_fwspec *fwspec = args;
2019650c60eSMa Jun irq_hw_number_t hwirq;
2029650c60eSMa Jun unsigned int type;
2039650c60eSMa Jun struct mbigen_device *mgn_chip;
2049650c60eSMa Jun int i, err;
2059650c60eSMa Jun
2069650c60eSMa Jun err = mbigen_domain_translate(domain, fwspec, &hwirq, &type);
2079650c60eSMa Jun if (err)
2089650c60eSMa Jun return err;
2099650c60eSMa Jun
2109835cec6SThomas Gleixner err = platform_msi_device_domain_alloc(domain, virq, nr_irqs);
2119650c60eSMa Jun if (err)
2129650c60eSMa Jun return err;
2139650c60eSMa Jun
2149650c60eSMa Jun mgn_chip = platform_msi_get_host_data(domain);
2159650c60eSMa Jun
2169650c60eSMa Jun for (i = 0; i < nr_irqs; i++)
2179650c60eSMa Jun irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
2189650c60eSMa Jun &mbigen_irq_chip, mgn_chip->base);
2199650c60eSMa Jun
2209650c60eSMa Jun return 0;
2219650c60eSMa Jun }
2229650c60eSMa Jun
mbigen_irq_domain_free(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs)223edfc23f6SZenghui Yu static void mbigen_irq_domain_free(struct irq_domain *domain, unsigned int virq,
224edfc23f6SZenghui Yu unsigned int nr_irqs)
225edfc23f6SZenghui Yu {
2269835cec6SThomas Gleixner platform_msi_device_domain_free(domain, virq, nr_irqs);
227edfc23f6SZenghui Yu }
228edfc23f6SZenghui Yu
229e183c2a3STobias Klauser static const struct irq_domain_ops mbigen_domain_ops = {
2309650c60eSMa Jun .translate = mbigen_domain_translate,
2319650c60eSMa Jun .alloc = mbigen_irq_domain_alloc,
232edfc23f6SZenghui Yu .free = mbigen_irq_domain_free,
2339650c60eSMa Jun };
2349650c60eSMa Jun
mbigen_of_create_domain(struct platform_device * pdev,struct mbigen_device * mgn_chip)23576e1f77fSKefeng Wang static int mbigen_of_create_domain(struct platform_device *pdev,
23676e1f77fSKefeng Wang struct mbigen_device *mgn_chip)
237717c3dbcSMa Jun {
238ed2a1002SMaJun struct platform_device *child;
2399650c60eSMa Jun struct irq_domain *domain;
240ed2a1002SMaJun struct device_node *np;
2419650c60eSMa Jun u32 num_pins;
242cddb536aSKefeng Wang int ret = 0;
243cddb536aSKefeng Wang
244ed2a1002SMaJun for_each_child_of_node(pdev->dev.of_node, np) {
245ed2a1002SMaJun if (!of_property_read_bool(np, "interrupt-controller"))
246ed2a1002SMaJun continue;
247ed2a1002SMaJun
248*a9ab3386SChen Jun child = of_platform_device_create(np, NULL, NULL);
249321275f0SNishka Dasgupta if (!child) {
250cddb536aSKefeng Wang ret = -ENOMEM;
251cddb536aSKefeng Wang break;
252fea087fcSGreg Kroah-Hartman }
253ed2a1002SMaJun
254ed2a1002SMaJun if (of_property_read_u32(child->dev.of_node, "num-pins",
255ed2a1002SMaJun &num_pins) < 0) {
2569650c60eSMa Jun dev_err(&pdev->dev, "No num-pins property\n");
257cddb536aSKefeng Wang ret = -EINVAL;
258cddb536aSKefeng Wang break;
2599650c60eSMa Jun }
2609650c60eSMa Jun
261ed2a1002SMaJun domain = platform_msi_create_device_domain(&child->dev, num_pins,
2629650c60eSMa Jun mbigen_write_msg,
2639650c60eSMa Jun &mbigen_domain_ops,
2649650c60eSMa Jun mgn_chip);
265321275f0SNishka Dasgupta if (!domain) {
266cddb536aSKefeng Wang ret = -ENOMEM;
267cddb536aSKefeng Wang break;
268ed2a1002SMaJun }
269321275f0SNishka Dasgupta }
2709650c60eSMa Jun
271cddb536aSKefeng Wang if (ret)
272cddb536aSKefeng Wang of_node_put(np);
273cddb536aSKefeng Wang
274cddb536aSKefeng Wang return ret;
27576e1f77fSKefeng Wang }
27676e1f77fSKefeng Wang
277f907c515SHanjun Guo #ifdef CONFIG_ACPI
278c96d6abbSYang Yingliang static const struct acpi_device_id mbigen_acpi_match[] = {
279c96d6abbSYang Yingliang { "HISI0152", 0 },
280c96d6abbSYang Yingliang {}
281c96d6abbSYang Yingliang };
282c96d6abbSYang Yingliang MODULE_DEVICE_TABLE(acpi, mbigen_acpi_match);
283c96d6abbSYang Yingliang
mbigen_acpi_create_domain(struct platform_device * pdev,struct mbigen_device * mgn_chip)284f907c515SHanjun Guo static int mbigen_acpi_create_domain(struct platform_device *pdev,
285f907c515SHanjun Guo struct mbigen_device *mgn_chip)
286f907c515SHanjun Guo {
287f907c515SHanjun Guo struct irq_domain *domain;
288f907c515SHanjun Guo u32 num_pins = 0;
289f907c515SHanjun Guo int ret;
290f907c515SHanjun Guo
291f907c515SHanjun Guo /*
292f907c515SHanjun Guo * "num-pins" is the total number of interrupt pins implemented in
293f907c515SHanjun Guo * this mbigen instance, and mbigen is an interrupt controller
294f907c515SHanjun Guo * connected to ITS converting wired interrupts into MSI, so we
295f907c515SHanjun Guo * use "num-pins" to alloc MSI vectors which are needed by client
296f907c515SHanjun Guo * devices connected to it.
297f907c515SHanjun Guo *
298f907c515SHanjun Guo * Here is the DSDT device node used for mbigen in firmware:
299f907c515SHanjun Guo * Device(MBI0) {
300f907c515SHanjun Guo * Name(_HID, "HISI0152")
301f907c515SHanjun Guo * Name(_UID, Zero)
302f907c515SHanjun Guo * Name(_CRS, ResourceTemplate() {
303f907c515SHanjun Guo * Memory32Fixed(ReadWrite, 0xa0080000, 0x10000)
304f907c515SHanjun Guo * })
305f907c515SHanjun Guo *
306f907c515SHanjun Guo * Name(_DSD, Package () {
307f907c515SHanjun Guo * ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
308f907c515SHanjun Guo * Package () {
309f907c515SHanjun Guo * Package () {"num-pins", 378}
310f907c515SHanjun Guo * }
311f907c515SHanjun Guo * })
312f907c515SHanjun Guo * }
313f907c515SHanjun Guo */
314f907c515SHanjun Guo ret = device_property_read_u32(&pdev->dev, "num-pins", &num_pins);
315f907c515SHanjun Guo if (ret || num_pins == 0)
316f907c515SHanjun Guo return -EINVAL;
317f907c515SHanjun Guo
318f907c515SHanjun Guo domain = platform_msi_create_device_domain(&pdev->dev, num_pins,
319f907c515SHanjun Guo mbigen_write_msg,
320f907c515SHanjun Guo &mbigen_domain_ops,
321f907c515SHanjun Guo mgn_chip);
322f907c515SHanjun Guo if (!domain)
323f907c515SHanjun Guo return -ENOMEM;
324f907c515SHanjun Guo
325f907c515SHanjun Guo return 0;
326f907c515SHanjun Guo }
327f907c515SHanjun Guo #else
mbigen_acpi_create_domain(struct platform_device * pdev,struct mbigen_device * mgn_chip)328f907c515SHanjun Guo static inline int mbigen_acpi_create_domain(struct platform_device *pdev,
329f907c515SHanjun Guo struct mbigen_device *mgn_chip)
330f907c515SHanjun Guo {
331f907c515SHanjun Guo return -ENODEV;
332f907c515SHanjun Guo }
333f907c515SHanjun Guo #endif
334f907c515SHanjun Guo
mbigen_device_probe(struct platform_device * pdev)33576e1f77fSKefeng Wang static int mbigen_device_probe(struct platform_device *pdev)
33676e1f77fSKefeng Wang {
33776e1f77fSKefeng Wang struct mbigen_device *mgn_chip;
33876e1f77fSKefeng Wang struct resource *res;
33976e1f77fSKefeng Wang int err;
34076e1f77fSKefeng Wang
34176e1f77fSKefeng Wang mgn_chip = devm_kzalloc(&pdev->dev, sizeof(*mgn_chip), GFP_KERNEL);
34276e1f77fSKefeng Wang if (!mgn_chip)
34376e1f77fSKefeng Wang return -ENOMEM;
34476e1f77fSKefeng Wang
34576e1f77fSKefeng Wang mgn_chip->pdev = pdev;
34676e1f77fSKefeng Wang
34776e1f77fSKefeng Wang res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
348ad7cc3c0SHanjun Guo if (!res)
349ad7cc3c0SHanjun Guo return -EINVAL;
350ad7cc3c0SHanjun Guo
3515ba9b0a1SHanjun Guo mgn_chip->base = devm_ioremap(&pdev->dev, res->start,
3525ba9b0a1SHanjun Guo resource_size(res));
3535ba9b0a1SHanjun Guo if (!mgn_chip->base) {
3545ba9b0a1SHanjun Guo dev_err(&pdev->dev, "failed to ioremap %pR\n", res);
3555ba9b0a1SHanjun Guo return -ENOMEM;
3565ba9b0a1SHanjun Guo }
35776e1f77fSKefeng Wang
358f907c515SHanjun Guo if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node)
35976e1f77fSKefeng Wang err = mbigen_of_create_domain(pdev, mgn_chip);
360f907c515SHanjun Guo else if (ACPI_COMPANION(&pdev->dev))
361f907c515SHanjun Guo err = mbigen_acpi_create_domain(pdev, mgn_chip);
362f907c515SHanjun Guo else
363f907c515SHanjun Guo err = -EINVAL;
364f907c515SHanjun Guo
365f907c515SHanjun Guo if (err) {
3660bdd0047SKefeng Wang dev_err(&pdev->dev, "Failed to create mbi-gen irqdomain\n");
36776e1f77fSKefeng Wang return err;
368f907c515SHanjun Guo }
36976e1f77fSKefeng Wang
370717c3dbcSMa Jun platform_set_drvdata(pdev, mgn_chip);
371717c3dbcSMa Jun return 0;
372717c3dbcSMa Jun }
373717c3dbcSMa Jun
374717c3dbcSMa Jun static const struct of_device_id mbigen_of_match[] = {
375717c3dbcSMa Jun { .compatible = "hisilicon,mbigen-v2" },
376717c3dbcSMa Jun { /* END */ }
377717c3dbcSMa Jun };
378717c3dbcSMa Jun MODULE_DEVICE_TABLE(of, mbigen_of_match);
379717c3dbcSMa Jun
380717c3dbcSMa Jun static struct platform_driver mbigen_platform_driver = {
381717c3dbcSMa Jun .driver = {
382717c3dbcSMa Jun .name = "Hisilicon MBIGEN-V2",
383717c3dbcSMa Jun .of_match_table = mbigen_of_match,
384f907c515SHanjun Guo .acpi_match_table = ACPI_PTR(mbigen_acpi_match),
385d6152e6eSJohn Garry .suppress_bind_attrs = true,
386717c3dbcSMa Jun },
387717c3dbcSMa Jun .probe = mbigen_device_probe,
388717c3dbcSMa Jun };
389717c3dbcSMa Jun
390717c3dbcSMa Jun module_platform_driver(mbigen_platform_driver);
391717c3dbcSMa Jun
392717c3dbcSMa Jun MODULE_AUTHOR("Jun Ma <majun258@huawei.com>");
393717c3dbcSMa Jun MODULE_AUTHOR("Yun Wu <wuyun.wu@huawei.com>");
39464ec2ad3SHao Fang MODULE_DESCRIPTION("HiSilicon MBI Generator driver");
395