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/openbmc/linux/drivers/clk/bcm/
H A Dclk-sr.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
11 #include <dt-bindings/clock/bcm-sr.h>
12 #include "clk-iproc.h"
49 .channel = BCM_SR_GENPLL0_125M_CLK,
52 .mdiv = REG_VAL(0x18, 0, 9),
55 .channel = BCM_SR_GENPLL0_SCR_CLK,
58 .mdiv = REG_VAL(0x18, 10, 9),
61 .channel = BCM_SR_GENPLL0_250M_CLK,
64 .mdiv = REG_VAL(0x18, 20, 9),
[all …]
H A Dclk-cygnus.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/bcm-cygnus.h>
14 #include "clk-iproc.h"
45 CLK_OF_DECLARE(cygnus_armpll, "brcm,cygnus-armpll", cygnus_armpll_init);
63 .channel = BCM_CYGNUS_GENPLL_AXI21_CLK,
69 .channel = BCM_CYGNUS_GENPLL_250MHZ_CLK,
75 .channel = BCM_CYGNUS_GENPLL_IHOST_SYS_CLK,
81 .channel = BCM_CYGNUS_GENPLL_ENET_SW_CLK,
83 .enable = ENABLE_VAL(0x4, 9, 3, 15),
[all …]
/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dnvidia,tegra210-admaif.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra210-admaif.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 ADMAIF is the interface between ADMA and AHUB. Each ADMA channel
12 ADMAIF channel. ADMA channel sending data to AHUB pairs with ADMAIF
13 Tx channel and ADMA channel receiving data from AHUB pairs with
14 ADMAIF Rx channel.
17 - Jon Hunter <jonathanh@nvidia.com>
18 - Sameer Pujar <spujar@nvidia.com>
[all …]
H A Dsnps,designware-i2s.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/snps,designware-i2s.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jose Abreu <joabreu@synopsys.com>
15 - items:
16 - const: canaan,k210-i2s
17 - const: snps,designware-i2s
18 - enum:
19 - snps,designware-i2s
[all …]
/openbmc/bmcweb/redfish-core/schema/dmtf/json-schema/
H A DVCATEntry.v1_0_3.json4 "$schema": "http://redfish.dmtf.org/schemas/v1/redfish-schema-v1.json",
5 …"copyright": "Copyright 2014-2024 DMTF. For the full DMTF copyright policy, see http://www.dmtf.or…
12 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
28 "description": "The available OEM-specific actions for this resource.",
29 …"longDescription": "This property shall contain the available OEM-specific actions for this resour…
36 "description": "The available OEM-specific actions for this resource.",
37 …"longDescription": "This type shall contain the available OEM-specific actions for this resource.",
39 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
57 …: "The `VCATEntry` schema defines an entry in a Virtual Channel Action Table. A Virtual Channel i…
58 …"longDescription": "This resource shall represent an entry of Virtual Channel Action Table in a Re…
[all …]
H A DNetworkDeviceFunctionMetrics.v1_2_0.json4 "$schema": "http://redfish.dmtf.org/schemas/v1/redfish-schema-v1.json",
5 …"copyright": "Copyright 2014-2024 DMTF. For the full DMTF copyright policy, see http://www.dmtf.or…
12 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
31 "description": "The available OEM-specific actions for this resource.",
32 …"longDescription": "This property shall contain the available OEM-specific actions for this resour…
40 … "longDescription": "This type shall describe the Ethernet-related network function metrics.",
42 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
79 "description": "The network function metrics for a Fibre Channel interface.",
80 … "longDescription": "This type shall describe the Fibre Channel-related network function metrics.",
82 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
[all …]
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/ddr/
H A Djedec,lpddr-channel.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr-channel.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR channel with chip/rank topology description
10 An LPDDR channel is a completely independent set of LPDDR pins (DQ, CA, CS,
16 - Julius Werner <jwerner@chromium.org>
21 - jedec,lpddr2-channel
22 - jedec,lpddr3-channel
23 - jedec,lpddr4-channel
[all …]
/openbmc/openbmc/meta-openembedded/meta-multimedia/recipes-multimedia/dvb-apps/files/dvb-scan-table/dvb-s/
H A DGalaxy19_C-97.0W1 # Galaxy 19 @ 97W C-BAND
3 [CHANNEL]
12 [CHANNEL]
21 [CHANNEL]
26 INNER_FEC = 9/10
30 [CHANNEL]
39 [CHANNEL]
48 [CHANNEL]
57 [CHANNEL]
66 [CHANNEL]
[all …]
H A DInsat2E_C-83.0E1 # Insat 2E @ 83.0E C-BAND
5 # MPEG-2 & MPEG-4 QPSK (DVBS/S2)
9 [CHANNEL]
19 [CHANNEL]
28 # TV 9 Telugu
29 [CHANNEL]
38 # S1 Channel
39 [CHANNEL]
48 # TV 9 Kannada
49 [CHANNEL]
[all …]
H A DIntelsat21_C-58.0W1 # Intelsat 21 @ 58.0W C-BAND
4 [CHANNEL]
13 [CHANNEL]
22 [CHANNEL]
27 INNER_FEC = 9/10
31 [CHANNEL]
40 [CHANNEL]
49 [CHANNEL]
58 [CHANNEL]
63 INNER_FEC = 9/10
[all …]
H A DGalaxy16_C-99.0W1 # Galaxy 16 @ 99W C-BAND
3 [CHANNEL]
12 [CHANNEL]
21 [CHANNEL]
30 [CHANNEL]
39 [CHANNEL]
48 [CHANNEL]
57 [CHANNEL]
66 [CHANNEL]
75 [CHANNEL]
[all …]
/openbmc/linux/arch/arm/boot/dts/microchip/
H A Dat91-natte.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * at91-natte.dts - Device Tree include file for the Natte board
11 mux: mux-controller {
12 compatible = "gpio-mux";
13 #mux-control-cells = <0>;
15 mux-gpios = <&ioexp 0 GPIO_ACTIVE_HIGH>,
20 batntc-mux {
21 compatible = "io-channel-mux";
22 io-channels = <&adc 5>;
23 io-channel-names = "parent";
[all …]
/openbmc/linux/drivers/hsi/controllers/
H A Domap_ssi_regs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
33 # define SSI_DATAACCEPT(channel) (1 << (channel)) argument
34 # define SSI_DATAAVAILABLE(channel) (1 << ((channel) + 8)) argument
35 # define SSI_DATAOVERRUN(channel) (1 << ((channel) + 16)) argument
40 # define SSI_GDD_LCH(channel) (1 << (channel)) argument
44 # define SSI_WAKE(channel) (1 << (channel)) argument
62 # define SSI_FULL(channel) (1 << (channel)) argument
71 #define SSI_SST_BUFFER_CH_REG(channel) (0x80 + ((channel) * 4)) argument
72 #define SSI_SST_SWAPBUF_CH_REG(channel) (0xc0 + ((channel) * 4)) argument
82 # define SSI_NOTEMPTY(channel) (1 << (channel)) argument
[all …]
/openbmc/linux/Documentation/devicetree/bindings/iio/adc/
H A Dqcom,spmi-vadc.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/qcom,spmi-vadc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andy Gross <agross@kernel.org>
11 - Bjorn Andersson <bjorn.andersson@linaro.org>
15 voltage. The VADC is a 15-bit sigma-delta ADC.
17 voltage. The VADC is a 16-bit sigma-delta ADC.
22 - items:
23 - const: qcom,pms405-adc
[all …]
/openbmc/linux/sound/soc/sprd/
H A Dsprd-mcdt.c1 // SPDX-License-Identifier: GPL-2.0
14 #include "sprd-mcdt.h"
57 /* Channel water mark definition */
62 /* DMA channel select definition */
75 /* DMA channel ACK select definition */
78 /* Channel FIFO definition */
80 #define MCDT_CH_FIFO_ADDR_MASK GENMASK(9, 0)
121 u32 orig = readl_relaxed(mcdt->base + reg); in sprd_mcdt_update()
125 writel_relaxed(tmp, mcdt->base + reg); in sprd_mcdt_update()
128 static void sprd_mcdt_dac_set_watermark(struct sprd_mcdt_dev *mcdt, u8 channel, in sprd_mcdt_dac_set_watermark() argument
[all …]
/openbmc/linux/Documentation/devicetree/bindings/input/
H A Dazoteq,iqs7222.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jeff LaBundy <jeff@labundy.com>
21 - azoteq,iqs7222a
22 - azoteq,iqs7222b
23 - azoteq,iqs7222c
24 - azoteq,iqs7222d
29 irq-gpios:
32 Specifies the GPIO connected to the device's active-low RDY output.
[all …]
/openbmc/linux/drivers/iio/adc/
H A Dtwl6030-gpadc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2009-2013 Texas Instruments Inc.
13 * Based on twl4030-madc.c
73 * struct twl6030_chnl_calib - channel calibration
85 * struct twl6030_ideal_code - GPADC calibration parameters
89 * @channel: channel number
96 int channel; member
106 * struct twl6030_gpadc_platform_data - platform specific data
111 * @channel_to_reg: pointer to ADC function to convert channel to
119 int (*start_conversion)(int channel);
[all …]
/openbmc/u-boot/drivers/dma/
H A DMCD_tasksInit.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
22 volatile TaskTableEntry * taskTable, int channel) in MCD_startDmaChainNoEu() argument
24 volatile TaskTableEntry *taskChan = taskTable + channel; in MCD_startDmaChainNoEu()
39 MCD_SET_VAR(taskChan, 9, (u32) 0x00000000); /* var[9] */ in MCD_startDmaChainNoEu()
52 MCD_dmaBar->taskControl[channel] |= (u16) 0x8000; in MCD_startDmaChainNoEu()
60 volatile TaskTableEntry * taskTable, int channel) in MCD_startDmaSingleNoEu() argument
62 volatile TaskTableEntry *taskChan = taskTable + channel; in MCD_startDmaSingleNoEu()
76 MCD_SET_VAR(taskChan, 9, (u32) 0x00000004); /* var[9] */ in MCD_startDmaSingleNoEu()
83 MCD_dmaBar->taskControl[channel] |= (u16) 0x8000; in MCD_startDmaSingleNoEu()
[all …]
/openbmc/linux/drivers/net/ethernet/microchip/
H A Dlan743x_main.h1 /* SPDX-License-Identifier: GPL-2.0+ */
64 #define PMT_CTL_RES_CLR_WKP_MASK_ GENMASK(9, 8)
131 #define HS_E2P_CFG_I2C_BAUD_RATE_MASK_ GENMASK(9, 8)
151 #define FCT_RX_CTL_EN_(channel) BIT(28 + (channel)) argument
152 #define FCT_RX_CTL_DIS_(channel) BIT(24 + (channel)) argument
153 #define FCT_RX_CTL_RESET_(channel) BIT(20 + (channel)) argument
156 #define FCT_TX_CTL_EN_(channel) BIT(28 + (channel)) argument
157 #define FCT_TX_CTL_DIS_(channel) BIT(24 + (channel)) argument
158 #define FCT_TX_CTL_RESET_(channel) BIT(20 + (channel)) argument
233 #define MAC_WUCSR_RFE_WAKE_FR_ BIT(9)
[all …]
/openbmc/linux/Documentation/devicetree/bindings/dma/
H A Dstericsson,dma40.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST-Ericsson DMA40 DMA Engine
10 - Linus Walleij <linus.walleij@linaro.org>
13 - $ref: dma-controller.yaml#
16 "#dma-cells":
19 The first cell is the unique device channel number as indicated by this
31 9: Synchronous Serial Port SSP1
32 10: Multi-Channel Display Engine MCDE RX
[all …]
/openbmc/linux/drivers/net/wireless/zydas/zd1211rw/
H A Dzd_rf_uw2453.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* ZD1211 USB-WLAN driver for Linux
4 * Copyright (C) 2005-2007 Ulrich Kunitz <kune@deine-taler.de>
5 * Copyright (C) 2006-2007 Daniel Drake <dsd@gentoo.org>
20 /* The 3-wire serial interface provides access to 8 write-only registers.
24 /* For channel tuning, we have to configure registers 1 (synthesizer), 2 (synth
29 * of different VCO configurations on channel 1 until we detect a PLL lock.
35 * autocal configuration, which has a fixed (as opposed to per-channel) VCO
39 /* The per-channel synth values for all standard VCO configurations. These get
50 RF_CHANNEL( 9) = 0x57,
[all …]
/openbmc/u-boot/doc/device-tree-bindings/clock/
H A Drockchip,rk3288-dmc.txt3 - compatible: "rockchip,rk3288-dmc", "syscon"
4 - rockchip,cru: this driver should access cru regs, so need get cru here
5 - rockchip,grf: this driver should access grf regs, so need get grf here
6 - rockchip,pmu: this driver should access pmu regs, so need get pmu here
7 - rockchip,sgrf: this driver should access sgrf regs, so need get sgrf here
8 - rockchip,noc: this driver should access noc regs, so need get noc here
9 - reg: dynamic ram protocol controller(PCTL) address and phy controller(PHYCTL) address
10 - clock: must include clock specifiers corresponding to entries in the clock-names property.
11 - clock-output-names: from common clock binding to override the default output clock name
13 pclk_ddrupctl0: support clock for access protocol controller registers of channel 0
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dbrcm,asp-v2.0.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/brcm,asp-v2.0.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Justin Chen <justin.chen@broadcom.com>
11 - Florian Fainelli <florian.fainelli@broadcom.com>
18 - items:
19 - enum:
20 - brcm,bcm74165-asp
21 - const: brcm,asp-v2.1
[all …]
/openbmc/openbmc/meta-yadro/meta-nicole/recipes-kernel/linux/linux-aspeed/
H A D0001-Add-NCSI-channel-selector.patch4 Subject: [PATCH] Add NCSI channel selector
6 NCSI channel number is selected depending on GPIO state of a pin
11 Channel selector scheme:
12 * GPIO pin value is 0: channel 0;
13 * GPIO pin value is 1: channel 1;
14 * invalid configuration or error: channel 0.
17 new channel number.
19 Signed-off-by: Artem Senichev <a.senichev@yadro.com>
20 ---
21 net/ncsi/ncsi-rsp.c | 80 ++++++++++++++++++++++++++++++++++++++++++++-
[all …]
/openbmc/linux/drivers/net/wireless/broadcom/b43/
H A Dphy_lp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 IEEE 802.11a/g LP-PHY driver
7 Copyright (c) 2008-2009 Michael Buesch <m@bues.ch>
23 static inline u16 channel2freq_lp(u8 channel) in channel2freq_lp() argument
25 if (channel < 14) in channel2freq_lp()
26 return (2407 + 5 * channel); in channel2freq_lp()
27 else if (channel == 14) in channel2freq_lp()
29 else if (channel < 184) in channel2freq_lp()
30 return (5000 + 5 * channel); in channel2freq_lp()
32 return (4000 + 5 * channel); in channel2freq_lp()
[all …]

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