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Searched +full:cfgr +full:- +full:clk (Results 1 – 17 of 17) sorted by relevance

/openbmc/u-boot/drivers/clk/
H A Dclk_stm32f.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
8 #include <clk-uclass.h>
16 #include <dt-bindings/mfd/stm32f7-rcc.h>
147 struct stm32_rcc_regs *regs = priv->base; in configure_clocks()
148 struct stm32_pwr_regs *pwr = priv->pwr_regs; in configure_clocks()
149 struct pll_psc *sys_pll_psc = &priv->info.sys_pll_psc; in configure_clocks()
152 setbits_le32(&regs->cr, RCC_CR_HSION); in configure_clocks()
153 writel(0, &regs->cfgr); /* Reset CFGR */ in configure_clocks()
154 clrbits_le32(&regs->cr, (RCC_CR_HSEON | RCC_CR_CSSON in configure_clocks()
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H A Dclk_stm32h7.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
8 #include <clk-uclass.h>
15 #include <dt-bindings/clock/stm32h7-clks.h>
124 u32 cfgr; /* 0x10 Clock Configuration Register */ member
348 struct stm32_rcc_regs *regs = priv->rcc_base; in configure_clocks()
349 uint8_t *pwr_base = (uint8_t *)regmap_get_range(priv->pwr_regmap, 0); in configure_clocks()
355 setbits_le32(&regs->cr, RCC_CR_HSION); in configure_clocks()
356 while (!(readl(&regs->cr) & RCC_CR_HSIRDY)) in configure_clocks()
359 /* Reset CFGR, now HSI is the default system clock */ in configure_clocks()
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/openbmc/u-boot/drivers/gpio/
H A Datmel_pio4.c1 // SPDX-License-Identifier: GPL-2.0+
9 #include <clk.h>
52 return -EINVAL; in atmel_pio4_config_io_func()
56 return -EINVAL; in atmel_pio4_config_io_func()
62 writel(mask, &port_base->mskr); in atmel_pio4_config_io_func()
63 writel(reg, &port_base->cfgr); in atmel_pio4_config_io_func()
130 return -EINVAL; in atmel_pio4_set_pio_output()
134 return -EINVAL; in atmel_pio4_set_pio_output()
139 writel(mask, &port_base->mskr); in atmel_pio4_set_pio_output()
140 writel(reg, &port_base->cfgr); in atmel_pio4_set_pio_output()
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/openbmc/linux/drivers/pwm/
H A Dpwm-stm32-lp.c1 // SPDX-License-Identifier: GPL-2.0
3 * STM32 Low-Power Timer PWM driver
9 * Inspired by Gerald Baeza's pwm-stm32 driver
13 #include <linux/mfd/stm32-lptimer.h>
22 struct clk *clk; member
31 /* STM32 Low-Power Timer is preceded by a configurable power-of-2 prescaler */
40 u32 val, mask, cfgr, presc = 0; in stm32_pwm_lp_apply() local
47 if (!state->enabled) { in stm32_pwm_lp_apply()
50 ret = regmap_write(priv->regmap, STM32_LPTIM_CR, 0); in stm32_pwm_lp_apply()
54 clk_disable(priv->clk); in stm32_pwm_lp_apply()
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/openbmc/linux/drivers/mmc/host/
H A Dmmci_stm32_sdmmc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
8 #include <linux/dma-mapping.h>
84 struct sdmmc_idma *idma = host->dma_priv; in sdmmc_idma_validate_data()
85 struct device *dev = mmc_dev(host->mmc); in sdmmc_idma_validate_data()
93 idma->use_bounce_buffer = false; in sdmmc_idma_validate_data()
94 for_each_sg(data->sg, sg, data->sg_len - 1, i) { in sdmmc_idma_validate_data()
95 if (!IS_ALIGNED(sg->offset, sizeof(u32)) || in sdmmc_idma_validate_data()
96 !IS_ALIGNED(sg->length, in sdmmc_idma_validate_data()
97 host->variant->stm32_idmabsize_align)) { in sdmmc_idma_validate_data()
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/openbmc/linux/Documentation/devicetree/bindings/dma/
H A Dsnps,dw-axi-dmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/snps,dw-axi-dmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
16 - $ref: dma-controller.yaml#
21 - snps,axi-dma-1.01a
22 - intel,kmb-axi-dma
23 - starfive,jh7110-axi-dma
28 - description: Address range of the DMAC registers
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/openbmc/linux/sound/soc/stm/
H A Dstm32_i2s.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
10 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
136 #define I2S_CGFR_I2SDIV_MAX ((1 << (I2S_CGFR_I2SDIV_BIT_H -\
137 I2S_CGFR_I2SDIV_SHIFT)) - 1)
198 #define STM32_I2S_IS_MASTER(x) ((x)->ms_flg == I2S_MS_MASTER)
199 #define STM32_I2S_IS_SLAVE(x) ((x)->ms_flg == I2S_MS_SLAVE)
205 * struct stm32_i2s_data - private data of I2S
238 struct clk *i2sclk;
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/openbmc/u-boot/include/
H A Dstm32_rcc.h1 /* SPDX-License-Identifier: GPL-2.0+ */
62 u32 cfgr; /* RCC clock configuration */ member
78 u32 ahb1lpenr; /* RCC AHB1 periph clk enable in low pwr mode */
79 u32 ahb2lpenr; /* RCC AHB2 periph clk enable in low pwr mode */
80 u32 ahb3lpenr; /* RCC AHB3 periph clk enable in low pwr mode */
82 u32 apb1lpenr; /* RCC APB1 periph clk enable in low pwr mode */
83 u32 apb2lpenr; /* RCC APB2 periph clk enable in low pwr mode */
/openbmc/linux/arch/arm64/boot/dts/intel/
H A Dsocfpga_agilex5.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/clock/intel,agilex5-clkmgr.h>
14 compatible = "intel,socfpga-agilex5";
15 #address-cells = <2>;
16 #size-cells = <2>;
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/openbmc/linux/drivers/pinctrl/
H A Dpinctrl-at91-pio4.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <dt-bindings/pinctrl/at91.h>
11 #include <linux/clk.h>
21 #include <linux/pinctrl/pinconf-generic.h>
28 #include "pinctrl-utils.h"
80 * struct atmel_pioctrl_data - Atmel PIO controller (pinmux + gpio) data struct
107 * struct atmel_pioctrl - Atmel PIO controller (pinmux + gpio)
109 * @clk: clock of the controller.
131 struct clk *clk; member
145 u32 cfgr[ATMEL_PIO_NPINS_PER_BANK]; member
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/openbmc/linux/arch/arc/boot/dts/
H A Dhsdk.dts1 // SPDX-License-Identifier: GPL-2.0-only
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/reset/snps,hsdk-reset.h>
18 #address-cells = <2>;
19 #size-cells = <2>;
22 … "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
30 #address-cells = <1>;
31 #size-cells = <0>;
62 input_clk: input-clk {
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/openbmc/linux/arch/riscv/boot/dts/thead/
H A Dth1520.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <dt-bindings/interrupt-controller/irq.h>
11 #address-cells = <2>;
12 #size-cells = <2>;
15 #address-cells = <1>;
16 #size-cells = <0>;
17 timebase-frequency = <3000000>;
24 i-cache-block-size = <64>;
25 i-cache-size = <65536>;
26 i-cache-sets = <512>;
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/openbmc/linux/arch/riscv/boot/dts/canaan/
H A Dk210.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
6 #include <dt-bindings/clock/k210-clk.h>
7 #include <dt-bindings/pinctrl/k210-fpioa.h>
8 #include <dt-bindings/reset/k210-rst.h>
12 * Although the K210 is a 64-bit CPU, the address bus is only 32-bits
15 #address-cells = <1>;
16 #size-cells = <1>;
17 compatible = "canaan,kendryte-k210";
28 * Since this is a non-ratified draft specification, the kernel does not
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/openbmc/linux/sound/soc/atmel/
H A Dmchp-pdmc.c1 // SPDX-License-Identifier: GPL-2.0
5 // Copyright (C) 2019-2022 Microchip Technology Inc. and its subsidiaries
9 #include <dt-bindings/sound/microchip,pdmc.h>
12 #include <linux/clk.h>
24 * ---- PDMC Register map ----
37 * ---- Control Register (Write-only) ----
42 * ---- Mode Register (Read/Write) ----
66 * ---- Configuration Register (Read/Write) ----
75 * ---- Interrupt Enable/Disable/Mask/Status Registers ----
85 * ---- Version Register (Read-only) ----
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/openbmc/linux/arch/riscv/boot/dts/starfive/
H A Djh7110.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive,jh7110-crg.h>
9 #include <dt-bindings/power/starfive,jh7110-pmu.h>
10 #include <dt-bindings/reset/starfive,jh7110-crg.h>
11 #include <dt-bindings/thermal/thermal.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
19 #address-cells = <1>;
20 #size-cells = <0>;
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/openbmc/linux/drivers/dma/dw-axi-dmac/
H A Ddw-axi-dmac-platform.c1 // SPDX-License-Identifier: GPL-2.0
2 // (C) 2017-2018 Synopsys, Inc. (www.synopsys.com)
15 #include <linux/dma-mapping.h>
20 #include <linux/io-64-nonatomic-lo-hi.h>
32 #include "dw-axi-dmac.h"
34 #include "../virt-dma.h"
57 iowrite32(val, chip->regs + reg); in axi_dma_iowrite32()
62 return ioread32(chip->regs + reg); in axi_dma_ioread32()
68 iowrite32(val, chan->chan_regs + reg); in axi_chan_iowrite32()
73 return ioread32(chan->chan_regs + reg); in axi_chan_ioread32()
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/openbmc/linux/drivers/net/ethernet/freescale/
H A Dfec_main.c1 // SPDX-License-Identifier: GPL-2.0+
17 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
20 * Copyright (c) 2004-2006 Macq Electronique SA.
22 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
52 #include <linux/clk.h>
190 .name = "imx25-fec",
193 .name = "imx27-fec",
196 .name = "imx28-fec",
199 .name = "imx6q-fec",
202 .name = "mvf600-fec",
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