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/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_cdclk.c44 * DOC: CDCLK / RAWCLK
49 * are the core display clock (CDCLK) and RAWCLK.
51 * CDCLK clocks most of the display pipe logic, and thus its frequency
56 * On several platforms the CDCLK frequency can be changed dynamically
58 * Typically changes to the CDCLK frequency require all the display pipes
61 * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit.
62 * DMC will not change the active CDCLK frequency however, so that part
78 u8 (*calc_voltage_level)(int cdclk);
84 dev_priv->display.funcs.cdclk->get_cdclk(dev_priv, cdclk_config); in intel_cdclk_get_cdclk()
91 dev_priv->display.funcs.cdclk->set_cdclk(dev_priv, cdclk_config, pipe); in intel_cdclk_set_cdclk()
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H A Dintel_cdclk.h19 unsigned int cdclk, vco, ref, bypass; member
27 * Logical configuration of cdclk (used for all scaling,
34 * Actual configuration of cdclk, can be different from the
39 /* minimum acceptable cdclk to satisfy bandwidth requirements */
41 /* minimum acceptable cdclk for each pipe */
49 /* forced minimum cdclk for glk+ audio w/a */
55 /* update cdclk with pipes disabled */
83 …k_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->display.cdclk.obj))
85 …k_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->display.cdclk.obj))
H A Dintel_audio.c427 unsigned int fec_coeff, cdclk, vdsc_bpp; in calc_hblank_early_prog() local
435 cdclk = i915->display.cdclk.hw.cdclk; in calc_hblank_early_prog()
442 "lanes = %u vdsc_bpp = %u cdclk = %u\n", in calc_hblank_early_prog()
443 h_active, link_clk, lanes, vdsc_bpp, cdclk); in calc_hblank_early_prog()
445 if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bpp || !cdclk)) in calc_hblank_early_prog()
454 hblank_delta = DIV64_U64_ROUND_UP(mul_u32_u32(5 * (link_clk + cdclk), pixel_clk), in calc_hblank_early_prog()
455 mul_u32_u32(link_clk, cdclk)); in calc_hblank_early_prog()
887 static void get_aud_ts_cdclk_m_n(int refclk, int cdclk, struct aud_ts_cdclk_m_n *aud_ts) in get_aud_ts_cdclk_m_n() argument
890 aud_ts->n = cdclk * aud_ts->m / 24000; in get_aud_ts_cdclk_m_n()
898 get_aud_ts_cdclk_m_n(i915->display.cdclk.hw.ref, i915->display.cdclk.hw.cdclk, &aud_ts); in intel_audio_cdclk_change_post()
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H A Dhsw_ips.c203 * the increased cdclk requirement into account when in hsw_crtc_state_ips_capable()
204 * calculating the new cdclk. in hsw_crtc_state_ips_capable()
206 * Should measure whether using a lower cdclk w/o IPS in hsw_crtc_state_ips_capable()
209 crtc_state->pixel_rate > i915->display.cdclk.max_cdclk_freq * 95 / 100) in hsw_crtc_state_ips_capable()
247 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ in hsw_ips_compute_config()
248 if (crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100) in hsw_ips_compute_config()
H A Dintel_display_core.h116 * dpll and cdclk state is protected by connection_mutex dpll.lock serializes
275 /* Display CDCLK functions */
276 const struct intel_cdclk_funcs *cdclk; member
325 /* The current hardware cdclk configuration */
328 /* cdclk, divider, and ratio table from bspec */
334 } cdclk; member
H A Dintel_display_driver.c86 cdclk_state = to_intel_cdclk_state(i915->display.cdclk.obj.state); in intel_display_driver_init_hw()
89 intel_cdclk_dump_config(i915, &i915->display.cdclk.hw, "Current CDCLK"); in intel_display_driver_init_hw()
90 cdclk_state->logical = cdclk_state->actual = i915->display.cdclk.hw; in intel_display_driver_init_hw()
314 if (i915->display.cdclk.max_cdclk_freq == 0) in intel_display_driver_probe_nogem()
H A Dintel_atomic_plane.c274 * No need to check against the cdclk state if in intel_plane_calc_min_cdclk()
275 * the min cdclk for the plane doesn't increase. in intel_plane_calc_min_cdclk()
277 * Ie. we only ever increase the cdclk due to plane in intel_plane_calc_min_cdclk()
279 * display blinking due to constant cdclk changes. in intel_plane_calc_min_cdclk()
290 * No need to recalculate the cdclk state if in intel_plane_calc_min_cdclk()
291 * the min cdclk for the pipe doesn't increase. in intel_plane_calc_min_cdclk()
293 * Ie. we only ever increase the cdclk due to plane in intel_plane_calc_min_cdclk()
295 * display blinking due to constant cdclk changes. in intel_plane_calc_min_cdclk()
302 "[PLANE:%d:%s] min cdclk (%d kHz) > [CRTC:%d:%s] min cdclk (%d kHz)\n", in intel_plane_calc_min_cdclk()
H A Dintel_bw.c1175 * No need to check against the cdclk state if in intel_bw_calc_min_cdclk()
1176 * the min cdclk doesn't increase. in intel_bw_calc_min_cdclk()
1178 * Ie. we only ever increase the cdclk due to bandwidth in intel_bw_calc_min_cdclk()
1180 * display blinking due to constant cdclk changes. in intel_bw_calc_min_cdclk()
1190 * No need to recalculate the cdclk state if in intel_bw_calc_min_cdclk()
1191 * the min cdclk doesn't increase. in intel_bw_calc_min_cdclk()
1193 * Ie. we only ever increase the cdclk due to bandwidth in intel_bw_calc_min_cdclk()
1195 * display blinking due to constant cdclk changes. in intel_bw_calc_min_cdclk()
1201 "new bandwidth min cdclk (%d kHz) > old min cdclk (%d kHz)\n", in intel_bw_calc_min_cdclk()
H A Dintel_pmdemand.c292 (new_cdclk_state->actual.cdclk != in intel_pmdemand_needs_update()
293 old_cdclk_state->actual.cdclk || in intel_pmdemand_needs_update()
348 DIV_ROUND_UP(new_cdclk_state->actual.cdclk, 1000); in intel_pmdemand_atomic_check()
355 * Active_PLLs starts with 1 because of CDCLK PLL. in intel_pmdemand_atomic_check()
H A Dintel_dp_aux.c84 * The clock divider is based off the cdclk or PCH rawclk, and would in ilk_get_aux_clock_divider()
85 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and in ilk_get_aux_clock_divider()
89 freq = dev_priv->display.cdclk.hw.cdclk; in ilk_get_aux_clock_divider()
116 * derive the clock from CDCLK automatically). We still implement the in skl_get_aux_clock_divider()
H A Di9xx_plane.c379 * of cdclk when the sprite plane is enabled on the in i9xx_plane_ratio()
381 * never allowed to exceed 80% of cdclk. Let's just go in i9xx_plane_ratio()
H A Dintel_modeset_setup.c158 to_intel_cdclk_state(i915->display.cdclk.obj.state); in intel_crtc_disable_noatomic_complete()
678 to_intel_cdclk_state(i915->display.cdclk.obj.state); in intel_modeset_readout_hw_state()
H A Dintel_backlight.c1095 clock = KHz(i915->display.cdclk.hw.cdclk); in i9xx_hz_to_pwm()
1113 clock = KHz(i915->display.cdclk.hw.cdclk); in i965_hz_to_pwm()
H A Dintel_display_power.c1188 drm_err(&dev_priv->drm, "CDCLK source is not LCPLL\n"); in hsw_assert_cdclk()
1367 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK"); in hsw_restore_lcpll()
1679 /* 4. Enable CDCLK. */ in icl_display_core_init()
H A Dintel_dpll_mgr.c1375 /* DPLL0 is always enabled since it drives CDCLK */ in skl_ddi_dpll0_get_hw_state()
1873 i915->display.dpll.ref_clks.nssc = i915->display.cdclk.hw.ref; in skl_update_dpll_ref_clks()
3831 * DVFS pre sequence would be here, but in our driver the cdclk code in combo_pll_enable()
3851 * DVFS pre sequence would be here, but in our driver the cdclk code in tbt_pll_enable()
3874 * DVFS pre sequence would be here, but in our driver the cdclk code in mg_pll_enable()
3891 * DVFS pre sequence would be here, but in our driver the cdclk code in icl_pll_disable()
3945 i915->display.dpll.ref_clks.nssc = i915->display.cdclk.hw.ref; in icl_update_dpll_ref_clks()
/openbmc/u-boot/drivers/video/
H A Dbroadwell_igd.c37 int cdclk; member
399 int cdclk = plat->cdclk; in igd_cdclk_init_haswell() local
412 if (cdclk == GT_CDCLK_675) in igd_cdclk_init_haswell()
413 cdclk = GT_CDCLK_337; in igd_cdclk_init_haswell()
417 cdclk = GT_CDCLK_450; in igd_cdclk_init_haswell()
420 if (gpu_is_ulx && cdclk == GT_CDCLK_540) in igd_cdclk_init_haswell()
421 cdclk = GT_CDCLK_337; in igd_cdclk_init_haswell()
424 if (!gpu_is_ulx && !cpu_is_ult() && cdclk == GT_CDCLK_337) in igd_cdclk_init_haswell()
425 cdclk = GT_CDCLK_450; in igd_cdclk_init_haswell()
428 switch (cdclk) { in igd_cdclk_init_haswell()
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/openbmc/linux/drivers/clk/samsung/
H A Dclk-exynos-audss.c128 struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in; in exynos_audss_clk_probe() local
188 cdclk = devm_clk_get(dev, "cdclk"); in exynos_audss_clk_probe()
190 if (!IS_ERR(cdclk)) in exynos_audss_clk_probe()
191 mout_i2s_p[1] = __clk_get_name(cdclk); in exynos_audss_clk_probe()
H A Dclk-s5pv210-audss.c70 struct clk *hclk, *pll_ref, *pll_in, *cdclk, *sclk_audio; in s5pv210_audss_clk_probe() local
105 cdclk = devm_clk_get(&pdev->dev, "iiscdclk0"); in s5pv210_audss_clk_probe()
119 if (!IS_ERR(cdclk)) in s5pv210_audss_clk_probe()
120 mout_i2s_p[1] = __clk_get_name(cdclk); in s5pv210_audss_clk_probe()
/openbmc/linux/sound/hda/
H A Dhdac_i915.c20 * are used to convert CDClk (Core Display Clock) to 24MHz BCLK:
21 * BCLK = CDCLK * M / N
48 default: /* default CDCLK 450MHz */ in snd_hdac_i915_set_bclk()
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dsamsung,exynos-audss-clock.yaml52 - const: cdclk
79 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in", "cdclk";
/openbmc/linux/include/dt-bindings/sound/
H A Dsamsung-i2s.h5 #define CLK_I2S_CDCLK 0 /* the CDCLK (CODECLKO) gate clock */
/openbmc/linux/drivers/gpu/drm/i915/gt/
H A Dintel_gt_pm_debugfs.c396 drm_printf(p, "Current CD clock frequency: %d kHz\n", i915->display.cdclk.hw.cdclk); in intel_gt_pm_frequency_dump()
397 drm_printf(p, "Max CD clock frequency: %d kHz\n", i915->display.cdclk.max_cdclk_freq); in intel_gt_pm_frequency_dump()
/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dsamsung-i2s.yaml110 description: Names of the CDCLK I2S output clocks.
/openbmc/linux/arch/arm/boot/dts/samsung/
H A Ds3c64xx-pinctrl.dtsi334 i2s0_cdclk: i2s0-cdclk-pins {
346 i2s1_cdclk: i2s1-cdclk-pins {
360 i2s2_cdclk: i2s2-cdclk-pins {
/openbmc/linux/sound/soc/samsung/
H A Di2s.c1092 /* Gate CDCLK by default */ in samsung_i2s_dai_probe()
1281 const char * const i2s_clk_desc[] = { "cdclk", "rclk_src", "prescaler" }; in i2s_register_clock_provider()

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