1df0566a6SJani Nikula /*
2df0566a6SJani Nikula * Copyright © 2014 Intel Corporation
3df0566a6SJani Nikula *
4df0566a6SJani Nikula * Permission is hereby granted, free of charge, to any person obtaining a
5df0566a6SJani Nikula * copy of this software and associated documentation files (the "Software"),
6df0566a6SJani Nikula * to deal in the Software without restriction, including without limitation
7df0566a6SJani Nikula * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8df0566a6SJani Nikula * and/or sell copies of the Software, and to permit persons to whom the
9df0566a6SJani Nikula * Software is furnished to do so, subject to the following conditions:
10df0566a6SJani Nikula *
11df0566a6SJani Nikula * The above copyright notice and this permission notice (including the next
12df0566a6SJani Nikula * paragraph) shall be included in all copies or substantial portions of the
13df0566a6SJani Nikula * Software.
14df0566a6SJani Nikula *
15df0566a6SJani Nikula * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16df0566a6SJani Nikula * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17df0566a6SJani Nikula * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18df0566a6SJani Nikula * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19df0566a6SJani Nikula * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20df0566a6SJani Nikula * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21df0566a6SJani Nikula * DEALINGS IN THE SOFTWARE.
22df0566a6SJani Nikula */
23df0566a6SJani Nikula
24df0566a6SJani Nikula /**
25df0566a6SJani Nikula * DOC: atomic plane helpers
26df0566a6SJani Nikula *
27df0566a6SJani Nikula * The functions here are used by the atomic plane helper functions to
28df0566a6SJani Nikula * implement legacy plane updates (i.e., drm_plane->update_plane() and
29df0566a6SJani Nikula * drm_plane->disable_plane()). This allows plane updates to use the
30df0566a6SJani Nikula * atomic state infrastructure and perform plane updates as separate
31df0566a6SJani Nikula * prepare/check/commit/cleanup steps.
32df0566a6SJani Nikula */
33df0566a6SJani Nikula
34df0566a6SJani Nikula #include <drm/drm_atomic_helper.h>
350ec2a5b2SVille Syrjälä #include <drm/drm_blend.h>
36df0566a6SJani Nikula #include <drm/drm_fourcc.h>
37df0566a6SJani Nikula
38ff1e93e9SJani Nikula #include "i915_config.h"
39476f62b8SJani Nikula #include "i915_reg.h"
40df0566a6SJani Nikula #include "intel_atomic_plane.h"
4128a30b45SVille Syrjälä #include "intel_cdclk.h"
426dbbff25SJani Nikula #include "intel_display_rps.h"
43fd2b94a5SJani Nikula #include "intel_display_trace.h"
441d455f8dSJani Nikula #include "intel_display_types.h"
450f2922efSImre Deak #include "intel_fb.h"
46814c8757SDave Airlie #include "intel_fb_pin.h"
47c1789742SVille Syrjälä #include "skl_scaler.h"
4842a0d256SVille Syrjälä #include "skl_watermark.h"
49df0566a6SJani Nikula
intel_plane_state_reset(struct intel_plane_state * plane_state,struct intel_plane * plane)5074cb2751SVille Syrjälä static void intel_plane_state_reset(struct intel_plane_state *plane_state,
5174cb2751SVille Syrjälä struct intel_plane *plane)
5274cb2751SVille Syrjälä {
5374cb2751SVille Syrjälä memset(plane_state, 0, sizeof(*plane_state));
5474cb2751SVille Syrjälä
5574cb2751SVille Syrjälä __drm_atomic_helper_plane_state_reset(&plane_state->uapi, &plane->base);
5674cb2751SVille Syrjälä
5774cb2751SVille Syrjälä plane_state->scaler_id = -1;
5874cb2751SVille Syrjälä }
5974cb2751SVille Syrjälä
intel_plane_alloc(void)60df0566a6SJani Nikula struct intel_plane *intel_plane_alloc(void)
61df0566a6SJani Nikula {
62df0566a6SJani Nikula struct intel_plane_state *plane_state;
63df0566a6SJani Nikula struct intel_plane *plane;
64df0566a6SJani Nikula
65df0566a6SJani Nikula plane = kzalloc(sizeof(*plane), GFP_KERNEL);
66df0566a6SJani Nikula if (!plane)
67df0566a6SJani Nikula return ERR_PTR(-ENOMEM);
68df0566a6SJani Nikula
69df0566a6SJani Nikula plane_state = kzalloc(sizeof(*plane_state), GFP_KERNEL);
70df0566a6SJani Nikula if (!plane_state) {
71df0566a6SJani Nikula kfree(plane);
72df0566a6SJani Nikula return ERR_PTR(-ENOMEM);
73df0566a6SJani Nikula }
74df0566a6SJani Nikula
7574cb2751SVille Syrjälä intel_plane_state_reset(plane_state, plane);
7674cb2751SVille Syrjälä
7774cb2751SVille Syrjälä plane->base.state = &plane_state->uapi;
78df0566a6SJani Nikula
79df0566a6SJani Nikula return plane;
80df0566a6SJani Nikula }
81df0566a6SJani Nikula
intel_plane_free(struct intel_plane * plane)82df0566a6SJani Nikula void intel_plane_free(struct intel_plane *plane)
83df0566a6SJani Nikula {
84df0566a6SJani Nikula intel_plane_destroy_state(&plane->base, plane->base.state);
85df0566a6SJani Nikula kfree(plane);
86df0566a6SJani Nikula }
87df0566a6SJani Nikula
88df0566a6SJani Nikula /**
89df0566a6SJani Nikula * intel_plane_duplicate_state - duplicate plane state
90df0566a6SJani Nikula * @plane: drm plane
91df0566a6SJani Nikula *
92df0566a6SJani Nikula * Allocates and returns a copy of the plane state (both common and
93df0566a6SJani Nikula * Intel-specific) for the specified plane.
94df0566a6SJani Nikula *
95df0566a6SJani Nikula * Returns: The newly allocated plane state, or NULL on failure.
96df0566a6SJani Nikula */
97df0566a6SJani Nikula struct drm_plane_state *
intel_plane_duplicate_state(struct drm_plane * plane)98df0566a6SJani Nikula intel_plane_duplicate_state(struct drm_plane *plane)
99df0566a6SJani Nikula {
100df0566a6SJani Nikula struct intel_plane_state *intel_state;
101df0566a6SJani Nikula
1025b6edb88SMaarten Lankhorst intel_state = to_intel_plane_state(plane->state);
1035b6edb88SMaarten Lankhorst intel_state = kmemdup(intel_state, sizeof(*intel_state), GFP_KERNEL);
104df0566a6SJani Nikula
105df0566a6SJani Nikula if (!intel_state)
106df0566a6SJani Nikula return NULL;
107df0566a6SJani Nikula
108f90a85e7SMaarten Lankhorst __drm_atomic_helper_plane_duplicate_state(plane, &intel_state->uapi);
109df0566a6SJani Nikula
11033e7a975SVille Syrjälä intel_state->ggtt_vma = NULL;
11133e7a975SVille Syrjälä intel_state->dpt_vma = NULL;
112df0566a6SJani Nikula intel_state->flags = 0;
113df0566a6SJani Nikula
114380015bfSMaarten Lankhorst /* add reference to fb */
115380015bfSMaarten Lankhorst if (intel_state->hw.fb)
116380015bfSMaarten Lankhorst drm_framebuffer_get(intel_state->hw.fb);
117380015bfSMaarten Lankhorst
118f90a85e7SMaarten Lankhorst return &intel_state->uapi;
119df0566a6SJani Nikula }
120df0566a6SJani Nikula
121df0566a6SJani Nikula /**
122df0566a6SJani Nikula * intel_plane_destroy_state - destroy plane state
123df0566a6SJani Nikula * @plane: drm plane
124df0566a6SJani Nikula * @state: state object to destroy
125df0566a6SJani Nikula *
126df0566a6SJani Nikula * Destroys the plane state (both common and Intel-specific) for the
127df0566a6SJani Nikula * specified plane.
128df0566a6SJani Nikula */
129df0566a6SJani Nikula void
intel_plane_destroy_state(struct drm_plane * plane,struct drm_plane_state * state)130df0566a6SJani Nikula intel_plane_destroy_state(struct drm_plane *plane,
131df0566a6SJani Nikula struct drm_plane_state *state)
132df0566a6SJani Nikula {
1335b6edb88SMaarten Lankhorst struct intel_plane_state *plane_state = to_intel_plane_state(state);
13433e7a975SVille Syrjälä
13533e7a975SVille Syrjälä drm_WARN_ON(plane->dev, plane_state->ggtt_vma);
13633e7a975SVille Syrjälä drm_WARN_ON(plane->dev, plane_state->dpt_vma);
137df0566a6SJani Nikula
138f90a85e7SMaarten Lankhorst __drm_atomic_helper_plane_destroy_state(&plane_state->uapi);
139380015bfSMaarten Lankhorst if (plane_state->hw.fb)
140380015bfSMaarten Lankhorst drm_framebuffer_put(plane_state->hw.fb);
1415b6edb88SMaarten Lankhorst kfree(plane_state);
142df0566a6SJani Nikula }
143df0566a6SJani Nikula
intel_adjusted_rate(const struct drm_rect * src,const struct drm_rect * dst,unsigned int rate)1444028988eSVille Syrjälä unsigned int intel_adjusted_rate(const struct drm_rect *src,
145b876e79dSVille Syrjälä const struct drm_rect *dst,
146b876e79dSVille Syrjälä unsigned int rate)
1477a9ccdd1SStanislav Lisovskiy {
1487a9ccdd1SStanislav Lisovskiy unsigned int src_w, src_h, dst_w, dst_h;
1497a9ccdd1SStanislav Lisovskiy
150b876e79dSVille Syrjälä src_w = drm_rect_width(src) >> 16;
151b876e79dSVille Syrjälä src_h = drm_rect_height(src) >> 16;
152b876e79dSVille Syrjälä dst_w = drm_rect_width(dst);
153b876e79dSVille Syrjälä dst_h = drm_rect_height(dst);
1547a9ccdd1SStanislav Lisovskiy
1557a9ccdd1SStanislav Lisovskiy /* Downscaling limits the maximum pixel rate */
1567a9ccdd1SStanislav Lisovskiy dst_w = min(src_w, dst_w);
1577a9ccdd1SStanislav Lisovskiy dst_h = min(src_h, dst_h);
1587a9ccdd1SStanislav Lisovskiy
159b876e79dSVille Syrjälä return DIV_ROUND_UP_ULL(mul_u32_u32(rate, src_w * src_h),
1607a9ccdd1SStanislav Lisovskiy dst_w * dst_h);
1617a9ccdd1SStanislav Lisovskiy }
1627a9ccdd1SStanislav Lisovskiy
intel_plane_pixel_rate(const struct intel_crtc_state * crtc_state,const struct intel_plane_state * plane_state)163b876e79dSVille Syrjälä unsigned int intel_plane_pixel_rate(const struct intel_crtc_state *crtc_state,
164b876e79dSVille Syrjälä const struct intel_plane_state *plane_state)
165b876e79dSVille Syrjälä {
166b876e79dSVille Syrjälä /*
167b876e79dSVille Syrjälä * Note we don't check for plane visibility here as
168b876e79dSVille Syrjälä * we want to use this when calculating the cursor
169b876e79dSVille Syrjälä * watermarks even if the cursor is fully offscreen.
170b876e79dSVille Syrjälä * That depends on the src/dst rectangles being
171b876e79dSVille Syrjälä * correctly populated whenever the watermark code
172b876e79dSVille Syrjälä * considers the cursor to be visible, whether or not
173b876e79dSVille Syrjälä * it is actually visible.
174b876e79dSVille Syrjälä *
175b876e79dSVille Syrjälä * See: intel_wm_plane_visible() and intel_check_cursor()
176b876e79dSVille Syrjälä */
177b876e79dSVille Syrjälä
178b876e79dSVille Syrjälä return intel_adjusted_rate(&plane_state->uapi.src,
179b876e79dSVille Syrjälä &plane_state->uapi.dst,
180b876e79dSVille Syrjälä crtc_state->pixel_rate);
181b876e79dSVille Syrjälä }
182b876e79dSVille Syrjälä
intel_plane_data_rate(const struct intel_crtc_state * crtc_state,const struct intel_plane_state * plane_state,int color_plane)183df0566a6SJani Nikula unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
184943ed3ccSVille Syrjälä const struct intel_plane_state *plane_state,
185943ed3ccSVille Syrjälä int color_plane)
186df0566a6SJani Nikula {
1877b3cb17aSMaarten Lankhorst const struct drm_framebuffer *fb = plane_state->hw.fb;
188df0566a6SJani Nikula
189f90a85e7SMaarten Lankhorst if (!plane_state->uapi.visible)
190df0566a6SJani Nikula return 0;
191df0566a6SJani Nikula
192943ed3ccSVille Syrjälä return intel_plane_pixel_rate(crtc_state, plane_state) *
193943ed3ccSVille Syrjälä fb->format->cpp[color_plane];
194df0566a6SJani Nikula }
1957b3cb17aSMaarten Lankhorst
196c034363cSVille Syrjälä static bool
use_min_ddb(const struct intel_crtc_state * crtc_state,struct intel_plane * plane)197c034363cSVille Syrjälä use_min_ddb(const struct intel_crtc_state *crtc_state,
198c034363cSVille Syrjälä struct intel_plane *plane)
199c034363cSVille Syrjälä {
200c034363cSVille Syrjälä struct drm_i915_private *i915 = to_i915(plane->base.dev);
201c034363cSVille Syrjälä
202c034363cSVille Syrjälä return DISPLAY_VER(i915) >= 13 &&
203c034363cSVille Syrjälä crtc_state->uapi.async_flip &&
204c034363cSVille Syrjälä plane->async_flip;
205c034363cSVille Syrjälä }
206c034363cSVille Syrjälä
207c034363cSVille Syrjälä static unsigned int
intel_plane_relative_data_rate(const struct intel_crtc_state * crtc_state,const struct intel_plane_state * plane_state,int color_plane)208c034363cSVille Syrjälä intel_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
209c034363cSVille Syrjälä const struct intel_plane_state *plane_state,
210c034363cSVille Syrjälä int color_plane)
211c034363cSVille Syrjälä {
212c034363cSVille Syrjälä struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
213c034363cSVille Syrjälä const struct drm_framebuffer *fb = plane_state->hw.fb;
214c034363cSVille Syrjälä int width, height;
215*a86c75dcSStanislav Lisovskiy unsigned int rel_data_rate;
216c034363cSVille Syrjälä
217c034363cSVille Syrjälä if (plane->id == PLANE_CURSOR)
218c034363cSVille Syrjälä return 0;
219c034363cSVille Syrjälä
220c034363cSVille Syrjälä if (!plane_state->uapi.visible)
221c034363cSVille Syrjälä return 0;
222def85091SChris Wilson
223def85091SChris Wilson /*
224c034363cSVille Syrjälä * We calculate extra ddb based on ratio plane rate/total data rate
225c034363cSVille Syrjälä * in case, in some cases we should not allocate extra ddb for the plane,
226c034363cSVille Syrjälä * so do not count its data rate, if this is the case.
227def85091SChris Wilson */
228c034363cSVille Syrjälä if (use_min_ddb(crtc_state, plane))
229c034363cSVille Syrjälä return 0;
23028a30b45SVille Syrjälä
231c034363cSVille Syrjälä /*
232c034363cSVille Syrjälä * Src coordinates are already rotated by 270 degrees for
233c034363cSVille Syrjälä * the 90/270 degree plane rotation cases (to match the
234c034363cSVille Syrjälä * GTT mapping), hence no need to account for rotation here.
235c034363cSVille Syrjälä */
236c034363cSVille Syrjälä width = drm_rect_width(&plane_state->uapi.src) >> 16;
237c034363cSVille Syrjälä height = drm_rect_height(&plane_state->uapi.src) >> 16;
238c034363cSVille Syrjälä
239c034363cSVille Syrjälä /* UV plane does 1/2 pixel sub-sampling */
240c034363cSVille Syrjälä if (color_plane == 1) {
241c034363cSVille Syrjälä width /= 2;
242c034363cSVille Syrjälä height /= 2;
243c034363cSVille Syrjälä }
244c034363cSVille Syrjälä
245*a86c75dcSStanislav Lisovskiy rel_data_rate = width * height * fb->format->cpp[color_plane];
246*a86c75dcSStanislav Lisovskiy
247*a86c75dcSStanislav Lisovskiy return intel_adjusted_rate(&plane_state->uapi.src,
248*a86c75dcSStanislav Lisovskiy &plane_state->uapi.dst,
249*a86c75dcSStanislav Lisovskiy rel_data_rate);
250df0566a6SJani Nikula }
251df0566a6SJani Nikula
intel_plane_calc_min_cdclk(struct intel_atomic_state * state,struct intel_plane * plane,bool * need_cdclk_calc)252df0566a6SJani Nikula int intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
253df0566a6SJani Nikula struct intel_plane *plane,
254df0566a6SJani Nikula bool *need_cdclk_calc)
255df0566a6SJani Nikula {
256df0566a6SJani Nikula struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
257bb6ae9e6SVille Syrjälä const struct intel_plane_state *plane_state =
258bb6ae9e6SVille Syrjälä intel_atomic_get_new_plane_state(state, plane);
259bb6ae9e6SVille Syrjälä struct intel_crtc *crtc = to_intel_crtc(plane_state->hw.crtc);
260bb6ae9e6SVille Syrjälä const struct intel_cdclk_state *cdclk_state;
261bb6ae9e6SVille Syrjälä const struct intel_crtc_state *old_crtc_state;
262bb6ae9e6SVille Syrjälä struct intel_crtc_state *new_crtc_state;
263bb6ae9e6SVille Syrjälä
264bb6ae9e6SVille Syrjälä if (!plane_state->uapi.visible || !plane->min_cdclk)
265bb6ae9e6SVille Syrjälä return 0;
266f90a85e7SMaarten Lankhorst
267bb6ae9e6SVille Syrjälä old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
268bb6ae9e6SVille Syrjälä new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
26928a30b45SVille Syrjälä
27028a30b45SVille Syrjälä new_crtc_state->min_cdclk[plane->id] =
271bb6ae9e6SVille Syrjälä plane->min_cdclk(new_crtc_state, plane_state);
272bb6ae9e6SVille Syrjälä
27328a30b45SVille Syrjälä /*
27428a30b45SVille Syrjälä * No need to check against the cdclk state if
275bb6ae9e6SVille Syrjälä * the min cdclk for the plane doesn't increase.
27628a30b45SVille Syrjälä *
27728a30b45SVille Syrjälä * Ie. we only ever increase the cdclk due to plane
27828a30b45SVille Syrjälä * requirements. This can reduce back and forth
279bb6ae9e6SVille Syrjälä * display blinking due to constant cdclk changes.
28028a30b45SVille Syrjälä */
28128a30b45SVille Syrjälä if (new_crtc_state->min_cdclk[plane->id] <=
28228a30b45SVille Syrjälä old_crtc_state->min_cdclk[plane->id])
283bb6ae9e6SVille Syrjälä return 0;
28428a30b45SVille Syrjälä
28528a30b45SVille Syrjälä cdclk_state = intel_atomic_get_cdclk_state(state);
28628a30b45SVille Syrjälä if (IS_ERR(cdclk_state))
28728a30b45SVille Syrjälä return PTR_ERR(cdclk_state);
28828a30b45SVille Syrjälä
28928a30b45SVille Syrjälä /*
29028a30b45SVille Syrjälä * No need to recalculate the cdclk state if
29128a30b45SVille Syrjälä * the min cdclk for the pipe doesn't increase.
29228a30b45SVille Syrjälä *
29328a30b45SVille Syrjälä * Ie. we only ever increase the cdclk due to plane
29428a30b45SVille Syrjälä * requirements. This can reduce back and forth
29528a30b45SVille Syrjälä * display blinking due to constant cdclk changes.
29628a30b45SVille Syrjälä */
29728a30b45SVille Syrjälä if (new_crtc_state->min_cdclk[plane->id] <=
29828a30b45SVille Syrjälä cdclk_state->min_cdclk[crtc->pipe])
29928a30b45SVille Syrjälä return 0;
30028a30b45SVille Syrjälä
30128a30b45SVille Syrjälä drm_dbg_kms(&dev_priv->drm,
30228a30b45SVille Syrjälä "[PLANE:%d:%s] min cdclk (%d kHz) > [CRTC:%d:%s] min cdclk (%d kHz)\n",
30328a30b45SVille Syrjälä plane->base.base.id, plane->base.name,
30428a30b45SVille Syrjälä new_crtc_state->min_cdclk[plane->id],
30528a30b45SVille Syrjälä crtc->base.base.id, crtc->base.name,
30628a30b45SVille Syrjälä cdclk_state->min_cdclk[crtc->pipe]);
30728a30b45SVille Syrjälä *need_cdclk_calc = true;
30828a30b45SVille Syrjälä
309bb6ae9e6SVille Syrjälä return 0;
310bb6ae9e6SVille Syrjälä }
311380015bfSMaarten Lankhorst
intel_plane_clear_hw_state(struct intel_plane_state * plane_state)312380015bfSMaarten Lankhorst static void intel_plane_clear_hw_state(struct intel_plane_state *plane_state)
313380015bfSMaarten Lankhorst {
314380015bfSMaarten Lankhorst if (plane_state->hw.fb)
315380015bfSMaarten Lankhorst drm_framebuffer_put(plane_state->hw.fb);
316380015bfSMaarten Lankhorst
317380015bfSMaarten Lankhorst memset(&plane_state->hw, 0, sizeof(plane_state->hw));
318380015bfSMaarten Lankhorst }
319380015bfSMaarten Lankhorst
intel_plane_copy_uapi_to_hw_state(struct intel_plane_state * plane_state,const struct intel_plane_state * from_plane_state,struct intel_crtc * crtc)320380015bfSMaarten Lankhorst void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
3218246d9c7SVille Syrjälä const struct intel_plane_state *from_plane_state,
3228246d9c7SVille Syrjälä struct intel_crtc *crtc)
323380015bfSMaarten Lankhorst {
324380015bfSMaarten Lankhorst intel_plane_clear_hw_state(plane_state);
325380015bfSMaarten Lankhorst
3268246d9c7SVille Syrjälä /*
3278246d9c7SVille Syrjälä * For the bigjoiner slave uapi.crtc will point at
3288246d9c7SVille Syrjälä * the master crtc. So we explicitly assign the right
3298246d9c7SVille Syrjälä * slave crtc to hw.crtc. uapi.crtc!=NULL simply indicates
3308246d9c7SVille Syrjälä * the plane is logically enabled on the uapi level.
3318246d9c7SVille Syrjälä */
3328246d9c7SVille Syrjälä plane_state->hw.crtc = from_plane_state->uapi.crtc ? &crtc->base : NULL;
3338246d9c7SVille Syrjälä
334380015bfSMaarten Lankhorst plane_state->hw.fb = from_plane_state->uapi.fb;
335380015bfSMaarten Lankhorst if (plane_state->hw.fb)
336380015bfSMaarten Lankhorst drm_framebuffer_get(plane_state->hw.fb);
337380015bfSMaarten Lankhorst
338380015bfSMaarten Lankhorst plane_state->hw.alpha = from_plane_state->uapi.alpha;
339380015bfSMaarten Lankhorst plane_state->hw.pixel_blend_mode =
340380015bfSMaarten Lankhorst from_plane_state->uapi.pixel_blend_mode;
341380015bfSMaarten Lankhorst plane_state->hw.rotation = from_plane_state->uapi.rotation;
342380015bfSMaarten Lankhorst plane_state->hw.color_encoding = from_plane_state->uapi.color_encoding;
343380015bfSMaarten Lankhorst plane_state->hw.color_range = from_plane_state->uapi.color_range;
3446d1a2fdeSPankaj Bharadiya plane_state->hw.scaling_filter = from_plane_state->uapi.scaling_filter;
3459f05a7c0SMaarten Lankhorst
3469f05a7c0SMaarten Lankhorst plane_state->uapi.src = drm_plane_state_src(&from_plane_state->uapi);
3479f05a7c0SMaarten Lankhorst plane_state->uapi.dst = drm_plane_state_dest(&from_plane_state->uapi);
348380015bfSMaarten Lankhorst }
349380015bfSMaarten Lankhorst
intel_plane_copy_hw_state(struct intel_plane_state * plane_state,const struct intel_plane_state * from_plane_state)350e85e7458SVille Syrjälä void intel_plane_copy_hw_state(struct intel_plane_state *plane_state,
351e85e7458SVille Syrjälä const struct intel_plane_state *from_plane_state)
352e85e7458SVille Syrjälä {
353e85e7458SVille Syrjälä intel_plane_clear_hw_state(plane_state);
354e85e7458SVille Syrjälä
355e85e7458SVille Syrjälä memcpy(&plane_state->hw, &from_plane_state->hw,
356e85e7458SVille Syrjälä sizeof(plane_state->hw));
357e85e7458SVille Syrjälä
358e85e7458SVille Syrjälä if (plane_state->hw.fb)
359e85e7458SVille Syrjälä drm_framebuffer_get(plane_state->hw.fb);
360e85e7458SVille Syrjälä }
361e85e7458SVille Syrjälä
intel_plane_set_invisible(struct intel_crtc_state * crtc_state,struct intel_plane_state * plane_state)362cb1824bbSVille Syrjälä void intel_plane_set_invisible(struct intel_crtc_state *crtc_state,
363cb1824bbSVille Syrjälä struct intel_plane_state *plane_state)
364cb1824bbSVille Syrjälä {
365cb1824bbSVille Syrjälä struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
366cb1824bbSVille Syrjälä
367cb1824bbSVille Syrjälä crtc_state->active_planes &= ~BIT(plane->id);
3683358e2caSVille Syrjälä crtc_state->scaled_planes &= ~BIT(plane->id);
369cb1824bbSVille Syrjälä crtc_state->nv12_planes &= ~BIT(plane->id);
370cb1824bbSVille Syrjälä crtc_state->c8_planes &= ~BIT(plane->id);
3719d691c19SAndrzej Hajda crtc_state->async_flip_planes &= ~BIT(plane->id);
372cb1824bbSVille Syrjälä crtc_state->data_rate[plane->id] = 0;
373943ed3ccSVille Syrjälä crtc_state->data_rate_y[plane->id] = 0;
374c034363cSVille Syrjälä crtc_state->rel_data_rate[plane->id] = 0;
375c034363cSVille Syrjälä crtc_state->rel_data_rate_y[plane->id] = 0;
376cb1824bbSVille Syrjälä crtc_state->min_cdclk[plane->id] = 0;
377cb1824bbSVille Syrjälä
378cb1824bbSVille Syrjälä plane_state->uapi.visible = false;
379cb1824bbSVille Syrjälä }
380cb1824bbSVille Syrjälä
381c1789742SVille Syrjälä /* FIXME nuke when all wm code is atomic */
intel_wm_need_update(const struct intel_plane_state * cur,struct intel_plane_state * new)382c1789742SVille Syrjälä static bool intel_wm_need_update(const struct intel_plane_state *cur,
383c1789742SVille Syrjälä struct intel_plane_state *new)
384c1789742SVille Syrjälä {
385c1789742SVille Syrjälä /* Update watermarks on tiling or size changes. */
386c1789742SVille Syrjälä if (new->uapi.visible != cur->uapi.visible)
387c1789742SVille Syrjälä return true;
388c1789742SVille Syrjälä
389c1789742SVille Syrjälä if (!cur->hw.fb || !new->hw.fb)
390c1789742SVille Syrjälä return false;
391c1789742SVille Syrjälä
392c1789742SVille Syrjälä if (cur->hw.fb->modifier != new->hw.fb->modifier ||
393c1789742SVille Syrjälä cur->hw.rotation != new->hw.rotation ||
394c1789742SVille Syrjälä drm_rect_width(&new->uapi.src) != drm_rect_width(&cur->uapi.src) ||
395c1789742SVille Syrjälä drm_rect_height(&new->uapi.src) != drm_rect_height(&cur->uapi.src) ||
396c1789742SVille Syrjälä drm_rect_width(&new->uapi.dst) != drm_rect_width(&cur->uapi.dst) ||
397c1789742SVille Syrjälä drm_rect_height(&new->uapi.dst) != drm_rect_height(&cur->uapi.dst))
398c1789742SVille Syrjälä return true;
399c1789742SVille Syrjälä
400c1789742SVille Syrjälä return false;
401c1789742SVille Syrjälä }
402c1789742SVille Syrjälä
intel_plane_is_scaled(const struct intel_plane_state * plane_state)403c1789742SVille Syrjälä static bool intel_plane_is_scaled(const struct intel_plane_state *plane_state)
404c1789742SVille Syrjälä {
405c1789742SVille Syrjälä int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
406c1789742SVille Syrjälä int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
407c1789742SVille Syrjälä int dst_w = drm_rect_width(&plane_state->uapi.dst);
408c1789742SVille Syrjälä int dst_h = drm_rect_height(&plane_state->uapi.dst);
409c1789742SVille Syrjälä
410c1789742SVille Syrjälä return src_w != dst_w || src_h != dst_h;
411c1789742SVille Syrjälä }
412c1789742SVille Syrjälä
intel_plane_do_async_flip(struct intel_plane * plane,const struct intel_crtc_state * old_crtc_state,const struct intel_crtc_state * new_crtc_state)413c1789742SVille Syrjälä static bool intel_plane_do_async_flip(struct intel_plane *plane,
414c1789742SVille Syrjälä const struct intel_crtc_state *old_crtc_state,
415c1789742SVille Syrjälä const struct intel_crtc_state *new_crtc_state)
416c1789742SVille Syrjälä {
417c1789742SVille Syrjälä struct drm_i915_private *i915 = to_i915(plane->base.dev);
418c1789742SVille Syrjälä
419c1789742SVille Syrjälä if (!plane->async_flip)
420c1789742SVille Syrjälä return false;
421c1789742SVille Syrjälä
422c1789742SVille Syrjälä if (!new_crtc_state->uapi.async_flip)
423c1789742SVille Syrjälä return false;
424c1789742SVille Syrjälä
425c1789742SVille Syrjälä /*
426c1789742SVille Syrjälä * In platforms after DISPLAY13, we might need to override
427c1789742SVille Syrjälä * first async flip in order to change watermark levels
428c1789742SVille Syrjälä * as part of optimization.
429c1789742SVille Syrjälä * So for those, we are checking if this is a first async flip.
430c1789742SVille Syrjälä * For platforms earlier than DISPLAY13 we always do async flip.
431c1789742SVille Syrjälä */
432c1789742SVille Syrjälä return DISPLAY_VER(i915) < 13 || old_crtc_state->uapi.async_flip;
433c1789742SVille Syrjälä }
434c1789742SVille Syrjälä
i9xx_must_disable_cxsr(const struct intel_crtc_state * new_crtc_state,const struct intel_plane_state * old_plane_state,const struct intel_plane_state * new_plane_state)4358c45f31cSVille Syrjälä static bool i9xx_must_disable_cxsr(const struct intel_crtc_state *new_crtc_state,
4368c45f31cSVille Syrjälä const struct intel_plane_state *old_plane_state,
4378c45f31cSVille Syrjälä const struct intel_plane_state *new_plane_state)
4388c45f31cSVille Syrjälä {
4398c45f31cSVille Syrjälä struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);
4408c45f31cSVille Syrjälä bool old_visible = old_plane_state->uapi.visible;
4418c45f31cSVille Syrjälä bool new_visible = new_plane_state->uapi.visible;
4428c45f31cSVille Syrjälä u32 old_ctl = old_plane_state->ctl;
4438c45f31cSVille Syrjälä u32 new_ctl = new_plane_state->ctl;
4448c45f31cSVille Syrjälä bool modeset, turn_on, turn_off;
4458c45f31cSVille Syrjälä
4468c45f31cSVille Syrjälä if (plane->id == PLANE_CURSOR)
4478c45f31cSVille Syrjälä return false;
4488c45f31cSVille Syrjälä
4498c45f31cSVille Syrjälä modeset = intel_crtc_needs_modeset(new_crtc_state);
4508c45f31cSVille Syrjälä turn_off = old_visible && (!new_visible || modeset);
4518c45f31cSVille Syrjälä turn_on = new_visible && (!old_visible || modeset);
4528c45f31cSVille Syrjälä
4538c45f31cSVille Syrjälä /* Must disable CxSR around plane enable/disable */
4548c45f31cSVille Syrjälä if (turn_on || turn_off)
4558c45f31cSVille Syrjälä return true;
4568c45f31cSVille Syrjälä
4578c45f31cSVille Syrjälä if (!old_visible || !new_visible)
4588c45f31cSVille Syrjälä return false;
4598c45f31cSVille Syrjälä
4608c45f31cSVille Syrjälä /*
4618c45f31cSVille Syrjälä * Most plane control register updates are blocked while in CxSR.
4628c45f31cSVille Syrjälä *
4638c45f31cSVille Syrjälä * Tiling mode is one exception where the primary plane can
4648c45f31cSVille Syrjälä * apparently handle it, whereas the sprites can not (the
4658c45f31cSVille Syrjälä * sprite issue being only relevant on VLV/CHV where CxSR
4668c45f31cSVille Syrjälä * is actually possible with a sprite enabled).
4678c45f31cSVille Syrjälä */
4688c45f31cSVille Syrjälä if (plane->id == PLANE_PRIMARY) {
4698c45f31cSVille Syrjälä old_ctl &= ~DISP_TILED;
4708c45f31cSVille Syrjälä new_ctl &= ~DISP_TILED;
4718c45f31cSVille Syrjälä }
4728c45f31cSVille Syrjälä
4738c45f31cSVille Syrjälä return old_ctl != new_ctl;
4748c45f31cSVille Syrjälä }
4758c45f31cSVille Syrjälä
intel_plane_atomic_calc_changes(const struct intel_crtc_state * old_crtc_state,struct intel_crtc_state * new_crtc_state,const struct intel_plane_state * old_plane_state,struct intel_plane_state * new_plane_state)476c1789742SVille Syrjälä static int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
477c1789742SVille Syrjälä struct intel_crtc_state *new_crtc_state,
478c1789742SVille Syrjälä const struct intel_plane_state *old_plane_state,
479c1789742SVille Syrjälä struct intel_plane_state *new_plane_state)
480c1789742SVille Syrjälä {
481c1789742SVille Syrjälä struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
482c1789742SVille Syrjälä struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);
483c1789742SVille Syrjälä struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
484c1789742SVille Syrjälä bool mode_changed = intel_crtc_needs_modeset(new_crtc_state);
485c1789742SVille Syrjälä bool was_crtc_enabled = old_crtc_state->hw.active;
486c1789742SVille Syrjälä bool is_crtc_enabled = new_crtc_state->hw.active;
487c1789742SVille Syrjälä bool turn_off, turn_on, visible, was_visible;
488c1789742SVille Syrjälä int ret;
489c1789742SVille Syrjälä
490c1789742SVille Syrjälä if (DISPLAY_VER(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
491c1789742SVille Syrjälä ret = skl_update_scaler_plane(new_crtc_state, new_plane_state);
492c1789742SVille Syrjälä if (ret)
493c1789742SVille Syrjälä return ret;
494c1789742SVille Syrjälä }
495c1789742SVille Syrjälä
496c1789742SVille Syrjälä was_visible = old_plane_state->uapi.visible;
497c1789742SVille Syrjälä visible = new_plane_state->uapi.visible;
498c1789742SVille Syrjälä
499c1789742SVille Syrjälä if (!was_crtc_enabled && drm_WARN_ON(&dev_priv->drm, was_visible))
500c1789742SVille Syrjälä was_visible = false;
501c1789742SVille Syrjälä
502c1789742SVille Syrjälä /*
503c1789742SVille Syrjälä * Visibility is calculated as if the crtc was on, but
504c1789742SVille Syrjälä * after scaler setup everything depends on it being off
505c1789742SVille Syrjälä * when the crtc isn't active.
506c1789742SVille Syrjälä *
507c1789742SVille Syrjälä * FIXME this is wrong for watermarks. Watermarks should also
508c1789742SVille Syrjälä * be computed as if the pipe would be active. Perhaps move
509c1789742SVille Syrjälä * per-plane wm computation to the .check_plane() hook, and
510c1789742SVille Syrjälä * only combine the results from all planes in the current place?
511c1789742SVille Syrjälä */
512c1789742SVille Syrjälä if (!is_crtc_enabled) {
513c1789742SVille Syrjälä intel_plane_set_invisible(new_crtc_state, new_plane_state);
514c1789742SVille Syrjälä visible = false;
515c1789742SVille Syrjälä }
516c1789742SVille Syrjälä
517c1789742SVille Syrjälä if (!was_visible && !visible)
518c1789742SVille Syrjälä return 0;
519c1789742SVille Syrjälä
520c1789742SVille Syrjälä turn_off = was_visible && (!visible || mode_changed);
521c1789742SVille Syrjälä turn_on = visible && (!was_visible || mode_changed);
522c1789742SVille Syrjälä
523c1789742SVille Syrjälä drm_dbg_atomic(&dev_priv->drm,
524c1789742SVille Syrjälä "[CRTC:%d:%s] with [PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
525c1789742SVille Syrjälä crtc->base.base.id, crtc->base.name,
526c1789742SVille Syrjälä plane->base.base.id, plane->base.name,
527c1789742SVille Syrjälä was_visible, visible,
528c1789742SVille Syrjälä turn_off, turn_on, mode_changed);
529c1789742SVille Syrjälä
530c1789742SVille Syrjälä if (turn_on) {
531c1789742SVille Syrjälä if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
532c1789742SVille Syrjälä new_crtc_state->update_wm_pre = true;
533c1789742SVille Syrjälä } else if (turn_off) {
534c1789742SVille Syrjälä if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
535c1789742SVille Syrjälä new_crtc_state->update_wm_post = true;
536c1789742SVille Syrjälä } else if (intel_wm_need_update(old_plane_state, new_plane_state)) {
537c1789742SVille Syrjälä if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv)) {
538c1789742SVille Syrjälä /* FIXME bollocks */
539c1789742SVille Syrjälä new_crtc_state->update_wm_pre = true;
540c1789742SVille Syrjälä new_crtc_state->update_wm_post = true;
541c1789742SVille Syrjälä }
542c1789742SVille Syrjälä }
543c1789742SVille Syrjälä
544c1789742SVille Syrjälä if (visible || was_visible)
545c1789742SVille Syrjälä new_crtc_state->fb_bits |= plane->frontbuffer_bit;
546c1789742SVille Syrjälä
5478c45f31cSVille Syrjälä if (HAS_GMCH(dev_priv) &&
5488c45f31cSVille Syrjälä i9xx_must_disable_cxsr(new_crtc_state, old_plane_state, new_plane_state))
5498c45f31cSVille Syrjälä new_crtc_state->disable_cxsr = true;
5508c45f31cSVille Syrjälä
551c1789742SVille Syrjälä /*
552c1789742SVille Syrjälä * ILK/SNB DVSACNTR/Sprite Enable
553c1789742SVille Syrjälä * IVB SPR_CTL/Sprite Enable
554c1789742SVille Syrjälä * "When in Self Refresh Big FIFO mode, a write to enable the
555c1789742SVille Syrjälä * plane will be internally buffered and delayed while Big FIFO
556c1789742SVille Syrjälä * mode is exiting."
557c1789742SVille Syrjälä *
558c1789742SVille Syrjälä * Which means that enabling the sprite can take an extra frame
559c1789742SVille Syrjälä * when we start in big FIFO mode (LP1+). Thus we need to drop
560c1789742SVille Syrjälä * down to LP0 and wait for vblank in order to make sure the
561c1789742SVille Syrjälä * sprite gets enabled on the next vblank after the register write.
562c1789742SVille Syrjälä * Doing otherwise would risk enabling the sprite one frame after
563c1789742SVille Syrjälä * we've already signalled flip completion. We can resume LP1+
564c1789742SVille Syrjälä * once the sprite has been enabled.
565c1789742SVille Syrjälä *
566c1789742SVille Syrjälä *
567c1789742SVille Syrjälä * WaCxSRDisabledForSpriteScaling:ivb
568c1789742SVille Syrjälä * IVB SPR_SCALE/Scaling Enable
569c1789742SVille Syrjälä * "Low Power watermarks must be disabled for at least one
570c1789742SVille Syrjälä * frame before enabling sprite scaling, and kept disabled
571c1789742SVille Syrjälä * until sprite scaling is disabled."
572c1789742SVille Syrjälä *
573c1789742SVille Syrjälä * ILK/SNB DVSASCALE/Scaling Enable
574c1789742SVille Syrjälä * "When in Self Refresh Big FIFO mode, scaling enable will be
575c1789742SVille Syrjälä * masked off while Big FIFO mode is exiting."
576c1789742SVille Syrjälä *
577c1789742SVille Syrjälä * Despite the w/a only being listed for IVB we assume that
578c1789742SVille Syrjälä * the ILK/SNB note has similar ramifications, hence we apply
579c1789742SVille Syrjälä * the w/a on all three platforms.
580c1789742SVille Syrjälä *
581c1789742SVille Syrjälä * With experimental results seems this is needed also for primary
582c1789742SVille Syrjälä * plane, not only sprite plane.
583c1789742SVille Syrjälä */
584c1789742SVille Syrjälä if (plane->id != PLANE_CURSOR &&
585c1789742SVille Syrjälä (IS_IRONLAKE(dev_priv) || IS_SANDYBRIDGE(dev_priv) ||
586c1789742SVille Syrjälä IS_IVYBRIDGE(dev_priv)) &&
587c1789742SVille Syrjälä (turn_on || (!intel_plane_is_scaled(old_plane_state) &&
588c1789742SVille Syrjälä intel_plane_is_scaled(new_plane_state))))
589c1789742SVille Syrjälä new_crtc_state->disable_lp_wm = true;
590c1789742SVille Syrjälä
5919d691c19SAndrzej Hajda if (intel_plane_do_async_flip(plane, old_crtc_state, new_crtc_state)) {
5925c8107dcSVille Syrjälä new_crtc_state->do_async_flip = true;
5939d691c19SAndrzej Hajda new_crtc_state->async_flip_planes |= BIT(plane->id);
5949d691c19SAndrzej Hajda }
595c1789742SVille Syrjälä
596c1789742SVille Syrjälä return 0;
597c1789742SVille Syrjälä }
598c1789742SVille Syrjälä
intel_plane_atomic_check_with_state(const struct intel_crtc_state * old_crtc_state,struct intel_crtc_state * new_crtc_state,const struct intel_plane_state * old_plane_state,struct intel_plane_state * new_plane_state)599df0566a6SJani Nikula int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
600df0566a6SJani Nikula struct intel_crtc_state *new_crtc_state,
601df0566a6SJani Nikula const struct intel_plane_state *old_plane_state,
602df0566a6SJani Nikula struct intel_plane_state *new_plane_state)
603df0566a6SJani Nikula {
604f90a85e7SMaarten Lankhorst struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);
6057d8d2cbcSVille Syrjälä const struct drm_framebuffer *fb = new_plane_state->hw.fb;
606df0566a6SJani Nikula int ret;
607df0566a6SJani Nikula
608cb1824bbSVille Syrjälä intel_plane_set_invisible(new_crtc_state, new_plane_state);
609ee42ec19SVille Syrjälä new_crtc_state->enabled_planes &= ~BIT(plane->id);
610df0566a6SJani Nikula
6117b3cb17aSMaarten Lankhorst if (!new_plane_state->hw.crtc && !old_plane_state->hw.crtc)
612df0566a6SJani Nikula return 0;
613df0566a6SJani Nikula
614df0566a6SJani Nikula ret = plane->check_plane(new_crtc_state, new_plane_state);
615df0566a6SJani Nikula if (ret)
616df0566a6SJani Nikula return ret;
617df0566a6SJani Nikula
61897bc7ffaSVille Syrjälä if (fb)
61997bc7ffaSVille Syrjälä new_crtc_state->enabled_planes |= BIT(plane->id);
62097bc7ffaSVille Syrjälä
621df0566a6SJani Nikula /* FIXME pre-g4x don't work like this */
622f90a85e7SMaarten Lankhorst if (new_plane_state->uapi.visible)
623df0566a6SJani Nikula new_crtc_state->active_planes |= BIT(plane->id);
624df0566a6SJani Nikula
625f90a85e7SMaarten Lankhorst if (new_plane_state->uapi.visible &&
6263358e2caSVille Syrjälä intel_plane_is_scaled(new_plane_state))
6273358e2caSVille Syrjälä new_crtc_state->scaled_planes |= BIT(plane->id);
6283358e2caSVille Syrjälä
6293358e2caSVille Syrjälä if (new_plane_state->uapi.visible &&
6304941f35bSImre Deak intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
631df0566a6SJani Nikula new_crtc_state->nv12_planes |= BIT(plane->id);
632df0566a6SJani Nikula
633f90a85e7SMaarten Lankhorst if (new_plane_state->uapi.visible &&
634d1d23d7fSVille Syrjälä fb->format->format == DRM_FORMAT_C8)
635df0566a6SJani Nikula new_crtc_state->c8_planes |= BIT(plane->id);
636df0566a6SJani Nikula
637f90a85e7SMaarten Lankhorst if (new_plane_state->uapi.visible || old_plane_state->uapi.visible)
638df0566a6SJani Nikula new_crtc_state->update_planes |= BIT(plane->id);
639df0566a6SJani Nikula
640943ed3ccSVille Syrjälä if (new_plane_state->uapi.visible &&
641943ed3ccSVille Syrjälä intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) {
642943ed3ccSVille Syrjälä new_crtc_state->data_rate_y[plane->id] =
643943ed3ccSVille Syrjälä intel_plane_data_rate(new_crtc_state, new_plane_state, 0);
644df0566a6SJani Nikula new_crtc_state->data_rate[plane->id] =
645943ed3ccSVille Syrjälä intel_plane_data_rate(new_crtc_state, new_plane_state, 1);
646c034363cSVille Syrjälä
647c034363cSVille Syrjälä new_crtc_state->rel_data_rate_y[plane->id] =
648c034363cSVille Syrjälä intel_plane_relative_data_rate(new_crtc_state,
649c034363cSVille Syrjälä new_plane_state, 0);
650c034363cSVille Syrjälä new_crtc_state->rel_data_rate[plane->id] =
651c034363cSVille Syrjälä intel_plane_relative_data_rate(new_crtc_state,
652c034363cSVille Syrjälä new_plane_state, 1);
653943ed3ccSVille Syrjälä } else if (new_plane_state->uapi.visible) {
654943ed3ccSVille Syrjälä new_crtc_state->data_rate[plane->id] =
655943ed3ccSVille Syrjälä intel_plane_data_rate(new_crtc_state, new_plane_state, 0);
656c034363cSVille Syrjälä
657c034363cSVille Syrjälä new_crtc_state->rel_data_rate[plane->id] =
658c034363cSVille Syrjälä intel_plane_relative_data_rate(new_crtc_state,
659c034363cSVille Syrjälä new_plane_state, 0);
660943ed3ccSVille Syrjälä }
661df0566a6SJani Nikula
6624f25720bSMaarten Lankhorst return intel_plane_atomic_calc_changes(old_crtc_state, new_crtc_state,
6634f25720bSMaarten Lankhorst old_plane_state, new_plane_state);
664df0566a6SJani Nikula }
665df0566a6SJani Nikula
6668246d9c7SVille Syrjälä static struct intel_plane *
intel_crtc_get_plane(struct intel_crtc * crtc,enum plane_id plane_id)6678246d9c7SVille Syrjälä intel_crtc_get_plane(struct intel_crtc *crtc, enum plane_id plane_id)
668df0566a6SJani Nikula {
6698246d9c7SVille Syrjälä struct drm_i915_private *i915 = to_i915(crtc->base.dev);
6708246d9c7SVille Syrjälä struct intel_plane *plane;
671df0566a6SJani Nikula
6728246d9c7SVille Syrjälä for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) {
6738246d9c7SVille Syrjälä if (plane->id == plane_id)
6748246d9c7SVille Syrjälä return plane;
6758246d9c7SVille Syrjälä }
6764f25720bSMaarten Lankhorst
6774f25720bSMaarten Lankhorst return NULL;
6784f25720bSMaarten Lankhorst }
6794f25720bSMaarten Lankhorst
intel_plane_atomic_check(struct intel_atomic_state * state,struct intel_plane * plane)680131d3b1aSVille Syrjälä int intel_plane_atomic_check(struct intel_atomic_state *state,
681131d3b1aSVille Syrjälä struct intel_plane *plane)
6824f25720bSMaarten Lankhorst {
6838246d9c7SVille Syrjälä struct drm_i915_private *i915 = to_i915(state->base.dev);
6844f25720bSMaarten Lankhorst struct intel_plane_state *new_plane_state =
685131d3b1aSVille Syrjälä intel_atomic_get_new_plane_state(state, plane);
6864f25720bSMaarten Lankhorst const struct intel_plane_state *old_plane_state =
6874f25720bSMaarten Lankhorst intel_atomic_get_old_plane_state(state, plane);
6888246d9c7SVille Syrjälä const struct intel_plane_state *new_master_plane_state;
6897794b6deSJani Nikula struct intel_crtc *crtc = intel_crtc_for_pipe(i915, plane->pipe);
6908246d9c7SVille Syrjälä const struct intel_crtc_state *old_crtc_state =
6918246d9c7SVille Syrjälä intel_atomic_get_old_crtc_state(state, crtc);
6928246d9c7SVille Syrjälä struct intel_crtc_state *new_crtc_state =
6938246d9c7SVille Syrjälä intel_atomic_get_new_crtc_state(state, crtc);
6944f25720bSMaarten Lankhorst
695df529053SVille Syrjälä if (new_crtc_state && intel_crtc_is_bigjoiner_slave(new_crtc_state)) {
696a6e7a006SVille Syrjälä struct intel_crtc *master_crtc =
697a6e7a006SVille Syrjälä intel_master_crtc(new_crtc_state);
6988246d9c7SVille Syrjälä struct intel_plane *master_plane =
699a6e7a006SVille Syrjälä intel_crtc_get_plane(master_crtc, plane->id);
7008246d9c7SVille Syrjälä
7018246d9c7SVille Syrjälä new_master_plane_state =
7028246d9c7SVille Syrjälä intel_atomic_get_new_plane_state(state, master_plane);
7038246d9c7SVille Syrjälä } else {
7048246d9c7SVille Syrjälä new_master_plane_state = new_plane_state;
7058246d9c7SVille Syrjälä }
7068246d9c7SVille Syrjälä
7078246d9c7SVille Syrjälä intel_plane_copy_uapi_to_hw_state(new_plane_state,
7088246d9c7SVille Syrjälä new_master_plane_state,
7098246d9c7SVille Syrjälä crtc);
7108246d9c7SVille Syrjälä
711f90a85e7SMaarten Lankhorst new_plane_state->uapi.visible = false;
7128246d9c7SVille Syrjälä if (!new_crtc_state)
713df0566a6SJani Nikula return 0;
714df0566a6SJani Nikula
7154f25720bSMaarten Lankhorst return intel_plane_atomic_check_with_state(old_crtc_state,
7164f25720bSMaarten Lankhorst new_crtc_state,
7174f25720bSMaarten Lankhorst old_plane_state,
7184f25720bSMaarten Lankhorst new_plane_state);
719df0566a6SJani Nikula }
720df0566a6SJani Nikula
721df0566a6SJani Nikula static struct intel_plane *
skl_next_plane_to_commit(struct intel_atomic_state * state,struct intel_crtc * crtc,struct skl_ddb_entry ddb[I915_MAX_PLANES],struct skl_ddb_entry ddb_y[I915_MAX_PLANES],unsigned int * update_mask)722df0566a6SJani Nikula skl_next_plane_to_commit(struct intel_atomic_state *state,
723df0566a6SJani Nikula struct intel_crtc *crtc,
7247d456172SVille Syrjälä struct skl_ddb_entry ddb[I915_MAX_PLANES],
7257d456172SVille Syrjälä struct skl_ddb_entry ddb_y[I915_MAX_PLANES],
726df0566a6SJani Nikula unsigned int *update_mask)
727df0566a6SJani Nikula {
728df0566a6SJani Nikula struct intel_crtc_state *crtc_state =
729df0566a6SJani Nikula intel_atomic_get_new_crtc_state(state, crtc);
730ace87304SJani Nikula struct intel_plane_state __maybe_unused *plane_state;
731df0566a6SJani Nikula struct intel_plane *plane;
732df0566a6SJani Nikula int i;
733df0566a6SJani Nikula
734df0566a6SJani Nikula if (*update_mask == 0)
735df0566a6SJani Nikula return NULL;
736df0566a6SJani Nikula
737df0566a6SJani Nikula for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
738df0566a6SJani Nikula enum plane_id plane_id = plane->id;
739df0566a6SJani Nikula
740df0566a6SJani Nikula if (crtc->pipe != plane->pipe ||
741df0566a6SJani Nikula !(*update_mask & BIT(plane_id)))
742df0566a6SJani Nikula continue;
743df0566a6SJani Nikula
7447d456172SVille Syrjälä if (skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb[plane_id],
7457d456172SVille Syrjälä ddb, I915_MAX_PLANES, plane_id) ||
7467d456172SVille Syrjälä skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb_y[plane_id],
7477d456172SVille Syrjälä ddb_y, I915_MAX_PLANES, plane_id))
748df0566a6SJani Nikula continue;
749df0566a6SJani Nikula
750df0566a6SJani Nikula *update_mask &= ~BIT(plane_id);
7517d456172SVille Syrjälä ddb[plane_id] = crtc_state->wm.skl.plane_ddb[plane_id];
7527d456172SVille Syrjälä ddb_y[plane_id] = crtc_state->wm.skl.plane_ddb_y[plane_id];
753df0566a6SJani Nikula
754df0566a6SJani Nikula return plane;
755df0566a6SJani Nikula }
756df0566a6SJani Nikula
757df0566a6SJani Nikula /* should never happen */
7581e6850eeSPankaj Bharadiya drm_WARN_ON(state->base.dev, 1);
759df0566a6SJani Nikula
760df0566a6SJani Nikula return NULL;
761df0566a6SJani Nikula }
762df0566a6SJani Nikula
intel_plane_update_noarm(struct intel_plane * plane,const struct intel_crtc_state * crtc_state,const struct intel_plane_state * plane_state)7638ac80733SVille Syrjälä void intel_plane_update_noarm(struct intel_plane *plane,
764df0566a6SJani Nikula const struct intel_crtc_state *crtc_state,
765df0566a6SJani Nikula const struct intel_plane_state *plane_state)
766df0566a6SJani Nikula {
7672225f3c6SMaarten Lankhorst struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
768df0566a6SJani Nikula
769b5423d1fSVille Syrjälä trace_intel_plane_update_noarm(plane, crtc);
7708ac80733SVille Syrjälä
7718ac80733SVille Syrjälä if (plane->update_noarm)
7728ac80733SVille Syrjälä plane->update_noarm(plane, crtc_state, plane_state);
7738ac80733SVille Syrjälä }
7748ac80733SVille Syrjälä
intel_plane_update_arm(struct intel_plane * plane,const struct intel_crtc_state * crtc_state,const struct intel_plane_state * plane_state)7758ac80733SVille Syrjälä void intel_plane_update_arm(struct intel_plane *plane,
7768ac80733SVille Syrjälä const struct intel_crtc_state *crtc_state,
7778ac80733SVille Syrjälä const struct intel_plane_state *plane_state)
7788ac80733SVille Syrjälä {
7798ac80733SVille Syrjälä struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7808ac80733SVille Syrjälä
781b5423d1fSVille Syrjälä trace_intel_plane_update_arm(plane, crtc);
782b039193dSKarthik B S
7835c8107dcSVille Syrjälä if (crtc_state->do_async_flip && plane->async_flip)
78468fd1faaSVille Syrjälä plane->async_flip(plane, crtc_state, plane_state, true);
785b039193dSKarthik B S else
7868ac80733SVille Syrjälä plane->update_arm(plane, crtc_state, plane_state);
787df0566a6SJani Nikula }
788df0566a6SJani Nikula
intel_plane_disable_arm(struct intel_plane * plane,const struct intel_crtc_state * crtc_state)7898ac80733SVille Syrjälä void intel_plane_disable_arm(struct intel_plane *plane,
790df0566a6SJani Nikula const struct intel_crtc_state *crtc_state)
791df0566a6SJani Nikula {
7922225f3c6SMaarten Lankhorst struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
793df0566a6SJani Nikula
794b5423d1fSVille Syrjälä trace_intel_plane_disable_arm(plane, crtc);
7958ac80733SVille Syrjälä plane->disable_arm(plane, crtc_state);
796df0566a6SJani Nikula }
797df0566a6SJani Nikula
intel_crtc_planes_update_noarm(struct intel_atomic_state * state,struct intel_crtc * crtc)7989b43698aSVille Syrjälä void intel_crtc_planes_update_noarm(struct intel_atomic_state *state,
7998ac80733SVille Syrjälä struct intel_crtc *crtc)
8008ac80733SVille Syrjälä {
8018ac80733SVille Syrjälä struct intel_crtc_state *new_crtc_state =
8028ac80733SVille Syrjälä intel_atomic_get_new_crtc_state(state, crtc);
8038ac80733SVille Syrjälä u32 update_mask = new_crtc_state->update_planes;
8048ac80733SVille Syrjälä struct intel_plane_state *new_plane_state;
8058ac80733SVille Syrjälä struct intel_plane *plane;
8068ac80733SVille Syrjälä int i;
8078ac80733SVille Syrjälä
8085c8107dcSVille Syrjälä if (new_crtc_state->do_async_flip)
8098ac80733SVille Syrjälä return;
8108ac80733SVille Syrjälä
8118ac80733SVille Syrjälä /*
8128ac80733SVille Syrjälä * Since we only write non-arming registers here,
8138ac80733SVille Syrjälä * the order does not matter even for skl+.
8148ac80733SVille Syrjälä */
8158ac80733SVille Syrjälä for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) {
8168ac80733SVille Syrjälä if (crtc->pipe != plane->pipe ||
8178ac80733SVille Syrjälä !(update_mask & BIT(plane->id)))
8188ac80733SVille Syrjälä continue;
8198ac80733SVille Syrjälä
8208ac80733SVille Syrjälä /* TODO: for mailbox updates this should be skipped */
8218ac80733SVille Syrjälä if (new_plane_state->uapi.visible ||
8228ac80733SVille Syrjälä new_plane_state->planar_slave)
8238ac80733SVille Syrjälä intel_plane_update_noarm(plane, new_crtc_state, new_plane_state);
8248ac80733SVille Syrjälä }
8258ac80733SVille Syrjälä }
8268ac80733SVille Syrjälä
skl_crtc_planes_update_arm(struct intel_atomic_state * state,struct intel_crtc * crtc)8279b43698aSVille Syrjälä static void skl_crtc_planes_update_arm(struct intel_atomic_state *state,
828df0566a6SJani Nikula struct intel_crtc *crtc)
829df0566a6SJani Nikula {
830df0566a6SJani Nikula struct intel_crtc_state *old_crtc_state =
831df0566a6SJani Nikula intel_atomic_get_old_crtc_state(state, crtc);
832df0566a6SJani Nikula struct intel_crtc_state *new_crtc_state =
833df0566a6SJani Nikula intel_atomic_get_new_crtc_state(state, crtc);
8347d456172SVille Syrjälä struct skl_ddb_entry ddb[I915_MAX_PLANES];
8357d456172SVille Syrjälä struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
836df0566a6SJani Nikula u32 update_mask = new_crtc_state->update_planes;
837df0566a6SJani Nikula struct intel_plane *plane;
838df0566a6SJani Nikula
8397d456172SVille Syrjälä memcpy(ddb, old_crtc_state->wm.skl.plane_ddb,
8407d456172SVille Syrjälä sizeof(old_crtc_state->wm.skl.plane_ddb));
8417d456172SVille Syrjälä memcpy(ddb_y, old_crtc_state->wm.skl.plane_ddb_y,
842df0566a6SJani Nikula sizeof(old_crtc_state->wm.skl.plane_ddb_y));
843df0566a6SJani Nikula
8447d456172SVille Syrjälä while ((plane = skl_next_plane_to_commit(state, crtc, ddb, ddb_y, &update_mask))) {
845df0566a6SJani Nikula struct intel_plane_state *new_plane_state =
846df0566a6SJani Nikula intel_atomic_get_new_plane_state(state, plane);
847df0566a6SJani Nikula
8488ac80733SVille Syrjälä /*
8498ac80733SVille Syrjälä * TODO: for mailbox updates intel_plane_update_noarm()
8508ac80733SVille Syrjälä * would have to be called here as well.
8518ac80733SVille Syrjälä */
8521f594b20SMaarten Lankhorst if (new_plane_state->uapi.visible ||
8538ac80733SVille Syrjälä new_plane_state->planar_slave)
8548ac80733SVille Syrjälä intel_plane_update_arm(plane, new_crtc_state, new_plane_state);
8558ac80733SVille Syrjälä else
8568ac80733SVille Syrjälä intel_plane_disable_arm(plane, new_crtc_state);
857df0566a6SJani Nikula }
858df0566a6SJani Nikula }
859df0566a6SJani Nikula
i9xx_crtc_planes_update_arm(struct intel_atomic_state * state,struct intel_crtc * crtc)8609b43698aSVille Syrjälä static void i9xx_crtc_planes_update_arm(struct intel_atomic_state *state,
861df0566a6SJani Nikula struct intel_crtc *crtc)
862df0566a6SJani Nikula {
863df0566a6SJani Nikula struct intel_crtc_state *new_crtc_state =
864df0566a6SJani Nikula intel_atomic_get_new_crtc_state(state, crtc);
865df0566a6SJani Nikula u32 update_mask = new_crtc_state->update_planes;
866df0566a6SJani Nikula struct intel_plane_state *new_plane_state;
867df0566a6SJani Nikula struct intel_plane *plane;
868df0566a6SJani Nikula int i;
869df0566a6SJani Nikula
870df0566a6SJani Nikula for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) {
871df0566a6SJani Nikula if (crtc->pipe != plane->pipe ||
872df0566a6SJani Nikula !(update_mask & BIT(plane->id)))
873df0566a6SJani Nikula continue;
874df0566a6SJani Nikula
8758ac80733SVille Syrjälä /*
8768ac80733SVille Syrjälä * TODO: for mailbox updates intel_plane_update_noarm()
8778ac80733SVille Syrjälä * would have to be called here as well.
8788ac80733SVille Syrjälä */
879f90a85e7SMaarten Lankhorst if (new_plane_state->uapi.visible)
8808ac80733SVille Syrjälä intel_plane_update_arm(plane, new_crtc_state, new_plane_state);
881df0566a6SJani Nikula else
8828ac80733SVille Syrjälä intel_plane_disable_arm(plane, new_crtc_state);
883df0566a6SJani Nikula }
884df0566a6SJani Nikula }
885df0566a6SJani Nikula
intel_crtc_planes_update_arm(struct intel_atomic_state * state,struct intel_crtc * crtc)8869b43698aSVille Syrjälä void intel_crtc_planes_update_arm(struct intel_atomic_state *state,
8879b43698aSVille Syrjälä struct intel_crtc *crtc)
8889b43698aSVille Syrjälä {
8899b43698aSVille Syrjälä struct drm_i915_private *i915 = to_i915(state->base.dev);
8909b43698aSVille Syrjälä
8919b43698aSVille Syrjälä if (DISPLAY_VER(i915) >= 9)
8929b43698aSVille Syrjälä skl_crtc_planes_update_arm(state, crtc);
8939b43698aSVille Syrjälä else
8949b43698aSVille Syrjälä i9xx_crtc_planes_update_arm(state, crtc);
8959b43698aSVille Syrjälä }
8969b43698aSVille Syrjälä
intel_atomic_plane_check_clipping(struct intel_plane_state * plane_state,struct intel_crtc_state * crtc_state,int min_scale,int max_scale,bool can_position)8979f05a7c0SMaarten Lankhorst int intel_atomic_plane_check_clipping(struct intel_plane_state *plane_state,
8989f05a7c0SMaarten Lankhorst struct intel_crtc_state *crtc_state,
8999f05a7c0SMaarten Lankhorst int min_scale, int max_scale,
9009f05a7c0SMaarten Lankhorst bool can_position)
9019f05a7c0SMaarten Lankhorst {
9025acbdcd1SJani Nikula struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
9039f05a7c0SMaarten Lankhorst struct drm_framebuffer *fb = plane_state->hw.fb;
9049f05a7c0SMaarten Lankhorst struct drm_rect *src = &plane_state->uapi.src;
9059f05a7c0SMaarten Lankhorst struct drm_rect *dst = &plane_state->uapi.dst;
90626111a16SVille Syrjälä const struct drm_rect *clip = &crtc_state->pipe_src;
9079f05a7c0SMaarten Lankhorst unsigned int rotation = plane_state->hw.rotation;
9089f05a7c0SMaarten Lankhorst int hscale, vscale;
9099f05a7c0SMaarten Lankhorst
9109f05a7c0SMaarten Lankhorst if (!fb) {
9119f05a7c0SMaarten Lankhorst plane_state->uapi.visible = false;
9129f05a7c0SMaarten Lankhorst return 0;
9139f05a7c0SMaarten Lankhorst }
9149f05a7c0SMaarten Lankhorst
9159f05a7c0SMaarten Lankhorst drm_rect_rotate(src, fb->width << 16, fb->height << 16, rotation);
9169f05a7c0SMaarten Lankhorst
9179f05a7c0SMaarten Lankhorst /* Check scaling */
9189f05a7c0SMaarten Lankhorst hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale);
9199f05a7c0SMaarten Lankhorst vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale);
9209f05a7c0SMaarten Lankhorst if (hscale < 0 || vscale < 0) {
9215acbdcd1SJani Nikula drm_dbg_kms(&i915->drm, "Invalid scaling of plane\n");
9229f05a7c0SMaarten Lankhorst drm_rect_debug_print("src: ", src, true);
9239f05a7c0SMaarten Lankhorst drm_rect_debug_print("dst: ", dst, false);
9249f05a7c0SMaarten Lankhorst return -ERANGE;
9259f05a7c0SMaarten Lankhorst }
9269f05a7c0SMaarten Lankhorst
9279f05a7c0SMaarten Lankhorst /*
9289f05a7c0SMaarten Lankhorst * FIXME: This might need further adjustment for seamless scaling
9299f05a7c0SMaarten Lankhorst * with phase information, for the 2p2 and 2p1 scenarios.
9309f05a7c0SMaarten Lankhorst */
93126111a16SVille Syrjälä plane_state->uapi.visible = drm_rect_clip_scaled(src, dst, clip);
9329f05a7c0SMaarten Lankhorst
9339f05a7c0SMaarten Lankhorst drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16, rotation);
9349f05a7c0SMaarten Lankhorst
9359f05a7c0SMaarten Lankhorst if (!can_position && plane_state->uapi.visible &&
93626111a16SVille Syrjälä !drm_rect_equals(dst, clip)) {
9375acbdcd1SJani Nikula drm_dbg_kms(&i915->drm, "Plane must cover entire CRTC\n");
9389f05a7c0SMaarten Lankhorst drm_rect_debug_print("dst: ", dst, false);
93926111a16SVille Syrjälä drm_rect_debug_print("clip: ", clip, false);
9409f05a7c0SMaarten Lankhorst return -EINVAL;
9419f05a7c0SMaarten Lankhorst }
9429f05a7c0SMaarten Lankhorst
9438d8b2dd3SVille Syrjälä /* final plane coordinates will be relative to the plane's pipe */
9448d8b2dd3SVille Syrjälä drm_rect_translate(dst, -clip->x1, -clip->y1);
9458d8b2dd3SVille Syrjälä
9469f05a7c0SMaarten Lankhorst return 0;
9479f05a7c0SMaarten Lankhorst }
9489f05a7c0SMaarten Lankhorst
intel_plane_check_src_coordinates(struct intel_plane_state * plane_state)9490ec2a5b2SVille Syrjälä int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state)
9500ec2a5b2SVille Syrjälä {
9510ec2a5b2SVille Syrjälä struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
9520ec2a5b2SVille Syrjälä const struct drm_framebuffer *fb = plane_state->hw.fb;
9530ec2a5b2SVille Syrjälä struct drm_rect *src = &plane_state->uapi.src;
9540ec2a5b2SVille Syrjälä u32 src_x, src_y, src_w, src_h, hsub, vsub;
9550ec2a5b2SVille Syrjälä bool rotated = drm_rotation_90_or_270(plane_state->hw.rotation);
9560ec2a5b2SVille Syrjälä
9570ec2a5b2SVille Syrjälä /*
9580ec2a5b2SVille Syrjälä * FIXME hsub/vsub vs. block size is a mess. Pre-tgl CCS
9590ec2a5b2SVille Syrjälä * abuses hsub/vsub so we can't use them here. But as they
9600ec2a5b2SVille Syrjälä * are limited to 32bpp RGB formats we don't actually need
9610ec2a5b2SVille Syrjälä * to check anything.
9620ec2a5b2SVille Syrjälä */
9630ec2a5b2SVille Syrjälä if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
9640ec2a5b2SVille Syrjälä fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS)
9650ec2a5b2SVille Syrjälä return 0;
9660ec2a5b2SVille Syrjälä
9670ec2a5b2SVille Syrjälä /*
9680ec2a5b2SVille Syrjälä * Hardware doesn't handle subpixel coordinates.
9690ec2a5b2SVille Syrjälä * Adjust to (macro)pixel boundary, but be careful not to
9700ec2a5b2SVille Syrjälä * increase the source viewport size, because that could
9710ec2a5b2SVille Syrjälä * push the downscaling factor out of bounds.
9720ec2a5b2SVille Syrjälä */
9730ec2a5b2SVille Syrjälä src_x = src->x1 >> 16;
9740ec2a5b2SVille Syrjälä src_w = drm_rect_width(src) >> 16;
9750ec2a5b2SVille Syrjälä src_y = src->y1 >> 16;
9760ec2a5b2SVille Syrjälä src_h = drm_rect_height(src) >> 16;
9770ec2a5b2SVille Syrjälä
9780ec2a5b2SVille Syrjälä drm_rect_init(src, src_x << 16, src_y << 16,
9790ec2a5b2SVille Syrjälä src_w << 16, src_h << 16);
9800ec2a5b2SVille Syrjälä
9810ec2a5b2SVille Syrjälä if (fb->format->format == DRM_FORMAT_RGB565 && rotated) {
9820ec2a5b2SVille Syrjälä hsub = 2;
9830ec2a5b2SVille Syrjälä vsub = 2;
9840ec2a5b2SVille Syrjälä } else {
9850ec2a5b2SVille Syrjälä hsub = fb->format->hsub;
9860ec2a5b2SVille Syrjälä vsub = fb->format->vsub;
9870ec2a5b2SVille Syrjälä }
9880ec2a5b2SVille Syrjälä
9890ec2a5b2SVille Syrjälä if (rotated)
9900ec2a5b2SVille Syrjälä hsub = vsub = max(hsub, vsub);
9910ec2a5b2SVille Syrjälä
9920ec2a5b2SVille Syrjälä if (src_x % hsub || src_w % hsub) {
9930ec2a5b2SVille Syrjälä drm_dbg_kms(&i915->drm, "src x/w (%u, %u) must be a multiple of %u (rotated: %s)\n",
9940ec2a5b2SVille Syrjälä src_x, src_w, hsub, str_yes_no(rotated));
9950ec2a5b2SVille Syrjälä return -EINVAL;
9960ec2a5b2SVille Syrjälä }
9970ec2a5b2SVille Syrjälä
9980ec2a5b2SVille Syrjälä if (src_y % vsub || src_h % vsub) {
9990ec2a5b2SVille Syrjälä drm_dbg_kms(&i915->drm, "src y/h (%u, %u) must be a multiple of %u (rotated: %s)\n",
10000ec2a5b2SVille Syrjälä src_y, src_h, vsub, str_yes_no(rotated));
10010ec2a5b2SVille Syrjälä return -EINVAL;
10020ec2a5b2SVille Syrjälä }
10030ec2a5b2SVille Syrjälä
10040ec2a5b2SVille Syrjälä return 0;
10050ec2a5b2SVille Syrjälä }
10060ec2a5b2SVille Syrjälä
100774a75dc9SDave Airlie /**
100874a75dc9SDave Airlie * intel_prepare_plane_fb - Prepare fb for usage on plane
100974a75dc9SDave Airlie * @_plane: drm plane to prepare for
101074a75dc9SDave Airlie * @_new_plane_state: the plane state being prepared
101174a75dc9SDave Airlie *
101274a75dc9SDave Airlie * Prepares a framebuffer for usage on a display plane. Generally this
101374a75dc9SDave Airlie * involves pinning the underlying object and updating the frontbuffer tracking
101474a75dc9SDave Airlie * bits. Some older platforms need special physical address handling for
101574a75dc9SDave Airlie * cursor planes.
101674a75dc9SDave Airlie *
101774a75dc9SDave Airlie * Returns 0 on success, negative error code on failure.
101874a75dc9SDave Airlie */
101974a75dc9SDave Airlie static int
intel_prepare_plane_fb(struct drm_plane * _plane,struct drm_plane_state * _new_plane_state)102074a75dc9SDave Airlie intel_prepare_plane_fb(struct drm_plane *_plane,
102174a75dc9SDave Airlie struct drm_plane_state *_new_plane_state)
102274a75dc9SDave Airlie {
102374a75dc9SDave Airlie struct i915_sched_attr attr = { .priority = I915_PRIORITY_DISPLAY };
102474a75dc9SDave Airlie struct intel_plane *plane = to_intel_plane(_plane);
102574a75dc9SDave Airlie struct intel_plane_state *new_plane_state =
102674a75dc9SDave Airlie to_intel_plane_state(_new_plane_state);
102774a75dc9SDave Airlie struct intel_atomic_state *state =
102874a75dc9SDave Airlie to_intel_atomic_state(new_plane_state->uapi.state);
102974a75dc9SDave Airlie struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
103074a75dc9SDave Airlie const struct intel_plane_state *old_plane_state =
103174a75dc9SDave Airlie intel_atomic_get_old_plane_state(state, plane);
103274a75dc9SDave Airlie struct drm_i915_gem_object *obj = intel_fb_obj(new_plane_state->hw.fb);
103374a75dc9SDave Airlie struct drm_i915_gem_object *old_obj = intel_fb_obj(old_plane_state->hw.fb);
103474a75dc9SDave Airlie int ret;
103574a75dc9SDave Airlie
103674a75dc9SDave Airlie if (old_obj) {
10371d5b09f8SStanislav Lisovskiy const struct intel_crtc_state *new_crtc_state =
103874a75dc9SDave Airlie intel_atomic_get_new_crtc_state(state,
103974a75dc9SDave Airlie to_intel_crtc(old_plane_state->hw.crtc));
104074a75dc9SDave Airlie
104174a75dc9SDave Airlie /* Big Hammer, we also need to ensure that any pending
104274a75dc9SDave Airlie * MI_WAIT_FOR_EVENT inside a user batch buffer on the
104374a75dc9SDave Airlie * current scanout is retired before unpinning the old
104474a75dc9SDave Airlie * framebuffer. Note that we rely on userspace rendering
104574a75dc9SDave Airlie * into the buffer attached to the pipe they are waiting
104674a75dc9SDave Airlie * on. If not, userspace generates a GPU hang with IPEHR
104774a75dc9SDave Airlie * point to the MI_WAIT_FOR_EVENT.
104874a75dc9SDave Airlie *
104974a75dc9SDave Airlie * This should only fail upon a hung GPU, in which case we
105074a75dc9SDave Airlie * can safely continue.
105174a75dc9SDave Airlie */
10521d5b09f8SStanislav Lisovskiy if (new_crtc_state && intel_crtc_needs_modeset(new_crtc_state)) {
105374a75dc9SDave Airlie ret = i915_sw_fence_await_reservation(&state->commit_ready,
10548146d588SNiranjana Vishwanathapura old_obj->base.resv,
105574a75dc9SDave Airlie false, 0,
105674a75dc9SDave Airlie GFP_KERNEL);
105774a75dc9SDave Airlie if (ret < 0)
105874a75dc9SDave Airlie return ret;
105974a75dc9SDave Airlie }
106074a75dc9SDave Airlie }
106174a75dc9SDave Airlie
106274a75dc9SDave Airlie if (new_plane_state->uapi.fence) { /* explicit fencing */
106374a75dc9SDave Airlie i915_gem_fence_wait_priority(new_plane_state->uapi.fence,
106474a75dc9SDave Airlie &attr);
106574a75dc9SDave Airlie ret = i915_sw_fence_await_dma_fence(&state->commit_ready,
106674a75dc9SDave Airlie new_plane_state->uapi.fence,
106774a75dc9SDave Airlie i915_fence_timeout(dev_priv),
106874a75dc9SDave Airlie GFP_KERNEL);
106974a75dc9SDave Airlie if (ret < 0)
107074a75dc9SDave Airlie return ret;
107174a75dc9SDave Airlie }
107274a75dc9SDave Airlie
107374a75dc9SDave Airlie if (!obj)
107474a75dc9SDave Airlie return 0;
107574a75dc9SDave Airlie
107674a75dc9SDave Airlie
107774a75dc9SDave Airlie ret = intel_plane_pin_fb(new_plane_state);
107874a75dc9SDave Airlie if (ret)
107974a75dc9SDave Airlie return ret;
108074a75dc9SDave Airlie
108174a75dc9SDave Airlie i915_gem_object_wait_priority(obj, 0, &attr);
108274a75dc9SDave Airlie
108374a75dc9SDave Airlie if (!new_plane_state->uapi.fence) { /* implicit fencing */
10845e9ddbdcSChristian König struct dma_resv_iter cursor;
108574a75dc9SDave Airlie struct dma_fence *fence;
108674a75dc9SDave Airlie
108774a75dc9SDave Airlie ret = i915_sw_fence_await_reservation(&state->commit_ready,
10888146d588SNiranjana Vishwanathapura obj->base.resv, false,
108974a75dc9SDave Airlie i915_fence_timeout(dev_priv),
109074a75dc9SDave Airlie GFP_KERNEL);
109174a75dc9SDave Airlie if (ret < 0)
109274a75dc9SDave Airlie goto unpin_fb;
109374a75dc9SDave Airlie
10947bc80a54SChristian König dma_resv_iter_begin(&cursor, obj->base.resv,
10957bc80a54SChristian König DMA_RESV_USAGE_WRITE);
10965e9ddbdcSChristian König dma_resv_for_each_fence_unlocked(&cursor, fence) {
10976dbbff25SJani Nikula intel_display_rps_boost_after_vblank(new_plane_state->hw.crtc,
109874a75dc9SDave Airlie fence);
109974a75dc9SDave Airlie }
11005e9ddbdcSChristian König dma_resv_iter_end(&cursor);
110174a75dc9SDave Airlie } else {
11026dbbff25SJani Nikula intel_display_rps_boost_after_vblank(new_plane_state->hw.crtc,
110374a75dc9SDave Airlie new_plane_state->uapi.fence);
110474a75dc9SDave Airlie }
110574a75dc9SDave Airlie
110674a75dc9SDave Airlie /*
110774a75dc9SDave Airlie * We declare pageflips to be interactive and so merit a small bias
110874a75dc9SDave Airlie * towards upclocking to deliver the frame on time. By only changing
110974a75dc9SDave Airlie * the RPS thresholds to sample more regularly and aim for higher
111074a75dc9SDave Airlie * clocks we can hopefully deliver low power workloads (like kodi)
111174a75dc9SDave Airlie * that are not quite steady state without resorting to forcing
111274a75dc9SDave Airlie * maximum clocks following a vblank miss (see do_rps_boost()).
111374a75dc9SDave Airlie */
11146dbbff25SJani Nikula intel_display_rps_mark_interactive(dev_priv, state, true);
111574a75dc9SDave Airlie
111674a75dc9SDave Airlie return 0;
111774a75dc9SDave Airlie
111874a75dc9SDave Airlie unpin_fb:
111974a75dc9SDave Airlie intel_plane_unpin_fb(new_plane_state);
112074a75dc9SDave Airlie
112174a75dc9SDave Airlie return ret;
112274a75dc9SDave Airlie }
112374a75dc9SDave Airlie
112474a75dc9SDave Airlie /**
112574a75dc9SDave Airlie * intel_cleanup_plane_fb - Cleans up an fb after plane use
112674a75dc9SDave Airlie * @plane: drm plane to clean up for
112774a75dc9SDave Airlie * @_old_plane_state: the state from the previous modeset
112874a75dc9SDave Airlie *
112974a75dc9SDave Airlie * Cleans up a framebuffer that has just been removed from a plane.
113074a75dc9SDave Airlie */
113174a75dc9SDave Airlie static void
intel_cleanup_plane_fb(struct drm_plane * plane,struct drm_plane_state * _old_plane_state)113274a75dc9SDave Airlie intel_cleanup_plane_fb(struct drm_plane *plane,
113374a75dc9SDave Airlie struct drm_plane_state *_old_plane_state)
113474a75dc9SDave Airlie {
113574a75dc9SDave Airlie struct intel_plane_state *old_plane_state =
113674a75dc9SDave Airlie to_intel_plane_state(_old_plane_state);
113774a75dc9SDave Airlie struct intel_atomic_state *state =
113874a75dc9SDave Airlie to_intel_atomic_state(old_plane_state->uapi.state);
113974a75dc9SDave Airlie struct drm_i915_private *dev_priv = to_i915(plane->dev);
114074a75dc9SDave Airlie struct drm_i915_gem_object *obj = intel_fb_obj(old_plane_state->hw.fb);
114174a75dc9SDave Airlie
114274a75dc9SDave Airlie if (!obj)
114374a75dc9SDave Airlie return;
114474a75dc9SDave Airlie
11456dbbff25SJani Nikula intel_display_rps_mark_interactive(dev_priv, state, false);
114674a75dc9SDave Airlie
114774a75dc9SDave Airlie /* Should only be called after a successful intel_prepare_plane_fb()! */
114874a75dc9SDave Airlie intel_plane_unpin_fb(old_plane_state);
114974a75dc9SDave Airlie }
115074a75dc9SDave Airlie
1151d372ba42SJani Nikula static const struct drm_plane_helper_funcs intel_plane_helper_funcs = {
1152df0566a6SJani Nikula .prepare_fb = intel_prepare_plane_fb,
1153df0566a6SJani Nikula .cleanup_fb = intel_cleanup_plane_fb,
1154df0566a6SJani Nikula };
1155d372ba42SJani Nikula
intel_plane_helper_add(struct intel_plane * plane)1156d372ba42SJani Nikula void intel_plane_helper_add(struct intel_plane *plane)
1157d372ba42SJani Nikula {
1158d372ba42SJani Nikula drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs);
1159d372ba42SJani Nikula }
1160