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/openbmc/linux/Documentation/devicetree/bindings/arm/
H A Darm,cci-400.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,cci-400.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM CCI Cache Coherent Interconnect
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
13 ARM multi-cluster systems maintain intra-cluster coherency through a cache
14 coherent interconnect (CCI) that is capable of monitoring bus transactions
24 pattern: "^cci(@[0-9a-f]+)?$"
28 - arm,cci-400
[all …]
/openbmc/linux/drivers/bus/
H A Darm-cci.c2 * CCI cache coherent interconnect driver
17 #include <linux/arm-cci.h>
49 {.compatible = "arm,cci-400", .data = CCI400_PORTS_DATA },
52 { .compatible = "arm,cci-500", },
53 { .compatible = "arm,cci-550", },
59 OF_DEV_AUXDATA("arm,cci-400-pmu", 0, NULL, &cci_ctrl_base),
60 OF_DEV_AUXDATA("arm,cci-400-pmu,r0", 0, NULL, &cci_ctrl_base),
61 OF_DEV_AUXDATA("arm,cci-400-pmu,r1", 0, NULL, &cci_ctrl_base),
62 OF_DEV_AUXDATA("arm,cci-500-pmu,r0", 0, NULL, &cci_ctrl_base),
63 OF_DEV_AUXDATA("arm,cci-550-pmu,r0", 0, NULL, &cci_ctrl_base),
[all …]
/openbmc/linux/drivers/perf/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
10 tristate "ARM CCI PMU driver"
14 Support for PMU events monitoring on the ARM CCI (Cache Coherent
17 If compiled as a module, it will be called arm-cci.
20 bool "support CCI-400"
25 CCI-400 provides 4 independent event counters counting events related
29 bool "support CCI-500/CCI-550"
33 CCI-500/CCI-550 both provide 8 independent event counters, which can
35 internal events to the CCI.
45 tristate "Arm CMN-600 PMU support"
[all …]
H A Darm-cci.c1 // SPDX-License-Identifier: GPL-2.0
2 // CCI Cache Coherent Interconnect PMU driver
3 // Copyright (C) 2013-2018 Arm Ltd.
6 #include <linux/arm-cci.h>
16 #define DRIVER_NAME "ARM-CCI PMU"
35 #define CCI_PMU_CNTR_SIZE(model) ((model)->cntr_size)
37 #define CCI_PMU_CNTR_MASK ((1ULL << 32) - 1)
38 #define CCI_PMU_CNTR_LAST(cci_pmu) (cci_pmu->num_cntrs - 1)
41 ((model)->num_hw_cntrs + (model)->fixed_hw_cntrs)
77 * @fixed_hw_cntrs - Number of fixed event counters
[all …]
/openbmc/linux/arch/arm/boot/dts/mediatek/
H A Dmt7629.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/mt7629-clk.h>
11 #include <dt-bindings/power/mt7622-power.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/reset/mt7629-resets.h>
18 interrupt-parent = <&sysirq>;
19 #address-cells = <1>;
[all …]
/openbmc/linux/arch/arm/boot/dts/samsung/
H A Dexynos5260.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/exynos5260-clk.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <1>;
17 #size-cells = <1>;
34 #address-cells = <1>;
35 #size-cells = <0>;
37 cpu-map {
[all …]
/openbmc/linux/arch/arm64/boot/dts/mediatek/
H A Dmt6795.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/mediatek,mt6795-clk.h>
10 #include <dt-bindings/gce/mediatek,mt6795-gce.h>
11 #include <dt-bindings/memory/mt6795-larb-port.h>
12 #include <dt-bindings/pinctrl/mt6795-pinfunc.h>
13 #include <dt-bindings/power/mt6795-power.h>
14 #include <dt-bindings/reset/mediatek,mt6795-resets.h>
18 interrupt-parent = <&sysirq>;
[all …]
H A Dmt7622.dtsi6 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/clock/mt7622-clk.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/power/mt7622-power.h>
14 #include <dt-bindings/reset/mt7622-reset.h>
15 #include <dt-bindings/thermal/thermal.h>
19 interrupt-parent = <&sysirq>;
20 #address-cells = <2>;
[all …]
/openbmc/u-boot/board/armltd/vexpress/
H A Dvexpress_tc2.c1 // SPDX-License-Identifier: GPL-2.0+
11 #include <asm/u-boot.h>
27 * bit 12 = Use per-cpu mailboxes for power management in armv7_boot_nonsec_default()
28 * bit 13 = Power down the non-boot cluster in armv7_boot_nonsec_default()
30 * It is only when both of these are false that U-Boot's current in armv7_boot_nonsec_default()
43 const char *cci_compatible = "arm,cci-400-ctrl-if"; in ft_board_setup()
51 /* Booting in nonsec mode, disable CCI access */ in ft_board_setup()
58 /* delete cci-control-port in each cpu node */ in ft_board_setup()
61 fdt_delprop(fdt, tmp, "cci-control-port"); in ft_board_setup()
63 /* disable all ace cci slave ports */ in ft_board_setup()
[all …]
/openbmc/linux/arch/arm/boot/dts/arm/
H A Dvexpress-v2p-ca15_a7.dts1 // SPDX-License-Identifier: GPL-2.0
6 * Cortex-A15_A7 MPCore (V2P-CA15_A7)
8 * HBI-0249A
11 /dts-v1/;
12 #include "vexpress-v2m-rs1.dtsi"
15 model = "V2P-CA15_CA7";
18 compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
[all …]
/openbmc/u-boot/arch/arm/cpu/armv7/ls102xa/
H A Dsoc.c1 // SPDX-License-Identifier: GPL-2.0+
47 { 0x14c, 0x0c, "2D-ACE" },
57 svr = in_be32(&gur->svr); in get_soc_major_rev()
111 struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR + in erratum_a008850_early() local
116 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); in erratum_a008850_early()
118 /* disable the re-ordering in DDRC */ in erratum_a008850_early()
119 out_be32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS); in erratum_a008850_early()
127 struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR + in erratum_a008850_post() local
133 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); in erratum_a008850_post()
135 /* enable the re-ordering in DDRC */ in erratum_a008850_post()
[all …]
/openbmc/u-boot/board/freescale/ls1012afrdm/
H A Dls1012afrdm.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2017-2018 NXP
33 val = in_be32(&pgpio->gpdat) & BOARD_REV_MASK;/*Get GPIO2 11,12,14*/ in get_board_version()
48 puts("Board: FRWY-LS1012A "); in checkboard()
90 gd->ram_size = tfa_get_dram_size(); in dram_init()
92 if (!gd->ram_size) { in dram_init()
97 gd->ram_size = SYS_SDRAM_SIZE_1024; in dram_init()
99 gd->ram_size = SYS_SDRAM_SIZE_512; in dram_init()
101 gd->ram_size = CONFIG_SYS_SDRAM_SIZE; in dram_init()
133 gd->ram_size = SYS_SDRAM_SIZE_1024; in dram_init()
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dsun8i-a83t.dtsi6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/clock/sun8i-a83t-ccu.h>
48 #include <dt-bindings/clock/sun8i-de2.h>
49 #include <dt-bindings/clock/sun8i-r-ccu.h>
50 #include <dt-bindings/reset/sun8i-a83t-ccu.h>
51 #include <dt-bindings/reset/sun8i-de2.h>
52 #include <dt-bindings/reset/sun8i-r-ccu.h>
55 interrupt-parent = <&gic>;
56 #address-cells = <1>;
[all …]
H A Dsun9i-a80.dtsi2 * Copyright 2014 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/clock/sun9i-a80-ccu.h>
48 #include <dt-bindings/clock/sun9i-a80-de.h>
49 #include <dt-bindings/clock/sun9i-a80-usb.h>
50 #include <dt-bindings/reset/sun9i-a80-ccu.h>
51 #include <dt-bindings/reset/sun9i-a80-de.h>
52 #include <dt-bindings/reset/sun9i-a80-usb.h>
[all …]
/openbmc/linux/arch/arm/boot/dts/allwinner/
H A Dsun9i-a80.dtsi2 * Copyright 2014 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/clock/sun9i-a80-ccu.h>
48 #include <dt-bindings/clock/sun9i-a80-de.h>
49 #include <dt-bindings/clock/sun9i-a80-usb.h>
50 #include <dt-bindings/reset/sun9i-a80-ccu.h>
51 #include <dt-bindings/reset/sun9i-a80-de.h>
52 #include <dt-bindings/reset/sun9i-a80-usb.h>
[all …]
H A Dsun8i-a83t.dtsi6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/clock/sun8i-a83t-ccu.h>
48 #include <dt-bindings/clock/sun8i-de2.h>
49 #include <dt-bindings/clock/sun8i-r-ccu.h>
50 #include <dt-bindings/reset/sun8i-a83t-ccu.h>
51 #include <dt-bindings/reset/sun8i-de2.h>
52 #include <dt-bindings/reset/sun8i-r-ccu.h>
53 #include <dt-bindings/thermal/thermal.h>
56 interrupt-parent = <&gic>;
[all …]
/openbmc/u-boot/board/freescale/ls1012aqds/
H A Dls1012aqds.c1 // SPDX-License-Identifier: GPL-2.0+
42 printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1); in checkboard()
63 gd->ram_size = tfa_get_dram_size(); in dram_init()
64 if (!gd->ram_size) in dram_init()
65 gd->ram_size = CONFIG_SYS_SDRAM_SIZE; in dram_init()
89 gd->ram_size = CONFIG_SYS_SDRAM_SIZE; in dram_init()
91 /* This will break-before-make MMU for DDR */ in dram_init()
120 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR + in board_init() local
123 /* Set CCI-400 control override register to enable barrier in board_init()
126 out_le32(&cci->ctrl_ord, in board_init()
[all …]
/openbmc/u-boot/board/freescale/ls1012ardb/
H A Dls1012ardb.c1 // SPDX-License-Identifier: GPL-2.0+
93 gd->ram_size = tfa_get_dram_size(); in dram_init()
94 if (!gd->ram_size) in dram_init()
95 gd->ram_size = CONFIG_SYS_SDRAM_SIZE; in dram_init()
122 gd->ram_size = CONFIG_SYS_SDRAM_SIZE; in dram_init()
124 /* This will break-before-make MMU for DDR */ in dram_init()
142 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR + in board_init() local
145 * Set CCI-400 control override register to enable barrier in board_init()
149 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); in board_init()
156 gd->env_addr = (ulong)&default_environment[0]; in board_init()
[all …]
/openbmc/linux/arch/arm64/boot/dts/broadcom/northstar2/
H A Dns2.dtsi35 #include <dt-bindings/interrupt-controller/arm-gic.h>
36 #include <dt-bindings/clock/bcm-ns2.h>
40 interrupt-parent = <&gic>;
41 #address-cells = <2>;
42 #size-cells = <2>;
45 #address-cells = <2>;
46 #size-cells = <0>;
50 compatible = "arm,cortex-a57";
52 enable-method = "psci";
53 next-level-cache = <&CLUSTER0_L2>;
[all …]
/openbmc/linux/arch/arm/mach-sunxi/
H A Dmc_smp.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018 Chen-Yu Tsai
5 * Chen-Yu Tsai <wens@csie.org>
7 * arch/arm/mach-sunxi/mc_smp.c
9 * Based on Allwinner code, arch/arm/mach-exynos/mcpm-exynos.c, and
10 * arch/arm/mach-hisi/platmcpm.c
14 #include <linux/arm-cci.h>
19 #include <linux/irqchip/arm-gic.h>
70 /* R_CPUCFG registers, specific to sun8i-a83t */
110 is_compatible = of_device_is_compatible(node, "arm,cortex-a15"); in sunxi_core_is_cortex_a15()
[all …]
/openbmc/qemu/hw/cxl/
H A Dcxl-mailbox-utils.c7 * COPYING file in the top-level directory.
17 #include "hw/pci-bridge/cxl_upstream_port.h"
47 * payload from cmd->payload and operating upon it as necessary. It must then
48 * fill the output data into cmd->payload (overwriting what was there),
108 /* CCI Message Format CXL r3.1 Figure 7-19 */
129 CXLCCI *cci) in cmd_tunnel_management_cmd() argument
148 if (cmd->in < sizeof(*in)) { in cmd_tunnel_management_cmd()
157 /* Enough room for minimum sized message - no payload */ in cmd_tunnel_management_cmd()
158 if (in->size < sizeof(in->ccimessage)) { in cmd_tunnel_management_cmd()
161 /* Length of input payload should be in->size + a wrapping tunnel header */ in cmd_tunnel_management_cmd()
[all …]
/openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/
H A Dsoc.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2014-2015 Freescale Semiconductor
13 #include <asm/arch-fsl-layerscape/config.h>
14 #include <asm/arch-fsl-layerscape/ns_access.h>
15 #include <asm/arch-fsl-layerscape/fsl_icid.h>
35 u32 svr = gur_in32(&gur->svr); in soc_has_dp_ddr()
49 u32 svr = gur_in32(&gur->svr); in soc_has_aiop()
346 fusesr = in_le32(&gur->dcfg_fusesr); in get_core_volt_from_fuse()
357 vdd = -EINVAL; in get_core_volt_from_fuse()
367 vdd = -EINVAL; in get_core_volt_from_fuse()
[all …]
/openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/
H A DREADME.soc13 ---------
14 The LS1043A integrated multicore processor combines four ARM Cortex-A53
20 - Four 64-bit ARM Cortex-A53 CPUs
21 - 1 MB unified L2 Cache
22 - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
24 - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
26 - Packet parsing, classification, and distribution (FMan)
27 - Queue management for scheduling, packet sequencing, and congestion
29 - Hardware buffer management for buffer allocation and de-allocation (BMan)
30 - Cryptography acceleration (SEC)
[all …]
/openbmc/u-boot/board/freescale/ls1021atwr/
H A DREADME2 --------
6 ------------------
8 is built on Layerscape architecture, the industry's first software-aware,
9 core-agnostic networking architecture to offer unprecedented efficiency
12 A member of the value-performance tier, the QorIQ LS1021A processor provides
14 enterprise networking applications. Incorporating dual ARM Cortex-A7 cores
15 running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark
17 security features and the broadest array of high-speed interconnects and
18 optimized peripheral features ever offered in a sub-3 W processor.
23 protection on both L1 and L2 caches. The LS1021A processor is pin- and
[all …]
/openbmc/u-boot/board/freescale/ls1021aqds/
H A DREADME2 --------
6 ------------------
8 is built on Layerscape architecture, the industry's first software-aware,
9 core-agnostic networking architecture to offer unprecedented efficiency
12 A member of the value-performance tier, the QorIQ LS1021A processor provides
14 enterprise networking applications. Incorporating dual ARM Cortex-A7 cores
15 running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark
17 security features and the broadest array of high-speed interconnects and
18 optimized peripheral features ever offered in a sub-3 W processor.
23 protection on both L1 and L2 caches. The LS1021A processor is pin- and
[all …]

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