1 // SPDX-License-Identifier: GPL-2.0+
3  * Copyright 2014-2015 Freescale Semiconductor
13 #include <asm/arch-fsl-layerscape/config.h>
14 #include <asm/arch-fsl-layerscape/ns_access.h>
15 #include <asm/arch-fsl-layerscape/fsl_icid.h>
35 	u32 svr = gur_in32(&gur->svr);  in soc_has_dp_ddr()
49 	u32 svr = gur_in32(&gur->svr);  in soc_has_aiop()
346 	fusesr = in_le32(&gur->dcfg_fusesr);  in get_core_volt_from_fuse()
357 		vdd = -EINVAL;  in get_core_volt_from_fuse()
367 		vdd = -EINVAL;  in get_core_volt_from_fuse()
383 	u32 rstrqmr1 = gur_in32(&gur->rstrqmr1);  in erratum_a009929()
386 	gur_out32(&gur->rstrqmr1, rstrqmr1);  in erratum_a009929()
413 	struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +  in erratum_a008850_early()  local
422 	out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);  in erratum_a008850_early()
424 	/* disable the re-ordering in DDRC */  in erratum_a008850_early()
425 	ddr_out32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);  in erratum_a008850_early()
433 	struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +  in erratum_a008850_post()  local
443 	out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);  in erratum_a008850_post()
445 	/* enable the re-ordering in DDRC */  in erratum_a008850_post()
446 	tmp = ddr_in32(&ddr->eor);  in erratum_a008850_post()
448 	ddr_out32(&ddr->eor, tmp);  in erratum_a008850_post()
471 	porsr1 = in_be32(&gur->porsr1);  in erratum_a010539()
487 	fusesr = in_be32(&gur->dcfg_fusesr);  in get_core_volt_from_fuse()
498 		vdd = -EINVAL;  in get_core_volt_from_fuse()
508 		vdd = -EINVAL;  in get_core_volt_from_fuse()
533 	tmp = ddr_in32(&ddr->ddr_cdr1);  in ddr_enable_0v9_volt()
540 	ddr_out32(&ddr->ddr_cdr1, tmp);  in ddr_enable_0v9_volt()
574 	out_be32(&scfg->pfeasbcr,  in init_pfe_scfg_dcfg_regs()
575 		 in_be32(&scfg->pfeasbcr) | SCFG_PFEASBCR_AWCACHE0);  in init_pfe_scfg_dcfg_regs()
576 	out_be32(&scfg->pfebsbcr,  in init_pfe_scfg_dcfg_regs()
577 		 in_be32(&scfg->pfebsbcr) | SCFG_PFEASBCR_AWCACHE0);  in init_pfe_scfg_dcfg_regs()
579 	/* CCI-400 QoS settings for PFE */  in init_pfe_scfg_dcfg_regs()
580 	out_be32(&scfg->wr_qos1, (unsigned int)(SCFG_WR_QOS1_PFE1_QOS  in init_pfe_scfg_dcfg_regs()
582 	out_be32(&scfg->rd_qos1, (unsigned int)(SCFG_RD_QOS1_PFE1_QOS  in init_pfe_scfg_dcfg_regs()
593 	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +  in fsl_lsch2_early_init_f()  local
606 	out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);  in fsl_lsch2_early_init_f()
609 	setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |  in fsl_lsch2_early_init_f()
619 		out_le32(&cci->slave[4].snoop_ctrl,  in fsl_lsch2_early_init_f()
808 	 * check if gd->env_addr is default_environment; then setenv bootcmd  in board_late_init()
811 	if (gd->env_addr + gd->reloc_off == (ulong)&default_environment[0]) {  in board_late_init()