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Searched +full:card +full:- +full:detect +full:- +full:delay (Results 1 – 25 of 42) sorted by relevance

12

/openbmc/u-boot/arch/arm/mach-sunxi/
H A DKconfig4 default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64
87 ---help---
100 ---help---
102 as the original A10 (mach-sun4i).
106 ---help---
113 ---help---
116 not have official open-source DRAM initialization code, but can
122 ---help---
124 have only 16-bit memory buswidth.
128 ---help---
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/openbmc/openbmc/meta-openembedded/meta-oe/recipes-support/pxaregs/pxaregs-1.14/
H A Dpxaregs.c2 * pxaregs - tool to display and modify PXA250's registers at runtime
4 * (c) Copyright 2002 by M&N Logistik-Lösungen Online GmbH
9 * Please send patches to h.schurig, working at mn-logistik.de
10 * - added fix from Bernhard Nemec
11 * - i2c registers from Stefan Eletzhofer
25 #include <linux/i2c-dev.h>
29 static int fd = -1;
85 { "PMCR", 0x40F00000, 0, 0xffffffff, 'x', "Power Manager Control Register (3-23)" },
88 { "PSSR", 0x40F00004, 0, 0xffffffff, 'x', "Power Manager Sleep Status Register (3-29)" },
95 { "PSPR", 0x40F00008, 0, 0xffffffff, 'x', "Power Manager Scratch Pad Register (3-30)" },
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/openbmc/u-boot/drivers/ddr/marvell/a38x/
H A Dmv_ddr_spd.h1 /* SPDX-License-Identifier: GPL-2.0 */
12 * Based on JEDEC Standard No. 21-C, 4.1.2.L-4:
13 * Serial Presence Detect (SPD) for DDR4 SDRAM Modules
18 /* block 1: module specific parameters sub-block */
20 /* block 1: hybrid memory parameters sub-block */
176 unsigned char byte_25; /* min ras to cas delay time (t rcd min), mtb */
177 unsigned char byte_26; /* min row precharge delay time (t rp min), mtb */
185 unsigned char byte_28; /* min active to precharge delay time (t ras min), l-s-byte, mtb */
186 unsigned char byte_29; /* min active to active/refresh delay time (t rc min), l-s-byte, mtb */
187 unsigned char byte_30; /* min refresh recovery delay time (t rfc1 min), l-s-byte, mtb */
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/openbmc/u-boot/arch/arm/dts/
H A Drk3229-evb.dts1 // SPDX-License-Identifier: GPL-2.0+ OR X11
6 /dts-v1/;
12 compatible = "rockchip,rk3229-evb", "rockchip,rk3229";
15 stdout-path = &uart2;
24 compatible = "fixed-clock";
25 clock-frequency = <125000000>;
26 clock-output-names = "ext_gmac";
27 #clock-cells = <0>;
30 vcc_phy: vcc-phy-regulator {
31 compatible = "regulator-fixed";
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H A Drk3288-rock2-square.dts2 * This file is dual-licensed: you can use it either under the terms
41 /dts-v1/;
42 #include "rk3288-rock2-som.dtsi"
46 compatible = "radxa,rock2-square", "rockchip,rk3288";
49 stdout-path = "serial2:115200n8";
52 ir: ir-receiver {
53 compatible = "gpio-ir-receiver";
55 pinctrl-names = "default";
56 pinctrl-0 = <&ir_int>;
60 compatible = "simple-audio-card";
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H A Drk3399-gru.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright 2016-2017 Google, Inc
8 #include <dt-bindings/input/input.h>
10 #include "rk3399-op1-opp.dtsi"
14 u-boot,dm-pre-reloc;
15 stdout-path = "serial2:115200n8";
16 u-boot,spl-boot-order = &spi_flash;
20 u-boot,spl-payload-offset = <0x40000>;
29 * - Rails that only connect to the EC (or devices that the EC talks to)
31 * - Rails _are_ included if the rails go to the AP even if the AP
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H A Drk3328-evb.dts1 // SPDX-License-Identifier: GPL-2.0+
6 /dts-v1/;
11 compatible = "rockchip,rk3328-evb", "rockchip,rk3328";
14 stdout-path = &uart2;
17 gmac_clkin: external-gmac-clock {
18 compatible = "fixed-clock";
19 clock-frequency = <125000000>;
20 clock-output-names = "gmac_clkin";
21 #clock-cells = <0>;
24 vcc3v3_sdmmc: sdmmc-pwren {
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H A Drk3288-miqi.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR X11
14 ext_gmac: external-gmac-clock {
15 compatible = "fixed-clock";
16 #clock-cells = <0>;
17 clock-frequency = <125000000>;
18 clock-output-names = "ext_gmac";
21 io_domains: io-domains {
22 compatible = "rockchip,rk3288-io-voltage-domain";
25 audio-supply = <&vcca_33>;
26 flash0-supply = <&vcc_flash>;
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H A Drk3288-veyron.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/rockchip,rk808.h>
9 #include <dt-bindings/input/input.h>
18 stdout-path = &uart2;
22 u-boot,dm-pre-reloc;
23 u-boot,boot0 = &spi_flash;
28 pinctrl-names = "default";
29 pinctrl-0 = <&fw_wp_ap>;
30 write-protect-gpio = <&gpio7 6 GPIO_ACTIVE_LOW>;
35 compatible = "pwm-backlight";
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H A Darmada-8040-clearfog-gt-8k.dts1 // SPDX-License-Identifier: GPL-2.0
6 #include "armada-8040.dtsi"
9 model = "ClearFog-GT-8K";
10 compatible = "solidrun,clearfog-gt-8k",
14 stdout-path = "serial0:115200n8";
28 simple-bus {
29 compatible = "simple-bus";
31 reg_usb3h0_vbus: usb3-vbus0 {
32 compatible = "regulator-fixed";
33 pinctrl-names = "default";
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H A Drk3399-rock960.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/pwm/pwm.h>
7 #include <dt-bindings/pinctrl/rockchip.h>
11 vcc1v8_s0: vcc1v8-s0 {
12 compatible = "regulator-fixed";
13 regulator-name = "vcc1v8_s0";
14 regulator-min-microvolt = <1800000>;
15 regulator-max-microvolt = <1800000>;
16 regulator-always-on;
19 vcc_sys: vcc-sys {
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H A Drk3288-phycore-rdk.dts2 * Device tree file for Phytec PCM-947 carrier board
6 * This file is dual-licensed: you can use it either under the terms
45 /dts-v1/;
47 #include <dt-bindings/input/input.h>
48 #include "rk3288-phycore-som.dtsi"
51 model = "Phytec RK3288 PCM-947";
52 compatible = "phytec,rk3288-pcm-947", "phytec,rk3288-phycore-som", "rockchip,rk3288";
55 stdout-path = &uart2;
59 u-boot,dm-pre-reloc;
60 u-boot,boot0 = &emmc;
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H A Darmada-8040-mcbin.dts1 // SPDX-License-Identifier: GPL-2.0
6 #include "armada-8040.dtsi" /* include SoC device tree */
9 model = "MACCHIATOBin-8040";
10 compatible = "marvell,armada8040-mcbin",
14 stdout-path = "serial0:115200n8";
31 simple-bus {
32 compatible = "simple-bus";
33 #address-cells = <1>;
34 #size-cells = <0>;
36 reg_usb3h0_vbus: usb3-vbus0 {
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H A Drk3288-firefly.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR X11
13 ext_gmac: external-gmac-clock {
14 compatible = "fixed-clock";
15 #clock-cells = <0>;
16 clock-frequency = <125000000>;
17 clock-output-names = "ext_gmac";
20 ir: ir-receiver {
21 compatible = "gpio-ir-receiver";
22 pinctrl-names = "default";
23 pinctrl-0 = <&ir_int>;
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H A Drk3288-evb.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR X11
13 ext_gmac: external-gmac-clock {
14 compatible = "fixed-clock";
15 #clock-cells = <0>;
16 clock-frequency = <125000000>;
17 clock-output-names = "ext_gmac";
20 keys: gpio-keys {
21 compatible = "gpio-keys";
24 gpio-key,wakeup = <1>;
28 pinctrl-names = "default";
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H A Drk3288-popmetal.dtsi2 * This file is dual-licensed: you can use it either under the terms
49 ext_gmac: external-gmac-clock {
50 compatible = "fixed-clock";
51 clock-frequency = <125000000>;
52 clock-output-names = "ext_gmac";
53 #clock-cells = <0>;
56 gpio-keys {
57 compatible = "gpio-keys";
60 pinctrl-names = "default";
61 pinctrl-0 = <&pwrbtn>;
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H A Drk3288-tinker.dtsi2 * This file is dual-licensed: you can use it either under the terms
49 ext_gmac: external-gmac-clock {
50 compatible = "fixed-clock";
51 clock-frequency = <125000000>;
52 clock-output-names = "ext_gmac";
53 #clock-cells = <0>;
56 gpio-keys {
57 compatible = "gpio-keys";
60 pinctrl-names = "default";
61 pinctrl-0 = <&pwrbtn>;
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H A Drk3288-fennec.dtsi2 * This file is dual-licensed: you can use it either under the terms
49 ext_gmac: external-gmac-clock {
50 compatible = "fixed-clock";
51 #clock-cells = <0>;
52 clock-frequency = <125000000>;
53 clock-output-names = "ext_gmac";
56 vcc_sys: vsys-regulator {
57 compatible = "regulator-fixed";
58 regulator-name = "vcc_sys";
59 regulator-min-microvolt = <5000000>;
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/openbmc/u-boot/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h2 * linux/include/asm-arm/arch-pxa/pxa-regs.h
12 * - 2003/01/20: Robert Schwebel <r.schwebel@pengutronix.de
13 * Original file taken from linux-2.4.19-rmk4-pxa1. Added some definitions.
22 /* FIXME hack so that SA-1111.h will work [cb] */
53 * Personal Computer Memory Card International Association (PCMCIA) sockets
134 #define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */
147 #define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */
148 #define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */
302 #define DCMD_ENDIAN (1 << 18) /* Device Endian-ness. */
309 #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
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/openbmc/u-boot/board/kosagi/novena/
H A Dnovena_spl.c1 // SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/mx6-ddr.h>
13 #include <asm/arch/mx6-pins.h>
16 #include <asm/mach-imx/boot_mode.h>
17 #include <asm/mach-imx/iomux-v3.h>
18 #include <asm/mach-imx/mxc_i2c.h>
25 #include <asm/arch/mx6-ddr.h>
132 * Use imx6 internal pull-ups to drive PHY mode pins during PHY reset in novena_spl_setup_iomux_enet()
133 * de-assertion. The intention is to use weak signal drivers (pull-ups) in novena_spl_setup_iomux_enet()
148 /* De-assert Ethernet PHY nRST */ in novena_spl_setup_iomux_enet()
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/openbmc/u-boot/board/wandboard/
H A Dwandboard.c1 // SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/imx-regs.h>
13 #include <asm/arch/mx6-pins.h>
17 #include <asm/mach-imx/iomux-v3.h>
18 #include <asm/mach-imx/mxc_i2c.h>
19 #include <asm/mach-imx/boot_mode.h>
20 #include <asm/mach-imx/video.h>
21 #include <asm/mach-imx/sata.h>
61 gd->ram_size = imx_ddr_size(); in dram_init()
78 /* Carrier MicroSD Card Detect */
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/openbmc/u-boot/drivers/mmc/
H A Dsunxi_mmc.c1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2007-2011
22 #include <asm-generic/gpio.h>
39 struct gpio_desc cd_gpio; /* Change Detect GPIO */
40 int cd_inverted; /* Inverted Card Detect */
60 return -EINVAL; in sunxi_mmc_getcd_gpio()
73 priv->reg = (struct sunxi_mmc *)SUNXI_MMC0_BASE; in mmc_resource_init()
74 priv->mclkreg = &ccm->sd0_clk_cfg; in mmc_resource_init()
77 priv->reg = (struct sunxi_mmc *)SUNXI_MMC1_BASE; in mmc_resource_init()
78 priv->mclkreg = &ccm->sd1_clk_cfg; in mmc_resource_init()
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/openbmc/openbmc/meta-security/recipes-ids/suricata/files/
H A Dsuricata.yaml2 ---
13 # If you are using the CUDA pattern matcher (mpm-algo: ac-cuda), different rules
16 #max-pending-packets: 1024
18 # Runmode the engine should use. Please check --list-runmodes to get the available
27 # round-robin - Flows assigned to threads in a round robin fashion.
28 # active-packets - Flows assigned to threads that have the lowest number of
30 # hash - Flow alloted usihng the address hash. More of a random
33 #autofp-scheduler: active-packets
36 # it is a pure sniffing setup, set it to 'sniffer-only'.
38 # and 'sniffer-only' in IDS mode.
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/openbmc/u-boot/include/linux/
H A Dserial_reg.h1 /* SPDX-License-Identifier: GPL-2.0+ */
39 #define UART_IIR_BUSY 0x07 /* DesignWare APB Busy Detect */
116 #define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS (TI16C550C/TI16C750) */
126 #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
135 #define UART_MSR_DCD 0x80 /* Data Carrier Detect */
160 #define UART_EFR_SCD 0x20 /* Special character detect */
200 #define UART_FCTR_RTS_NODELAY 0x00 /* RTS flow control delay */
222 * The Intel XScale on-chip UARTs define these bits
237 * Intel MID on-chip HSU (High Speed UART) defined bits
277 #define UART_NMR 0x0D /* Nine-bit Mode Register */
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/openbmc/u-boot/doc/driver-model/
H A Dof-plat.txt1 Driver Model Compiled-in Device Tree / Platform Data
6 ------------
8 Device tree is the standard configuration method in U-Boot. It is used to
12 The overhead of adding device tree access to U-Boot is fairly modest,
16 However there are some very constrained environments where U-Boot needs to
26 As an alternative, a new 'of-platdata' feature is provided. This converts the
37 -------
42 - Device tree does not describe data types. But the C code must define a
44 are wrong in several fairly common cases. For example an 8-byte value
45 is considered to be a 2-item integer array, and is byte-swapped. A
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