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/openbmc/qemu/tests/qemu-iotests/
H A D142.out6 === Simple test for all cache modes ===
8 Testing: -drive file=TEST_DIR/t.qcow2,cache=none
9 QEMU X.Y.Z monitor - type 'help' for more information
12 Testing: -drive file=TEST_DIR/t.qcow2,cache=directsync
13 QEMU X.Y.Z monitor - type 'help' for more information
16 Testing: -drive file=TEST_DIR/t.qcow2,cache=writeback
17 QEMU X.Y.Z monitor - type 'help' for more information
20 Testing: -drive file=TEST_DIR/t.qcow2,cache=writethrough
21 QEMU X.Y.Z monitor - type 'help' for more information
24 Testing: -drive file=TEST_DIR/t.qcow2,cache=unsafe
[all …]
H A D1423 # Test for configuring cache modes of arbitrary nodes (requires O_DIRECT)
43 # We test all cache modes anyway, but O_DIRECT needs to be supported
51 if ! test -t 0; then
57 ) | $QEMU -nographic -monitor stdio -nodefaults "$@"
70 _make_test_img -b "$TEST_IMG.base" $size -F $IMGFMT
73 echo === Simple test for all cache modes ===
76 run_qemu -drive file="$TEST_IMG",cache=none
77 run_qemu -drive file="$TEST_IMG",cache=directsync
78 run_qemu -drive file="$TEST_IMG",cache=writeback
79 run_qemu -drive file="$TEST_IMG",cache=writethrough
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/openbmc/linux/arch/powerpc/kernel/
H A Dcacheinfo.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Processor cache information made available to userspace via sysfs;
26 /* per-cpu object for tracking:
27 * - a "cache" kobject for the top-level directory
28 * - a list of "index" objects representing the cpu's local cache hierarchy
31 struct kobject *kobj; /* bare (not embedded) kobject for cache
36 /* "index" object: each cpu's cache directory has an index
37 * subdirectory corresponding to a cache object associated with the
43 struct cache *cache; member
47 * cache type */
[all …]
/openbmc/linux/fs/fscache/
H A Dcache.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* FS-Cache cache handling
8 #define FSCACHE_DEBUG_LEVEL CACHE
22 * Allocate a cache cookie.
26 struct fscache_cache *cache; in fscache_alloc_cache() local
28 cache = kzalloc(sizeof(*cache), GFP_KERNEL); in fscache_alloc_cache()
29 if (cache) { in fscache_alloc_cache()
31 cache->name = kstrdup(name, GFP_KERNEL); in fscache_alloc_cache()
32 if (!cache->name) { in fscache_alloc_cache()
33 kfree(cache); in fscache_alloc_cache()
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/openbmc/linux/drivers/md/
H A Ddm-cache-target.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include "dm-bio-prison-v2.h"
10 #include "dm-bio-record.h"
11 #include "dm-cache-metadata.h"
12 #include "dm-io-tracker.h"
13 #include "dm-cache-background-tracker.h"
15 #include <linux/dm-io.h>
16 #include <linux/dm-kcopyd.h>
25 #define DM_MSG_PREFIX "cache"
28 "A percentage of time allocated for copying to and/or from cache");
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/openbmc/linux/fs/cachefiles/
H A Dcache.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Manage high-level VFS aspects of a cache.
15 * Bring a cache online.
17 int cachefiles_add_cache(struct cachefiles_cache *cache) in cachefiles_add_cache() argument
28 cache_cookie = fscache_acquire_cache(cache->tag); in cachefiles_add_cache()
33 ret = cachefiles_get_security_ID(cache); in cachefiles_add_cache()
37 cachefiles_begin_secure(cache, &saved_cred); in cachefiles_add_cache()
39 /* look up the directory at the root of the cache */ in cachefiles_add_cache()
40 ret = kern_path(cache->rootdirname, LOOKUP_DIRECTORY, &path); in cachefiles_add_cache()
44 cache->mnt = path.mnt; in cachefiles_add_cache()
[all …]
H A Ddaemon.c1 // SPDX-License-Identifier: GPL-2.0-or-later
62 int (*handler)(struct cachefiles_cache *cache, char *args);
88 * Prepare a cache for caching.
92 struct cachefiles_cache *cache; in cachefiles_daemon_open() local
98 return -EPERM; in cachefiles_daemon_open()
102 return -EBUSY; in cachefiles_daemon_open()
104 /* allocate a cache record */ in cachefiles_daemon_open()
105 cache = kzalloc(sizeof(struct cachefiles_cache), GFP_KERNEL); in cachefiles_daemon_open()
106 if (!cache) { in cachefiles_daemon_open()
108 return -ENOMEM; in cachefiles_daemon_open()
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/openbmc/linux/arch/arm64/boot/dts/amazon/
H A Dalpine-v3.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 compatible = "amazon,al-alpine-v3";
14 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
20 #address-cells = <1>;
21 #size-cells = <0>;
25 compatible = "arm,cortex-a72";
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/openbmc/linux/tools/perf/pmu-events/arch/s390/cf_z16/
H A Dextended.json3 "Unit": "CPU-M-CF",
6 "BriefDescription": "L1D Read-only Exclusive Writes",
7 …-1 Data cache where the line was originally in a Read-Only state in the cache but has been updated…
10 "Unit": "CPU-M-CF",
14 …lation Lookaside Buffer 2 (TLB2) and the request was made by the Level-1 Data cache. This is a rep…
17 "Unit": "CPU-M-CF",
21 …or a request made by the Level-1 Data cache. Incremented by one for every TLB2 miss in progress fo…
24 "Unit": "CPU-M-CF",
28 … into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte page…
31 "Unit": "CPU-M-CF",
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/openbmc/linux/arch/arm64/boot/dts/amd/
H A Damd-seattle-cpus.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 #address-cells = <0x1>;
6 #size-cells = <0x0>;
8 cpu-map {
45 compatible = "arm,cortex-a57";
47 enable-method = "psci";
49 i-cache-size = <0xC000>;
50 i-cache-line-size = <64>;
51 i-cache-sets = <256>;
52 d-cache-size = <0x8000>;
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/openbmc/linux/Documentation/devicetree/bindings/cache/
H A Dfreescale-l2cache.txt1 Freescale L2 Cache Controller
3 L2 cache is present in Freescale's QorIQ and QorIQ Qonverge platforms.
4 The cache bindings explained below are Devicetree Specification compliant
8 - compatible : Should include one of the following:
9 "fsl,b4420-l2-cache-controller"
10 "fsl,b4860-l2-cache-controller"
11 "fsl,bsc9131-l2-cache-controller"
12 "fsl,bsc9132-l2-cache-controller"
13 "fsl,c293-l2-cache-controller"
14 "fsl,mpc8536-l2-cache-controller"
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H A Dsocionext,uniphier-system-cache.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/cache/socionext,uniphier-system-cache.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: UniPhier outer cache controller
10 UniPhier ARM 32-bit SoCs are integrated with a full-custom outer cache
11 controller system. All of them have a level 2 cache controller, and some
12 have a level 3 cache controller as well.
15 - Masahiro Yamada <yamada.masahiro@socionext.com>
19 const: socionext,uniphier-system-cache
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/openbmc/linux/fs/
H A Dmbcache.c1 // SPDX-License-Identifier: GPL-2.0-only
12 * Mbcache is a simple key-value store. Keys need not be unique, however
13 * key-value pairs are expected to be unique (we use this fact in
16 * Ext2 and ext4 use this cache for deduplication of extended attribute blocks.
21 * identifies a cache entry.
24 * and a special "delete entry with given key-value pair" operation. Fixed
33 /* Maximum entries in cache to avoid degrading hash too much */
38 /* Number of entries in cache */
41 /* Work for shrinking when the cache has too many entries */
47 static unsigned long mb_cache_shrink(struct mb_cache *cache,
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/openbmc/linux/fs/squashfs/
H A Dcache.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Squashfs - a compressed read only filesystem for Linux
8 * cache.c
15 * This file implements a generic cache implementation used for both caches,
16 * plus functions layered ontop of the generic cache implementation to
19 * To avoid out of memory and fragmentation issues with vmalloc the cache
22 * It should be noted that the cache is not used for file datablocks, these
23 * are decompressed and cached in the page-cache in the normal way. The
24 * cache is only used to temporarily cache fragment and metadata blocks
29 * have been packed with it, these because of locality-of-reference may be read
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/openbmc/qemu/migration/
H A Dpage_cache.c2 * Page cache for QEMU
3 * The cache is base on a hash of the page address
11 * See the COPYING file in the top-level directory.
19 #include "qemu/host-utils.h"
23 /* the page in cache will not be replaced in two cycles */
45 PageCache *cache; in cache_init() local
48 error_setg(errp, QERR_INVALID_PARAMETER_VALUE, "cache size", in cache_init()
55 error_setg(errp, QERR_INVALID_PARAMETER_VALUE, "cache size", in cache_init()
61 cache = g_try_malloc(sizeof(*cache)); in cache_init()
62 if (!cache) { in cache_init()
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/openbmc/linux/mm/
H A Dswap_slots.c1 // SPDX-License-Identifier: GPL-2.0
3 * Manage cache of swap slots to be used for and returned from
25 * The swap slots cache is protected by a mutex instead of
43 /* Serialize swap slots cache enable/disable operations */
106 /* if global pool of slot caches too low, deactivate cache */ in check_cache_active()
115 struct swap_slots_cache *cache; in alloc_swap_slot_cache() local
126 return -ENOMEM; in alloc_swap_slot_cache()
132 return -ENOMEM; in alloc_swap_slot_cache()
136 cache = &per_cpu(swp_slots, cpu); in alloc_swap_slot_cache()
137 if (cache->slots || cache->slots_ret) { in alloc_swap_slot_cache()
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/openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a65-e1/
H A Dcache.json111 …"Level 1 data cache refill started due to prefetch. Counts any linefills from the prefetcher which…
114 …"Level 1 data cache refill started due to prefetch. Counts any linefills from the prefetcher which…
117 …cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: This event …
120 …cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: This event …
123 …cache refill due to prefetch. This event counts any linefills from the hardware prefetcher which c…
126 …cache refill due to prefetch. This event counts any linefills from the hardware prefetcher which c…
141 … 2 cache write streaming mode. This event counts for each cycle where the core is in write-streami…
144 … 2 cache write streaming mode. This event counts for each cycle where the core is in write-streami…
147 … 3 cache write streaming mode. This event counts for each cycle where the core is in write-streami…
150 … 3 cache write streaming mode. This event counts for each cycle where the core is in write-streami…
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/openbmc/linux/arch/arm64/boot/dts/ti/
H A Dk3-am654.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
8 #include "k3-am65.dtsi"
12 #address-cells = <1>;
13 #size-cells = <0>;
14 cpu-map {
37 compatible = "arm,cortex-a53";
40 enable-method = "psci";
41 i-cache-size = <0x8000>;
42 i-cache-line-size = <64>;
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/openbmc/linux/tools/perf/pmu-events/arch/s390/cf_z13/
H A Dextended.json3 "Unit": "CPU-M-CF",
6 "BriefDescription": "L1D Read-only Exclusive Writes",
7 …-1 Data cache where the line was originally in a Read-Only state in the cache but has been updated…
10 "Unit": "CPU-M-CF",
14 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi…
17 "Unit": "CPU-M-CF",
21 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB…
24 "Unit": "CPU-M-CF",
27 "BriefDescription": "DTLB1 One-Megabyte Page Writes",
28 …": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a on…
[all …]
/openbmc/linux/fs/nfs/
H A Dnfs42xattr.c1 // SPDX-License-Identifier: GPL-2.0
6 * User extended attribute client side cache functions.
21 * a cache structure attached to NFS inodes. This structure is allocated
22 * when needed, and freed when the cache is zapped.
24 * The cache structure contains as hash table of entries, and a pointer
25 * to a special-cased entry for the listxattr cache.
28 * counting. The cache entries use a similar refcounting scheme.
30 * This makes freeing a cache, both from the shrinker and from the
31 * zap cache path, easy. It also means that, in current use cases,
40 * Two shrinkers deal with the cache entries themselves: one for
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dk3-am654.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
8 #include "k3-am65.dtsi"
12 #address-cells = <1>;
13 #size-cells = <0>;
14 cpu-map {
37 compatible = "arm,cortex-a53", "arm,armv8";
40 enable-method = "psci";
41 i-cache-size = <0x8000>;
42 i-cache-line-size = <64>;
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/openbmc/linux/arch/arm64/boot/dts/marvell/
H A Darmada-ap807-quad.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include "armada-ap807.dtsi"
12 compatible = "marvell,armada-ap807-quad", "marvell,armada-ap807";
15 #address-cells = <1>;
16 #size-cells = <0>;
20 compatible = "arm,cortex-a72";
22 enable-method = "psci";
23 #cooling-cells = <2>;
25 i-cache-size = <0xc000>;
26 i-cache-line-size = <64>;
[all …]
H A Darmada-ap806-quad.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include "armada-ap806.dtsi"
12 compatible = "marvell,armada-ap806-quad", "marvell,armada-ap806";
15 #address-cells = <1>;
16 #size-cells = <0>;
20 compatible = "arm,cortex-a72";
22 enable-method = "psci";
23 #cooling-cells = <2>;
25 i-cache-size = <0xc000>;
26 i-cache-line-size = <64>;
[all …]
/openbmc/linux/fs/btrfs/
H A Dlru_cache.c1 // SPDX-License-Identifier: GPL-2.0
8 * Initialize a cache object.
10 * @cache: The cache.
11 * @max_size: Maximum size (number of entries) for the cache.
13 * trim the cache in that case.
15 void btrfs_lru_cache_init(struct btrfs_lru_cache *cache, unsigned int max_size) in btrfs_lru_cache_init() argument
17 INIT_LIST_HEAD(&cache->lru_list); in btrfs_lru_cache_init()
18 mt_init(&cache->entries); in btrfs_lru_cache_init()
19 cache->size = 0; in btrfs_lru_cache_init()
20 cache->max_size = max_size; in btrfs_lru_cache_init()
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/openbmc/linux/tools/perf/pmu-events/arch/s390/cf_z14/
H A Dextended.json3 "Unit": "CPU-M-CF",
6 "BriefDescription": "L1D Read-only Exclusive Writes",
7 …-1 Data cache where the line was originally in a Read-Only state in the cache but has been updated…
10 "Unit": "CPU-M-CF",
14 …ranslation Lookaside Buffer 2 (TLB2) and the request was made by the data cache. This is a replace…
17 "Unit": "CPU-M-CF",
21 …ss for a request made by the data cache. Incremented by one for every TLB2 miss in progress for th…
24 "Unit": "CPU-M-CF",
27 "BriefDescription": "DTLB2 One-Megabyte Page Writes",
28 … into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte page…
[all …]

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