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/openbmc/u-boot/arch/arm/mach-exynos/
H A Ddmc_init_exynos4.c23 * MA 02111-1307 USA
27 #include <asm/arch/dmc.h>
51 static void phy_control_reset(int ctrl_no, struct exynos4_dmc *dmc) in phy_control_reset() argument
55 &dmc->phycontrol1); in phy_control_reset()
57 &dmc->phycontrol1); in phy_control_reset()
60 &dmc->phycontrol0); in phy_control_reset()
62 &dmc->phycontrol0); in phy_control_reset()
66 static void dmc_config_mrs(struct exynos4_dmc *dmc, int chip) in dmc_config_mrs() argument
76 &dmc->directcmd); in dmc_config_mrs()
80 static void dmc_init(struct exynos4_dmc *dmc) in dmc_init() argument
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H A Dexynos5_setup.h1 /* SPDX-License-Identifier: GPL-2.0+ */
12 #include <asm/arch/dmc.h>
69 * register must be set as half of the bus base address
168 /* SCLK_SRC_ISP - set SPI0/1 to 6 = SCLK_MPLL_USER */
174 /* SCLK_DIV_ISP - set SPI0/1 to 0xf = divide by 16 */
408 #define BUSIF_WR_CG_EN (1 << 1) /* Bus interface write channel clock gating */
409 #define BUSIF_RD_CG_EN (1 << 0) /* Bus interface read channel clock gating */
413 /* DMC PHY Control0 register */
889 /* Errors that we can encourter in low-level setup */
892 SETUP_ERR_RDLV_COMPLETE_TIMEOUT = -1,
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/openbmc/linux/Documentation/devicetree/bindings/interconnect/
H A Dsamsung,exynos-bus.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interconnect/samsung,exynos-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos SoC Bus and Interconnect
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
15 sub-blocks in SoC. Most Exynos SoCs share the common architecture for buses.
16 Generally, each bus of Exynos SoC includes a source clock and a power line,
17 which are able to change the clock frequency of the bus in runtime. To
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/openbmc/u-boot/doc/device-tree-bindings/clock/
H A Drockchip,rk3368-dmc.txt4 The RK3368 DMC (dynamic memory controller) driver supports setup/initialisation
7 (a) a target-frequency (i.e. operating point) for the memory operation
8 (b) a speed-bin (as defined in JESD-79) for the DDR3 used in hardware
9 (c) a memory-schedule (i.e. mapping from physical addresses to the address
10 pins of the memory bus)
13 -------------------
15 - compatible: "rockchip,rk3368-dmc"
16 - reg
18 - rockchip,ddr-speed-bin
19 the DDR3 device's speed-bin (as specified according to JESD-79)
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/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Drockchip,rk3399-dmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/rockchip,rk3399-dmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip rk3399 DMC (Dynamic Memory Controller) device
10 - Brian Norris <briannorris@chromium.org>
15 - rockchip,rk3399-dmc
17 devfreq-events:
21 Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt.
26 clock-names:
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/openbmc/linux/drivers/devfreq/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
20 to a device by 1-to-1. The device registering devfreq takes the
39 Simple-Ondemand should be able to provide busy/total counter
79 tristate "ARM Exynos Generic Memory Bus DEVFREQ Driver"
86 This adds the common DEVFREQ driver for Exynos Memory bus. Exynos
87 Memory bus has one more group of memory bus (e.g, MIF and INT block).
88 Each memory bus group could contain many memoby bus block. It reads
89 PPMU counters of memory controllers by using DEVFREQ-event device
94 tristate "i.MX Generic Bus DEVFREQ Driver"
133 tristate "ARM RK3399 DMC DEVFREQ Driver"
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/openbmc/linux/drivers/cpufreq/
H A Ds5pv210-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0-only
194 * ch: DMC port number 0 or 1
207 pr_err("Cannot find DMC port\n"); in s5pv210_set_refresh()
238 ret = -EINVAL; in s5pv210_target()
242 old_freq = policy->cur; in s5pv210_target()
267 /* Check if there need to change System bus clock */ in s5pv210_target()
287 * APLL -> MPLL(for stable transition) -> APLL in s5pv210_target()
294 * SCLKA2M(200/1=200)->(200/4=50)Mhz in s5pv210_target()
309 * (200/4=50)->(667/4=166)Mhz in s5pv210_target()
329 /* 4. SCLKAPLL -> SCLKMPLL */ in s5pv210_target()
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/openbmc/linux/drivers/edac/
H A Ddmc520_edac.c1 // SPDX-License-Identifier: GPL-2.0
4 * EDAC driver for DMC-520 memory controller.
25 /* DMC-520 registers */
43 /* DMC-520 types, masks and bitfields */
78 * The max-length message would be: "rank:7 bank:15 row:262143 col:1023".
79 * Max length is 34. Using a 40-size buffer is enough.
82 #define EDAC_MOD_NAME "dmc520-edac"
85 /* the data bus width for the attached memory chips. */
165 * error_lock is to protect concurrent writes to the mci->error_desc through
180 return readl(pvt->reg_base + offset); in dmc520_read_reg()
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/openbmc/linux/arch/arm/boot/dts/samsung/
H A Ds5pv210.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd.
19 #include <dt-bindings/clock/s5pv210.h>
20 #include <dt-bindings/clock/s5pv210-audss.h>
23 #address-cells = <1>;
24 #size-cells = <1>;
45 #address-cells = <1>;
46 #size-cells = <0>;
50 compatible = "arm,cortex-a8";
55 xxti: oscillator-0 {
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H A Dexynos3250.dtsi1 // SPDX-License-Identifier: GPL-2.0
17 #include "exynos4-cpu-thermal.dtsi"
18 #include <dt-bindings/clock/exynos3250.h>
19 #include <dt-bindings/interrupt-controller/arm-gic.h>
20 #include <dt-bindings/interrupt-controller/irq.h>
24 interrupt-parent = <&gic>;
25 #address-cells = <1>;
26 #size-cells = <1>;
46 bus_dmc: bus-dmc {
47 compatible = "samsung,exynos-bus";
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H A Dexynos4210.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2010-2011 Linaro Ltd.
20 #include "exynos4-cpu-thermal.dtsi"
31 bus_acp: bus-acp {
32 compatible = "samsung,exynos-bus";
34 clock-names = "bus";
35 operating-points-v2 = <&bus_acp_opp_table>;
38 bus_acp_opp_table: opp-table {
39 compatible = "operating-points-v2";
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H A Dexynos5420.dtsi1 // SPDX-License-Identifier: GPL-2.0
14 #include <dt-bindings/clock/exynos5420.h>
15 #include <dt-bindings/clock/exynos-audss-clk.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
37 bus_disp1: bus-disp1 {
38 compatible = "samsung,exynos-bus";
40 clock-names = "bus";
44 bus_disp1_fimd: bus-disp1-fimd {
45 compatible = "samsung,exynos-bus";
47 clock-names = "bus";
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/openbmc/linux/drivers/net/ethernet/sun/
H A Dniu.h1 /* SPDX-License-Identifier: GPL-2.0 */
19 #define DMC 0x600000UL macro
130 /* XMAC registers, offset from np->mac_regs */
415 /* BMAC registers, offset from np->mac_regs */
591 /* XPCS registers, offset from np->regs + np->xpcs_off */
688 /* PCS registers, offset from np->regs + np->pcs_off */
1201 #define TCAM_KEY_0_KEY 0x00000000000000ffULL /* bits 192-199 */
1204 #define TCAM_KEY_1_KEY 0xffffffffffffffffULL /* bits 128-191 */
1207 #define TCAM_KEY_2_KEY 0xffffffffffffffffULL /* bits 64-127 */
1210 #define TCAM_KEY_3_KEY 0xffffffffffffffffULL /* bits 0-63 */
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/openbmc/u-boot/arch/arm/dts/
H A Drk3229-evb.dts1 // SPDX-License-Identifier: GPL-2.0+ OR X11
6 /dts-v1/;
12 compatible = "rockchip,rk3229-evb", "rockchip,rk3229";
15 stdout-path = &uart2;
24 compatible = "fixed-clock";
25 clock-frequency = <125000000>;
26 clock-output-names = "ext_gmac";
27 #clock-cells = <0>;
30 vcc_phy: vcc-phy-regulator {
31 compatible = "regulator-fixed";
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H A Dexynos5420-smdk5420.dts1 // SPDX-License-Identifier: GPL-2.0+
9 /dts-v1/;
17 hwid = "smdk5420 TEST A-A 9382";
26 samsung,min-temp = <25>;
27 samsung,max-temp = <125>;
28 samsung,start-warning = <95>;
29 samsung,start-tripping = <105>;
30 samsung,hw-tripping = <110>;
31 samsung,efuse-min-value = <40>;
32 samsung,efuse-value = <55>;
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H A Drk3xxx.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR X11
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 interrupt-parent = <&gic>;
33 compatible = "simple-bus";
34 #address-cells = <1>;
35 #size-cells = <1>;
38 dmac1_s: dma-controller@20018000 {
43 #dma-cells = <1>;
44 arm,pl330-broken-no-flushp;
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H A Drk3288-veyron-jerry.dts1 // SPDX-License-Identifier: GPL-2.0
8 /dts-v1/;
9 #include "rk3288-veyron-chromebook.dtsi"
10 #include "cros-ec-sbs.dtsi"
14 compatible = "google,veyron-jerry-rev7", "google,veyron-jerry-rev6",
15 "google,veyron-jerry-rev5", "google,veyron-jerry-rev4",
16 "google,veyron-jerry-rev3", "google,veyron-jerry",
20 stdout-path = &uart2;
23 panel_regulator: panel-regulator {
24 compatible = "regulator-fixed";
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H A Drk3288-rock2-square.dts2 * This file is dual-licensed: you can use it either under the terms
41 /dts-v1/;
42 #include "rk3288-rock2-som.dtsi"
46 compatible = "radxa,rock2-square", "rockchip,rk3288";
49 stdout-path = "serial2:115200n8";
52 ir: ir-receiver {
53 compatible = "gpio-ir-receiver";
55 pinctrl-names = "default";
56 pinctrl-0 = <&ir_int>;
60 compatible = "simple-audio-card";
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H A Drk3128.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/pinctrl/rockchip.h>
10 #include <dt-bindings/clock/rk3128-cru.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <1>;
42 arm-pmu {
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H A Drk322x.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/pinctrl/rockchip.h>
10 #include <dt-bindings/clock/rk3228-cru.h>
11 #include <dt-bindings/thermal/thermal.h>
14 #address-cells = <1>;
15 #size-cells = <1>;
17 interrupt-parent = <&gic>;
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H A Dexynos54xx.dtsi1 // SPDX-License-Identifier: GPL-2.0+
8 #include "exynos54xx-pinctrl.dtsi"
12 machine-arch-id = <4151>;
45 compatible = "samsung,exynos-adc-v2";
52 #address-cells = <1>;
53 #size-cells = <0>;
54 compatible = "samsung,exynos5-hsi2c";
60 #address-cells = <1>;
61 #size-cells = <0>;
62 compatible = "samsung,exynos5-hsi2c";
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H A Dexynos5800-peach-pi.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * SAMSUNG/GOOGLE Peach-Pit board device tree source
9 /dts-v1/;
14 cpu-model = "Exynos5800";
16 compatible = "google,pit-rev#", "google,pit",
20 google,bad-wake-gpios = <&gpx0 6 GPIO_ACTIVE_HIGH>;
21 hwid = "PIT TEST A-A 7848";
22 lazy-init = <1>;
33 compatible = "pwm-backlight";
35 brightness-levels = <0 100 500 1000 1500 2000 2500 2800>;
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H A Drk3288-phycore-rdk.dts2 * Device tree file for Phytec PCM-947 carrier board
6 * This file is dual-licensed: you can use it either under the terms
45 /dts-v1/;
47 #include <dt-bindings/input/input.h>
48 #include "rk3288-phycore-som.dtsi"
51 model = "Phytec RK3288 PCM-947";
52 compatible = "phytec,rk3288-pcm-947", "phytec,rk3288-phycore-som", "rockchip,rk3288";
55 stdout-path = &uart2;
59 u-boot,dm-pre-reloc;
60 u-boot,boot0 = &emmc;
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/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_display_core.h1 /* SPDX-License-Identifier: MIT */
60 * fills out the pipe-config with the hw state.
179 * if we get a HPD irq from DP and a HPD irq from non-DP
180 * the non-DP HPD could block the workqueue on a mode config
183 * blocked behind the non-DP one.
261 * protects * intel_crtc->wm.active and
262 * crtc_state->wm.need_postvbl_update.
272 /* Top level crtc-ish functions */
365 struct intel_dmc *dmc; member
367 } dmc; member
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/openbmc/linux/drivers/input/touchscreen/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
20 support for the built-in touchscreen.
25 module will be called 88pm860x-ts.
34 and your board-specific setup code includes that in its
51 AD7877 controller, and your board-specific initialization
60 tristate "Analog Devices AD7879-1/AD7889-1 touchscreen interface"
63 the AD7879-1/AD7889-1 controller.
65 You should select a bus connection too.
71 tristate "support I2C bus connection"
75 Say Y here if you have AD7879-1/AD7889-1 hooked to an I2C bus.
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