| /openbmc/linux/drivers/eisa/ |
| H A D | eisa.ids | 6 # Marc Zyngier <maz@wild-wind.fr.eu.org>
10 ABP0510 "Advansys ABP-510 ISA SCSI Host Adapter"
11 ABP0540 "Advansys ABP-540/542 ISA SCSI Host Adapter"
12 ABP7401 "AdvanSys ABP-740/742 EISA Single Channel SCSI Host Adapter"
13 ABP7501 "AdvanSys ABP-750/752 EISA Dual Channel SCSI Host Adapter"
14 ACC1200 "ACCTON EtherCombo-32 Ethernet Adapter"
15 ACC120A "ACCTON EtherCombo-32 Ethernet Adapter"
18 ACE1010 "ACME Super Fast System Board"
21 ACE3030 "ACME Sample VS Board 1"
23 ACE5010 "ACME VDU Video Board"
[all …]
|
| /openbmc/u-boot/arch/arm/mach-rockchip/rk3288/ |
| H A D | Kconfig | 4 bool "Google/Rockchip Veyron-Jerry Chromebook"
7 Jerry is a RK3288-based clamshell device with 2 USB 3.0 ports,
8 HDMI, an 11.9 inch EDP display, micro-SD card, touchpad and
9 WiFi. It includes a Chrome OS EC (Cortex-M3) to provide access to
13 bool "Google/Rockchip Veyron-Mickey Chromebit"
16 Mickey is a small RK3288-based device with one USB 3.0 port, HDMI
23 bool "Google/Rockchip Veyron-Minnie Chromebook"
26 Minnie is a RK3288-based convertible clamshell device with 2 USB 3.0
27 ports, micro HDMI, a 10.1-inch 1280x800 EDP display, micro-SD card,
29 EC (Cortex-M3) to provide access to the keyboard and battery
[all …]
|
| /openbmc/openbmc/meta-facebook/meta-yosemite4/recipes-phosphor/dbus/ |
| H A D | fan-fault-led.bb | 1 SUMMARY = "Fan fault led configurations for meta-yosemite4 machines"
3 LICENSE = "Apache-2.0"
4 LIC_FILES_CHKSUM = "file://${COREBASE}/meta/files/common-licenses/Apache-2.0;md5=89aea4e17d99a7cacd…
7 inherit phosphor-dbus-monitor
15 file://board-0-fan-0.yaml \
16 file://board-0-fan-1.yaml \
17 file://board-0-fan-4.yaml \
18 file://board-0-fan-5.yaml \
19 file://board-0-fan-8.yaml \
20 file://board-0-fan-9.yaml \
[all …]
|
| /openbmc/linux/arch/sh/include/mach-common/mach/ |
| H A D | microdev.h | 1 /* SPDX-License-Identifier: GPL-2.0
3 * linux/include/asm-sh/microdev.h
7 * Definitions for the SuperH SH4-202 MicroDev board.
17 * controller (INTC) on the CPU-board FPGA. should be noted that there
18 * is an INTC on the FPGA, and a separate INTC on the SH4-202 core -
20 * correctly route - unfortunately, they have the same name and
23 #define MICRODEV_FPGA_INTC_BASE 0xa6110000ul /* INTC base address on CPU-board FPGA */
24 …INTENB_REG (MICRODEV_FPGA_INTC_BASE+0ul) /* Interrupt Enable Register on INTC on CPU-board FPGA */
25 …NTDSB_REG (MICRODEV_FPGA_INTC_BASE+8ul) /* Interrupt Disable Register on INTC on CPU-board FPGA */
26 …RODEV_FPGA_INTC_MASK(n) (1ul<<(n)) /* Interrupt mask to enable/disable INTC in CPU-board FPGA */
[all …]
|
| /openbmc/u-boot/doc/device-tree-bindings/memory/ |
| H A D | memory.txt | 3 The memory binding for U-Boot is as in the ePAPR with the following additions:
5 Optional subnodes can be used defining the memory layout for different board
6 ID masks. To match a set of board ids, a board-id node may define match-mask
7 and match-value ints to define a mask to apply to the board id, and the value
9 defaults to -1, meaning that the value must fully match the board id.
13 - #address-cells: should be 1.
14 - #size-cells: should be 0.
18 reg - board ID or mask for this subnode
19 memory-banks - list of memory banks in the same format as normal
23 match-mask - A mask to apply to the board id. This must be accompanied by
[all …]
|
| /openbmc/linux/arch/mips/cavium-octeon/executive/ |
| H A D | cvmx-helper-board.c | 7 * Copyright (c) 2003-2008 Cavium Networks
10 * it under the terms of the GNU General Public License, Version 2, as
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
30 * Helper functions to abstract board specific data about
31 * network ports from the rest of the cvmx-helper files.
36 #include <asm/octeon/cvmx-bootinfo.h>
38 #include <asm/octeon/cvmx-config.h>
40 #include <asm/octeon/cvmx-helper.h>
41 #include <asm/octeon/cvmx-helper-util.h>
[all …]
|
| /openbmc/u-boot/arch/arm/mach-davinci/ |
| H A D | Kconfig | 4 prompt "DaVinci board select"
8 bool "IPAM390 board"
14 bool "DA850 EVM board"
20 bool "EA20 board"
31 bool "Calimain board"
76 int "PLLC0 PLL Post-Divider"
79 Value written to PLLC0 PLL Post-Divider Control Register
88 hex "PLLC0 Divider 2"
91 Value written to PLLC0 Divider 2 register
124 hex "PLLC1 PLL Post-Divider"
[all …]
|
| /openbmc/u-boot/arch/arm/mach-rockchip/rk3399/ |
| H A D | Kconfig | 4 prompt "RK3399 board select"
7 bool "RK3399 evaluation board"
9 RK3399evb is a evaluation board for Rockchp rk3399,
10 with full function and phisical connectors support like type-C ports,
11 usb2.0 host ports, LVDS, JTAG, MAC, SDcard, HDMI, USB-2-serial...
14 bool "Theobroma Systems RK3399-Q7 (Puma)"
16 The RK3399-Q7 (Puma) is a system-on-module (designed and
18 in a Qseven-compatible form-factor (running of a single 5V
19 supply and exposing its external interfaces on a MXM-230
22 Key features of the RK3399-Q7 include:
[all …]
|
| /openbmc/u-boot/board/intel/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0+
14 This is the Intel Bayley Bay Customer Reference Board. It contains an
15 Intel quad-core Atom Processor E3800 with dual-channel DDR3L SODIMM
22 This is the Intel Cherry Hill Customer Reference Board. It is in a
23 mini-ITX form factor containing the Intel Braswell SoC, which has
24 a 64-bit quad-core, single-thread, Intel Atom processor, along with
25 serial console, 10/100/1000 Ethernet, SD-Card, USB 2/3, SATA, PCIe,
29 bool "Cougar Canyon 2"
31 This is the Intel Cougar Canyon 2 Customer Reference Board. It
33 and Panther Point chipset. The board has 4GB RAM, with some other
[all …]
|
| /openbmc/u-boot/arch/sh/ |
| H A D | Kconfig | 26 SH4A has 2 physical memory maps. This use 32bit mode.
27 And this is board specific. Please check your board if you
47 bool "Magic Panel Release 2 board"
59 bool "Data Technology ESPT-GIGA board"
71 bool "ALPHAPROJECT AP-SH4A-4A"
75 bool "Renesas AP-325RXA"
83 bool "Migo-R"
91 bool "Renesas R2D-PLUS"
95 bool "R7780MP board"
130 source "board/alphaproject/ap_sh4a_4a/Kconfig"
[all …]
|
| /openbmc/u-boot/board/gateworks/gw_ventana/ |
| H A D | common.c | 1 // SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/mx6-pins.h>
12 #include <asm/mach-imx/mxc_i2c.h>
46 /* 4-bit microSD on SD2 */
57 /* 8-bit eMMC on SD2/NAND */
560 2
587 2
614 2
641 2
645 IMX_GPIO_NR(2, 9),
[all …]
|
| /openbmc/linux/Documentation/devicetree/bindings/arm/ |
| H A D | fsl.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawnguo@kernel.org>
11 - Li Yang <leoyang.li@nxp.com>
18 - description: i.MX1 based Boards
20 - enum:
21 - armadeus,imx1-apf9328
22 - fsl,imx1ads
23 - const: fsl,imx1
[all …]
|
| /openbmc/linux/arch/sparc/kernel/ |
| H A D | sun4d_irq.c | 1 // SPDX-License-Identifier: GPL-2.0
29 * SBUS interrupts are encodes as a combination of board, level and slot.
38 static unsigned int sun4d_encode_irq(int board, int lvl, int slot) in sun4d_encode_irq() argument
40 return (board + 1) << 5 | (lvl << 2) | slot; in sun4d_encode_irq()
55 /* Specify which cpu handle interrupts from which board.
56 * Index is board - value is cpu.
64 2,
82 /* SBUS interrupts are encoded integers including the board number
92 * 2) For each bus showing interrupt pending from #1, read the
107 sbil = (sbusl << 2); in sun4d_sbus_handler_irq()
[all …]
|
| /openbmc/linux/drivers/comedi/drivers/ |
| H A D | pcl730.c | 1 // SPDX-License-Identifier: GPL-2.0
4 * Driver for Advantech PCL-730 and clones
10 * Description: Advantech PCL-730 (& compatibles)
11 * Devices: [Advantech] PCL-730 (pcl730), PCM-3730 (pcm3730), PCL-725 (pcl725),
12 * PCL-733 (pcl733), PCL-734 (pcl734),
13 * [ADLink] ACL-7130 (acl7130), ACL-7225b (acl7225b),
14 * [ICP] ISO-730 (iso730), P8R8-DIO (p8r8dio), P16R16-DIO (p16r16dio),
15 * [Diamond Systems] OPMM-1616-XT (opmm-1616-xt), PEARL-MM-P (pearl-mm-p),
16 * IR104-PBF (ir104-pbf),
21 * [0] - I/O port base
[all …]
|
| /openbmc/openbmc/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-base/ |
| H A D | 0002-vexpress64-Select-PSCI-RESET-by-default.patch | 9 sysreset-uclass.c instead.
11 Upstream-Status: Pending
12 Signed-off-by: Diego Sueiro <diego.sueiro@arm.com>
13 ---
14 board/armltd/vexpress64/Kconfig | 2 ++
15 board/armltd/vexpress64/vexpress64.c | 5 -----
16 2 files changed, 2 insertions(+), 5 deletions(-)
18 diff --git a/board/armltd/vexpress64/Kconfig b/board/armltd/vexpress64/Kconfig
20 --- a/board/armltd/vexpress64/Kconfig
21 +++ b/board/armltd/vexpress64/Kconfig
[all …]
|
| /openbmc/u-boot/board/freescale/mpc837xemds/ |
| H A D | README | 1 Freescale MPC837xEMDS Board
2 -----------------------------------------
3 1. Board Switches and Jumpers
4 1.0 There are four Dual-In-Line Packages(DIP) Switches on MPC837xEMDS board
11 and some of those signals may be high-bit-number-0 too. Heed
18 SW2[1:6] refers to bits labeled 1 through 6 in order on switch 2.
22 1.1 For the MPC837xEMDS Processor Board
24 First, make sure the board default setting is consistent with the
25 document shipped with your board. Then apply the following setting:
26 SW3[1-8]= 0011_0000 (BOOTSEQ, ROMLOC setting)
[all …]
|
| /openbmc/u-boot/board/freescale/mpc832xemds/ |
| H A D | README | 1 Freescale MPC832XEMDS Board
2 -----------------------------------------
3 1. Board Switches and Jumpers
4 1.0 There are five Dual-In-Line Packages(DIP) Switches on MPC832XE SYS board
11 and some of those signals may be high-bit-number-0 too. Heed
17 SW3 is switch 18 as silk-screened onto the board.
24 1.1 For the MPC832XEMDS PROTO Board
26 First, make sure the board default setting is consistent with the document
27 shipped with your board. Then apply the following setting:
28 SW3[1-8]= 0000_1000 (core PLL setting, core enable)
[all …]
|
| /openbmc/linux/drivers/video/fbdev/ |
| H A D | broadsheetfb.c | 2 * broadsheetfb.c -- FB driver for E-Ink Broadsheet controller
14 * It is intended to be architecture independent. A board specific driver
51 /* table of panel specific parameters to be indexed into by the board drivers */
57 .gdcfg = 2,
81 .gdcfg = 2,
121 par->board->set_ctl(par, BS_WR, 0); in broadsheet_gpio_issue_data()
122 par->board->set_hdb(par, data); in broadsheet_gpio_issue_data()
123 par->board->set_ctl(par, BS_WR, 1); in broadsheet_gpio_issue_data()
128 par->board->set_ctl(par, BS_DC, 0); in broadsheet_gpio_issue_cmd()
134 par->board->wait_for_rdy(par); in broadsheet_gpio_send_command()
[all …]
|
| /openbmc/u-boot/board/boundary/nitrogen6x/ |
| H A D | README.mx6qsabrelite | 1 U-Boot for the Freescale i.MX6q SabreLite board
4 This file contains information for the port of U-Boot to the Freescale
5 i.MX6q SabreLite board.
9 --------
11 To build U-Boot for the SabreLite board:
17 2. Boot from SD card
18 --------------------
22 board will still boot from SPI NOR, but the loader will in turn request the
23 BootROM to load the U-Boot from SD card.
29 This is provided under a open-source 3-clause BSD license.
[all …]
|
| /openbmc/u-boot/board/bosch/shc/ |
| H A D | README | 9 AM335X based board:
13 Enabling the D-Cache
19 2 Jumpers:
21 Jumper 1 Jumper 2 Bootmode
40 $ make -s all
42 -> now you have the MLO and the u-boot.img file, you can put
48 There are a lot of board versions and boot configurations, which
51 ARM architecture --->
52 enable different boot versions for the shc board (enable eMMC) --->
58 enable different board versions for the shc board (C3 Sample board version) --->
[all …]
|
| /openbmc/openbmc/meta-openpower/recipes-phosphor/ipmi/hostboot-inventory-config/ |
| H A D | config.yaml | 6 IPMIFruSection: Board
9 IPMIFruSection: Board
12 IPMIFruSection: Board
15 IPMIFruSection: Board
19 IPMIFruSection: Board
23 IPMIFruSection: Board
24 # Custom Field 2 is EC.
25 IPMIFruProperty: "Custom Field 2"
49 IPMIFruSection: Board
52 IPMIFruSection: Board
[all …]
|
| /openbmc/u-boot/doc/imx/common/ |
| H A D | mxs.txt | 1 Booting U-Boot on a MXS processor
4 This document describes the MXS U-Boot port. This document mostly covers topics
5 related to making the module/board bootable.
8 -----------
14 into the unix command prompt in U-Boot source code root directory.
16 The (=>) introduces a snipped of code that should by typed into U-Boot command
20 --------
23 2) Compiling U-Boot for a MXS based board
24 3) Installation of U-Boot for a MXS based board to SD card
25 4) Installation of U-Boot into NAND flash on a MX28 based board
[all …]
|
| /openbmc/linux/Documentation/devicetree/bindings/clock/ |
| H A D | cirrus,lochnagar.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cirrus Logic Lochnagar Audio Development Board
10 - patches@opensource.cirrus.com
13 Lochnagar is an evaluation and development board for Cirrus Logic
15 Logic devices on mini-cards, as well as allowing connection of various
25 [1] Clock : ../clock/clock-bindings.txt
28 [2] include/dt-bindings/clock/lochnagar.h
36 - cirrus,lochnagar1-clk
[all …]
|
| /openbmc/u-boot/board/freescale/mx6memcal/ |
| H A D | Kconfig | 22 Select this if your board uses UART1 for its' console.
27 Select this if your board uses UART2 for its' console.
53 is done on the i.MX6 Wand board and i.MX6 SabreSD.
69 Say "Y" if you want output formatted for use in non-SPL
70 (DCD-style) configuration files.
80 default 2
81 range 1 2
83 Select the number of chip selects used in your board design
93 Select this if your board design uses DDR3.
98 Select this if your board design uses LPDDR2.
[all …]
|
| /openbmc/openbmc/meta-facebook/meta-yosemite4/recipes-phosphor/dbus/fan-fault-led/ |
| H A D | board-1-fan-2.yaml | 1 - name: board 1 fan 2 current critical alarm path group
5 - meta: PATH
7 - meta: PATH
10 - name: current fan critical alarm property
15 - interface: xyz.openbmc_project.Sensor.Threshold.Critical
18 - interface: xyz.openbmc_project.Sensor.Threshold.Critical
22 - name: board 1 fan 2 critical alarm assert
25 paths: board 1 fan 2 current critical alarm path group
29 - name: board 1 fan 2 critical alarm deassert
32 paths: board 1 fan 2 current critical alarm path group
[all …]
|