| /openbmc/u-boot/include/configs/ |
| H A D | snapper9260.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
32 #define CONFIG_SYS_INIT_SP_ADDR (ATMEL_BASE_SRAM1 + 0x1000 - \
81 /* I2C - Bit-bashed */
83 #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
97 #define I2C_SDA(bit) do { \ argument
98 if (bit) { \
102 at91_set_gpio_value(AT91_PIN_PA23, bit); \
105 #define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTA, 24, bit) argument
120 /* U-Boot memory settings */
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| H A D | ethernut5.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
14 /* The first stage boot loader expects u-boot running at this address. */
32 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SRAM_BASE + CONFIG_SRAM_SIZE - \
43 - CONFIG_SYS_MALLOC_LEN)
45 /* 512kB on-chip NOR flash */
53 /* bootstrap + u-boot + env + linux in dataflash on CS0 */
110 #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
129 #define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTA, 24, bit) argument
130 #define I2C_SDA(bit) at91_set_pio_value(AT91_PIO_PORTA, 23, bit) argument
150 /* Misc. u-boot settings */
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| H A D | vct.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
52 #define CONFIG_SYS_NS16550_REG_SIZE -4
81 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* re-init HCD after CMD_RESET */
108 * For the non-memory-mapped NOR FLASH, we need to define the
111 * U-Boot code, before the NOR FLASH is detected.
145 #define CONFIG_ENV_ADDR (128 << 10) /* after compr. U-Boot image */
153 #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
158 * Software (bit-bang) I2C driver configuration
173 #define I2C_SDA(bit) vct_gpio_set(CONFIG_SYS_GPIO_I2C_SDA, bit) argument
174 #define I2C_SCL(bit) vct_gpio_set(CONFIG_SYS_GPIO_I2C_SCL, bit) argument
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| H A D | MPC8560ADS.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
25 * assume U-Boot is less than 0.5MB
29 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
83 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
86 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
98 #define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */
129 * port-size = 32-bits = BR2[19:20] = 11
149 * 9 columns OR2[19-21] = 010
150 * 13 rows OR2[23-25] = 100
184 * 32KB, 8-bit wide for ADS config reg
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| H A D | M54418TWR.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * Copyright 2010-2012 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
10 * board/config.h - configuration options, board specific
73 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
96 "uboot=u-boot.bin\0" \
110 "u-boot=u-boot.bin\0" \
111 "load=tftp ${loadaddr} ${u-boot};\0" \
124 "u-boot=u-boot.bin\0" \
125 "load=tftp ${loadaddr) ${u-boot}\0" \
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| H A D | MPC8349EMDS.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2006-2010
69 * 32-bit data path mode.
71 * Please note that using this mode for devices with the real density of 64-bit
75 * 128MB); normally this define should be used for devices with real 32-bit
88 * DDRCDR - DDR Control Driver Register
121 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
126 /* set burst length to 8 for 32-bit data path */
130 /* the default burst length is 4 - for 64-bit data path */
150 | BR_PS_16 /* 16 bit port */ \
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| /openbmc/linux/Documentation/devicetree/bindings/spi/ |
| H A D | spi-gpio.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SPI-GPIO
10 - Rob Herring <robh@kernel.org>
13 This represents a group of 3-n GPIO lines used for bit-banged SPI on
17 - $ref: /schemas/spi/spi-controller.yaml#
21 const: spi-gpio
23 sck-gpios:
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| /openbmc/u-boot/doc/ |
| H A D | README.bitbangMII | 1 This patch rewrites the miiphybb ( Bit-banged MII bus driver ) in order to
4 buses are implemented via bit-banging mode.
9 CONFIG_BITBANGMII - Enable the miiphybb driver
10 CONFIG_BITBANGMII_MULTI - Enable the multi bus support
15 MII_INIT - Generic code to enable the MII bus (optional)
16 MDIO_DECLARE - Declaration needed to access to the MDIO pin (optional)
17 MDIO_ACTIVE - Activate the MDIO pin as out pin
18 MDIO_TRISTATE - Activate the MDIO pin as input/tristate pin
19 MDIO_READ - Read the MDIO pin
20 MDIO(v) - Write v on the MDIO pin
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| /openbmc/linux/drivers/misc/eeprom/ |
| H A D | digsy_mtc_eeprom.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 * FIXME: this driver is used on a device-tree probed platform: it
9 * should be defined as a bit-banged SPI device and probed from the device
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| /openbmc/linux/arch/arm/boot/dts/st/ |
| H A D | ste-ux500-samsung-janice.dts | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Devicetree for the Samsung Galaxy S Advance GT-I9070 also known as Janice.
6 /dts-v1/;
7 #include "ste-db8500.dtsi"
8 #include "ste-ab8500.dtsi"
9 #include "ste-dbx5x0-pinctrl.dtsi"
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/leds/common.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
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| H A D | ste-ux500-samsung-gavini.dts | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Devicetree for the Samsung Galaxy Beam GT-I8530 also known as Gavini.
6 /dts-v1/;
7 #include "ste-db8500.dtsi"
8 #include "ste-ab8500.dtsi"
9 #include "ste-dbx5x0-pinctrl.dtsi"
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/leds/common.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
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| H A D | ste-ux500-samsung-codina-tmo.dts | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Devicetree for the Samsung Galaxy Exhibit SGH-T599 also known as Codina-TMO,
4 * the "TMO" shall be read "T-Mobile" as this phone was produced exlusively
5 * for T-Mobile in the United States.
8 * - No CPU speed cap, full ~1GHz rate
9 * - Different power management IC, AB8505
10 * - As AB8505 has a micro USB phy, no TI TSU6111
11 * - Different power routing such as the removal of the external LDO for the
13 * - Using a regulator for the key backlight LED
14 * - Using the Samsung S6D27A1 panel by default
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| H A D | ste-ux500-samsung-codina.dts | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Devicetree for the Samsung Galaxy Ace 2 GT-I8160 also known as Codina.
11 * The Samsung tree further talks about GT-I8160P and GT-I8160chn (China).
12 * The GT-I8160 plain is known as the "europe" variant.
13 * The GT-I8160P is the CDMA version and it appears to not use the ST
15 * The GT-I8160chn appears to be the same as the europe variant.
17 * There is also the Codina-TMO, Samsung SGH-T599, which has its own device
21 /dts-v1/;
22 #include "ste-db8500.dtsi"
23 #include "ste-ab8500.dtsi"
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| /openbmc/u-boot/drivers/net/phy/ |
| H A D | Kconfig | 3 bool "Bit-banged ethernet MII management channel support"
185 bool "Ethernet PHY RTL8211x: force 1000BASE-T master mode"
188 Force master mode for 1000BASE-T on RTl8211x PHYs (except for RTL8211F).
221 bool "Fixed-Link PHY"
224 Fixed PHY is used for having a 'fixed-link' to another MAC with a direct
227 on, the link is always up with fixed speed and fixed duplex-setting.
228 More information: doc/device-tree-bindings/net/fixed-link.txt
231 bool "NC-SI based PHY"
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| H A D | miiphybb.c | 1 // SPDX-License-Identifier: GPL-2.0+
4 * Luigi 'Comio' Mantellini <luigi.mantellini@idf-hit.com>
11 * This provides a bit-banged interface to the ethernet MII management
115 BB_MII_RELOCATE(bb_miiphy_buses[i].init, gd->reloc_off); in bb_miiphy_init()
116 BB_MII_RELOCATE(bb_miiphy_buses[i].mdio_active, gd->reloc_off); in bb_miiphy_init()
117 BB_MII_RELOCATE(bb_miiphy_buses[i].mdio_tristate, gd->reloc_off); in bb_miiphy_init()
118 BB_MII_RELOCATE(bb_miiphy_buses[i].set_mdio, gd->reloc_off); in bb_miiphy_init()
119 BB_MII_RELOCATE(bb_miiphy_buses[i].get_mdio, gd->reloc_off); in bb_miiphy_init()
120 BB_MII_RELOCATE(bb_miiphy_buses[i].set_mdc, gd->reloc_off); in bb_miiphy_init()
121 BB_MII_RELOCATE(bb_miiphy_buses[i].delay, gd->reloc_off); in bb_miiphy_init()
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| /openbmc/u-boot/include/configs/km/ |
| H A D | km_arm.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
10 * (C) Copyright 2010-2011
16 * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html
33 #include "keymile-common.h"
43 #define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */
44 #define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */
46 /* pseudo-non volatile RAM [hex] */
61 "u-boot="CONFIG_HOSTNAME "/u-boot.kwb\0" \
78 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
134 #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
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| /openbmc/u-boot/board/freescale/m53017evb/ |
| H A D | README | 4 TsiChung Liew(Tsi-Chung.Liew@freescale.com)
12 - board/freescale/m53017evb/m53017evb.c Dram setup
13 - board/freescale/m53017evb/mii.c Mii access
14 - board/freescale/m53017evb/Makefile Makefile
15 - board/freescale/m53017evb/config.mk config make
16 - board/freescale/m53017evb/u-boot.lds Linker description
18 - arch/m68k/cpu/mcf532x/cpu.c cpu specific code
19 - arch/m68k/cpu/mcf532x/cpu_init.c FBCS, Mux pins, icache and RTC extra regs
20 - arch/m68k/cpu/mcf532x/interrupts.c cpu specific interrupt support
21 - arch/m68k/cpu/mcf532x/speed.c system, flexbus, and cpu clock
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| /openbmc/u-boot/board/freescale/m52277evb/ |
| H A D | README | 4 TsiChung Liew(Tsi-Chung.Liew@freescale.com)
12 - board/freescale/m52277evb/m52277evb.c Dram setup
13 - board/freescale/m52277evb/Makefile Makefile
14 - board/freescale/m52277evb/config.mk config make
15 - board/freescale/m52277evb/u-boot.lds Linker description
17 - arch/m68k/cpu/mcf5227x/cpu.c cpu specific code
18 - arch/m68k/cpu/mcf5227x/cpu_init.c FBCS, Mux pins, icache and RTC extra regs
19 - arch/m68k/cpu/mcf5227x/interrupts.c cpu specific interrupt support
20 - arch/m68k/cpu/mcf5227x/speed.c system, flexbus, and cpu clock
21 - arch/m68k/cpu/mcf5227x/Makefile Makefile
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| /openbmc/u-boot/board/freescale/m547xevb/ |
| H A D | README | 4 TsiChung Liew(Tsi-Chung.Liew@freescale.com)
12 - board/freescale/m547xevb/m547xevb.c Dram setup, IDE pre init, and PCI init
13 - board/freescale/m547xevb/mii.c MII init
14 - board/freescale/m547xevb/Makefile Makefile
15 - board/freescale/m547xevb/config.mk config make
16 - board/freescale/m547xevb/u-boot.lds Linker description
18 - arch/m68k/cpu/mcf547x_8x/cpu.c cpu specific code
19 - arch/m68k/cpu/mcf547x_8x/cpu_init.c Flexbus ChipSelect, Mux pins setup, icache and RTC extra regs
20 - arch/m68k/cpu/mcf547x_8x/interrupts.c cpu specific interrupt support
21 - arch/m68k/cpu/mcf547x_8x/slicetimer.c Timer support
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| /openbmc/linux/drivers/bus/ |
| H A D | ts-nbus.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * NBUS driver for TS-4600 based boards
5 * Copyright (c) 2016 - Savoir-faire Linux
8 * This driver implements a GPIOs bit-banged bus, called the NBUS by Technologic
10 * TS-4600 SoM.
21 #include <linux/ts-nbus.h>
45 ts_nbus->data = devm_gpiod_get_array(&pdev->dev, "ts,data", in ts_nbus_init_pdata()
47 if (IS_ERR(ts_nbus->data)) { in ts_nbus_init_pdata()
48 dev_err(&pdev->dev, "failed to retrieve ts,data-gpio from dts\n"); in ts_nbus_init_pdata()
49 return PTR_ERR(ts_nbus->data); in ts_nbus_init_pdata()
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| /openbmc/linux/Documentation/devicetree/bindings/net/dsa/ |
| H A D | realtek.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: dsa.yaml#/$defs/ethernet-ports
13 - Linus Walleij <linus.walleij@linaro.org>
20 The SMI "Simple Management Interface" is a two-wire protocol using
21 bit-banged GPIO that while it reuses the MDIO lines MCK and MDIO does
23 SMI-based Realtek devices. The realtek-smi driver is a platform driver
26 The MDIO-connected switches use MDIO protocol to access their registers.
27 The realtek-mdio driver is an MDIO driver and it must be inserted inside
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| /openbmc/u-boot/doc/device-tree-bindings/gpio/ |
| H A D | gpio.txt | 5 -----------------
8 properties, each containing a 'gpio-list':
10 gpio-list ::= <single-gpio> [gpio-list]
11 single-gpio ::= <gpio-phandle> <gpio-specifier>
12 gpio-phandle : phandle to gpio controller node
13 gpio-specifier : Array of #gpio-cells specifying specific gpio
16 GPIO properties should be named "[<name>-]gpios", with <name> being the purpose
17 of this GPIO for the device. While a non-existent <name> is considered valid
31 and bit-banged data signals:
34 gpio-controller
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| /openbmc/linux/Documentation/devicetree/bindings/gpio/ |
| H A D | gpio.txt | 5 -----------------
7 GPIO properties should be named "[<name>-]gpios", with <name> being the purpose
8 of this GPIO for the device. While a non-existent <name> is considered valid
10 for new bindings. Also, GPIO properties named "[<name>-]gpio" are valid and old
24 and bit-banged data signals:
27 gpio-controller;
28 #gpio-cells = <2>;
32 data-gpios = <&gpio1 12 0>,
44 recommended to use the two-cell approach.
48 include/dt-bindings/gpio/gpio.h whenever possible:
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| /openbmc/linux/drivers/spi/ |
| H A D | spi-gpio.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
25 * platform_device->driver_data ... points to spi_gpio
27 * spi->controller_state ... reserved for bitbang framework code
29 * spi->controller->dev.driver_data ... points to spi_gpio->bitbang
40 /*----------------------------------------------------------------------*/
44 * per transferred bit can make performance a problem, this code
47 * - The slow generic way: set up platform_data to hold the GPIO
51 * - The quicker inlined way: only helps with platform GPIO code
62 * #include "spi-gpio.c"
72 /*----------------------------------------------------------------------*/
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| /openbmc/u-boot/board/freescale/m5373evb/ |
| H A D | README | 4 TsiChung Liew(Tsi-Chung.Liew@freescale.com)
12 - board/freescale/m5373evb/m5373evb.c Dram setup
13 - board/freescale/m5373evb/mii.c Mii access
14 - board/freescale/m5373evb/Makefile Makefile
15 - board/freescale/m5373evb/config.mk config make
16 - board/freescale/m5373evb/u-boot.lds Linker description
18 - arch/m68k/cpu/mcf532x/cpu.c cpu specific code
19 - arch/m68k/cpu/mcf532x/cpu_init.c FBCS, Mux pins, icache and RTC extra regs
20 - arch/m68k/cpu/mcf532x/interrupts.c cpu specific interrupt support
21 - arch/m68k/cpu/mcf532x/speed.c system, pci, flexbus, and cpu clock
[all …]
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