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/openbmc/qemu/include/hw/intc/
H A Darmv7m_nvic.h46 * exceptions are banked between security states (ie there exists both
49 * The rest (including all the external exceptions) are not banked, though
51 * We store the secure exception state in sec_vectors[] for the banked
54 * Entries in sec_vectors[] for non-banked exception numbers are unused.
57 /* The PRIGROUP field in AIRCR is banked */
72 /* true if vectpending is a banked secure exception, ie it is in
91 * @secure: false for non-banked exceptions or for the nonsecure
92 * version of a banked exception, true for the secure version of a banked
97 * of architecturally banked exceptions.
104 * @secure: false for non-banked exceptions or for the nonsecure
[all …]
H A Darm_gic_common.h55 /* The enable bits are only banked for per-cpu interrupts. */
78 /* GICD_CTLR; for a GIC with the security extensions the NS banked version
79 * of this register is just an alias of bit 1 of the S banked version.
82 /* GICC_CTLR; again, the NS banked version is just aliases of bits of
83 * the S banked register, so our state only needs to store the S version.
H A Darm_gicv3_common.h91 * (where the latter two are exposed as a single banked system register).
111 /* ICC_CTLR_EL1, GICD_STATUSR and GICR_STATUSR are banked but not
249 /* for a GIC with the security extensions the NS banked version of this
250 * register is just an alias of bit 1 of the S banked version.
/openbmc/linux/Documentation/arch/sh/
H A Dregister-banks.rst11 bank (selected by SR.RB, only r0 ... r7 are banked), whereas other families
17 In the case of this type of banking, banked registers are mapped directly to
19 can still be used to reference the banked registers (as r0_bank ... r7_bank)
21 in mind when writing code that utilizes these banked registers, for obvious
/openbmc/qemu/hw/intc/
H A Darmv7m_nvic.c152 * are banked (and thus have state in sec_vectors[]) in exc_is_banked()
173 /* Return true if this non-banked exception targets Secure state. */ in exc_targets_secure()
182 /* Function shouldn't be called for banked exceptions. */ in exc_targets_secure()
239 * - lowest exception number; if both the same (ie banked) then in nvic_recompute_state_secure()
432 * secure indicates the bank to use for banked exceptions (we assert if
433 * we are passed secure=true for a non-banked exception).
453 * secure indicates the bank to use for banked exceptions (we assert if
454 * we are passed secure=true for a non-banked exception).
497 * @secure: false for non-banked exceptions or for the nonsecure
498 * version of a banked exception, true for the secure version of a banked
[all …]
/openbmc/u-boot/arch/arm/mach-omap2/omap3/
H A Dboard.c384 /* L2 Cache Auxiliary Control Register is not banked */ in v7_arch_cp15_set_l2aux_ctrl()
390 /* Write ACR - affects secure banked bits */ in v7_arch_cp15_set_acr()
396 /* Write ACR - affects non-secure banked bits - some erratas need it */ in v7_arch_cp15_set_acr()
433 * On some revisions L2EN bit is banked on some revisions it's not in v7_outer_cache_enable()
434 * No harm in setting both banked bits(in fact this is required in v7_outer_cache_enable()
444 * On some revisions L2EN bit is banked on some revisions it's not in omap3_outer_cache_disable()
445 * No harm in clearing both banked bits(in fact this is required in omap3_outer_cache_disable()
/openbmc/linux/tools/arch/arm/include/uapi/asm/
H A Dkvm.h156 * registers that are banked by security. This is 1 for the secure banked
157 * register, and 0 for the nonsecure banked register or if the register is
158 * not banked by security.
/openbmc/qemu/linux-headers/asm-arm/
H A Dkvm.h156 * registers that are banked by security. This is 1 for the secure banked
157 * register, and 0 for the nonsecure banked register or if the register is
158 * not banked by security.
/openbmc/qemu/include/hw/timer/
H A Da9gtimer.h63 uint32_t control; /* only per cpu banked bits valid */
87 uint32_t control; /* only non per cpu banked bits valid */
/openbmc/linux/drivers/i2c/
H A Di2c-stub.c44 /* Some chips have banked register ranges */
56 MODULE_PARM_DESC(bank_start, "First banked register");
60 MODULE_PARM_DESC(bank_end, "Last banked register");
214 * We ignore banks here, because banked chips don't use I2C in stub_xfer()
383 /* Allocate extra memory for banked register ranges */ in i2c_stub_init()
/openbmc/linux/drivers/clocksource/
H A Darm_global_timer.c30 #define GT_CONTROL_TIMER_ENABLE BIT(0) /* this bit is NOT banked */
31 #define GT_CONTROL_COMP_ENABLE BIT(1) /* banked */
32 #define GT_CONTROL_IRQ_ENABLE BIT(2) /* banked */
33 #define GT_CONTROL_AUTO_INC BIT(3) /* banked */
/openbmc/linux/arch/arm/mach-omap2/
H A Domap-headsmp.S111 * banked version is now composed of 2 bits:
114 * The Non-Secure banked register has not changed
H A Domap-smp.c212 * banked version is now composed of 2 bits: in omap4_boot_secondary()
215 * The Non-Secure banked register has not changed in omap4_boot_secondary()
/openbmc/linux/Documentation/devicetree/bindings/gpio/
H A Dgpio-davinci.yaml47 The interrupts are specified as per the interrupt parent. Only banked
49 banked then provide list of interrupts corresponding to each bank, else
/openbmc/linux/drivers/clk/qcom/
H A Dclk-rcg.h105 * @mn: mn counter (banked)
106 * @s: source selector (banked)
/openbmc/linux/drivers/nvmem/
H A Dimx-ocotp.c359 * In banked/i.MX7 mode the OTP register bank goes into waddr in imx_ocotp_write()
368 * Non-banked i.MX6 mode. in imx_ocotp_write()
399 * Note: on i.MX7 there are four data fields to write for banked write in imx_ocotp_write()
405 /* Banked/i.MX7 mode */ in imx_ocotp_write()
433 /* Non-banked i.MX6 mode */ in imx_ocotp_write()
/openbmc/qemu/target/arm/
H A Dcpu-qom.h48 /* For M profile, some registers are banked secure vs non-secure;
/openbmc/linux/arch/sh/
H A DKconfig.cpu86 accomplishing what is taken care of by the banked registers.
/openbmc/linux/Documentation/i2c/
H A Di2c-stub.rst57 select the active bank, as well as the range of banked registers.
/openbmc/linux/drivers/leds/
H A Dleds-lp50xx.c282 * @num_of_banked_leds: holds the number of banked LEDs
417 dev_err(priv->dev, "Cannot setup banked LEDs\n"); in lp50xx_probe_leds()
479 * banked which also is presented as 3 LEDs. in lp50xx_probe_dt()
/openbmc/linux/Documentation/arch/arm/
H A Dsetup.rst23 the memory is banked, then this should contain the total number
/openbmc/linux/drivers/gpio/
H A Dgpio-davinci.c220 * interrupts is equal to number of gpios else all are banked so in davinci_gpio_probe()
540 * banked IRQs. Having GPIOs in the first GPIO bank use direct in davinci_gpio_irq_setup()
541 * IRQs, while the others use banked IRQs, would need some setup in davinci_gpio_irq_setup()
/openbmc/linux/drivers/irqchip/
H A Dirq-sun6i-r.c35 * ^ bits 16-18 are direct IRQs for peripherals with banked interrupts, such as
38 * The H6 variant adds two more (banked) direct IRQs and implements the full
H A Dirq-gic-common.c131 * Deal with the banked PPI and SGI interrupts - disable all in gic_cpu_config()
/openbmc/qemu/hw/arm/
H A Darmv7m.c387 * banked version of all of these. in armv7m_realize()
404 * Some registers within this space are banked between security states. in armv7m_realize()
414 * generally code determining which banked register to use should in armv7m_realize()

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