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/openbmc/linux/drivers/net/ethernet/xilinx/
H A Dxilinx_axienet.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Definitions for Xilinx Axi Ethernet device driver.
6 * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
72 /* Axi DMA Register definitions */
144 /* Axi Ethernet registers definition */
147 #define XAE_IFGP_OFFSET 0x00000008 /* Tx Inter-frame gap adjustment*/
180 /* Bit Masks for Axi Ethernet RAF register */
199 /* Bit Masks for Axi Ethernet TPF and IFGP registers */
201 /* Transmit inter-frame gap adjustment value */
204 /* Bit Masks for Axi Ethernet IS, IE and IP registers, Same masks apply
[all …]
/openbmc/linux/arch/arc/plat-axs10x/
H A Daxs10x.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
11 #include <asm/asm-offsets.h>
33 * --------------------- in axs10x_enable_gpio_intc_wire()
34 * | snps,arc700-intc | in axs10x_enable_gpio_intc_wire()
35 * --------------------- in axs10x_enable_gpio_intc_wire()
37 * ------------------- ------------------- in axs10x_enable_gpio_intc_wire()
38 * | snps,dw-apb-gpio | | snps,dw-apb-gpio | in axs10x_enable_gpio_intc_wire()
39 * ------------------- ------------------- in axs10x_enable_gpio_intc_wire()
43 * ------------------------ in axs10x_enable_gpio_intc_wire()
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/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dxlnx,axi-ethernet.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/xlnx,axi-ethernet.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: AXI 1G/2.5G Ethernet Subsystem
10 Also called AXI 1G/2.5G Ethernet Subsystem, the xilinx axi ethernet IP core
16 Management configuration is done through the AXI interface, while payload is
17 sent and received through means of an AXI DMA controller. This driver
18 includes the DMA driver code, so this driver is incompatible with AXI DMA
22 - Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
[all …]
/openbmc/linux/drivers/clk/baikal-t1/
H A Dclk-ccu-div.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * Baikal-T1 CCU Dividers clock driver
12 #define pr_fmt(fmt) "bt1-ccu-div: " fmt
18 #include <linux/clk-provider.h>
19 #include <linux/reset-controller.h>
26 #include <dt-bindings/clock/bt1-ccu.h>
28 #include "ccu-div.h"
29 #include "ccu-rst.h"
62 .base = _base, \
74 .base = _base, \
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/openbmc/linux/Documentation/devicetree/bindings/display/imx/
H A Dfsl-imx-drm.txt8 - compatible: Should be "fsl,imx-display-subsystem"
9 - ports: Should contain a list of phandles pointing to display interface ports
14 display-subsystem {
15 compatible = "fsl,imx-display-subsystem";
24 - compatible: Should be "fsl,<chip>-ipu" where <chip> is one of
25 - imx51
26 - imx53
27 - imx6q
28 - imx6qp
29 - reg: should be register base and length as documented in the
[all …]
H A Dnxp,imx8mq-dcss.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/imx/nxp,imx8mq-dcss.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Laurentiu Palcu <laurentiu.palcu@nxp.com>
17 2.2) or MIPI-DSI. The DCSS is intended to support up to 4kp60 displays. HDR10
23 const: nxp,imx8mq-dcss
27 - description: DCSS base address and size, up to IRQ steer start
28 - description: DCSS BLKCTL base address and size
32 - description: Context loader completion and error interrupt
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/openbmc/linux/sound/soc/adi/
H A Daxi-spdif.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012-2013, Analog Devices Inc.
4 * Author: Lars-Peter Clausen <lars@metafoo.de>
66 return -EINVAL; in axi_spdif_trigger()
69 regmap_update_bits(spdif->regmap, AXI_SPDIF_REG_CTRL, in axi_spdif_trigger()
97 clkdiv = DIV_ROUND_CLOSEST(clk_get_rate(spdif->clk_ref), in axi_spdif_hw_params()
98 rate * 64 * 2) - 1; in axi_spdif_hw_params()
101 regmap_write(spdif->regmap, AXI_SPDIF_REG_STAT, stat); in axi_spdif_hw_params()
102 regmap_update_bits(spdif->regmap, AXI_SPDIF_REG_CTRL, in axi_spdif_hw_params()
112 snd_soc_dai_init_dma_data(dai, &spdif->dma_data, NULL); in axi_spdif_dai_probe()
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H A Daxi-i2s.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012-2013, Analog Devices Inc.
4 * Author: Lars-Peter Clausen <lars@metafoo.de>
63 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) in axi_i2s_trigger()
80 return -EINVAL; in axi_i2s_trigger()
83 regmap_update_bits(i2s->regmap, AXI_I2S_REG_CTRL, mask, val); in axi_i2s_trigger()
97 word_size = AXI_I2S_BITS_PER_FRAME / 2 - 1; in axi_i2s_hw_params()
98 bclk_div = DIV_ROUND_UP(clk_get_rate(i2s->clk_ref), bclk_rate) / 2 - 1; in axi_i2s_hw_params()
100 regmap_write(i2s->regmap, AXI_I2S_REG_CLK_CTRL, (word_size << 16) | in axi_i2s_hw_params()
113 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) in axi_i2s_startup()
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/openbmc/linux/drivers/iio/adc/
H A Dadi-axi-adc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Analog Devices Generic AXI ADC IP core
6 * Copyright 2012-2020 Analog Devices Inc.
21 #include <linux/fpga/adi-axi-common.h>
24 #include <linux/iio/buffer-dmaengine.h>
69 ret = regmap_set_bits(st->regmap, ADI_AXI_REG_RSTN, in axi_adc_enable()
75 return regmap_set_bits(st->regmap, ADI_AXI_REG_RSTN, in axi_adc_enable()
83 regmap_write(st->regmap, ADI_AXI_REG_RSTN, 0); in axi_adc_disable()
92 if (!data->enable) in axi_adc_data_format_set()
93 return regmap_clear_bits(st->regmap, in axi_adc_data_format_set()
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/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Drockchip,rk3399-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip AXI PCIe Root Port Bridge Host
10 - Shawn Lin <shawn.lin@rock-chips.com>
13 - $ref: /schemas/pci/pci-bus.yaml#
14 - $ref: rockchip,rk3399-pcie-common.yaml#
18 const: rockchip,rk3399-pcie
22 reg-names:
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H A Dbrcm,iproc-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/brcm,iproc-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ray Jui <ray.jui@broadcom.com>
11 - Scott Branden <scott.branden@broadcom.com>
14 - $ref: /schemas/pci/pci-bus.yaml#
19 - enum:
22 - brcm,iproc-pcie
23 # for the second generation of PAXB-based controllers, used in
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/openbmc/linux/drivers/clk/microchip/
H A Dclk-mpfs.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2020-2022 Microchip Technology Inc. All rights reserved.
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/microchip,mpfs-clock.h>
35 void __iomem *base; member
41 void __iomem *base; member
99 void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; in mpfs_clk_msspll_recalc_rate()
100 void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR; in mpfs_clk_msspll_recalc_rate()
101 void __iomem *postdiv_addr = msspll_hw->base + REG_MSSPLL_POSTDIV_CR; in mpfs_clk_msspll_recalc_rate()
117 void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; in mpfs_clk_msspll_round_rate()
[all …]
/openbmc/linux/drivers/pci/controller/cadence/
H A Dpcie-cadence.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
11 #include <linux/pci-epf.h>
117 (((aperture) - 2) << ((bar) * 8))
144 /* Region r Outbound AXI to PCIe Address Translation Register 0 */
149 (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK)
157 /* Region r Outbound AXI to PCIe Address Translation Register 1 */
184 /* Region r AXI Region Base Address Register 0 */
189 (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK)
191 /* Region r AXI Region Base Address Register 1 */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Dadi,axi-spi-engine.txt1 Analog Devices AXI SPI Engine controller Device Tree Bindings
4 - compatible : Must be "adi,axi-spi-engine-1.00.a""
5 - reg : Physical base address and size of the register map.
6 - interrupts : Property with a value describing the interrupt
8 - clock-names : List of input clock names - "s_axi_aclk", "spi_clk"
9 - clocks : Clock phandles and specifiers (See clock bindings for
10 details on clock-names and clocks).
11 - #address-cells : Must be <1>
12 - #size-cells : Must be <0>
16 master. They follow the generic SPI bindings as outlined in spi-bus.txt.
[all …]
/openbmc/linux/Documentation/devicetree/bindings/ata/
H A Dahci-mtk.txt4 - compatible : Must be "mediatek,<chip>-ahci", "mediatek,mtk-ahci".
5 When using "mediatek,mtk-ahci" compatible strings, you
7 - "mediatek,mt7622-ahci"
8 - reg : Physical base addresses and length of register sets.
9 - interrupts : Interrupt associated with the SATA device.
10 - interrupt-names : Associated name must be: "hostc".
11 - clocks : A list of phandle and clock specifier pairs, one for each
12 entry in clock-names.
13 - clock-names : Associated names must be: "ahb", "axi", "asic", "rbc", "pm".
14 - phys : A phandle and PHY specifier pair for the PHY port.
[all …]
/openbmc/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac1000_dma.c1 // SPDX-License-Identifier: GPL-2.0-only
3 This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
9 Copyright (C) 2007-2009 STMicroelectronics Ltd
19 static void dwmac1000_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi) in dwmac1000_dma_axi() argument
24 pr_info("dwmac1000: Master AXI performs %s burst length\n", in dwmac1000_dma_axi()
27 if (axi->axi_lpi_en) in dwmac1000_dma_axi()
29 if (axi->axi_xit_frm) in dwmac1000_dma_axi()
33 value |= (axi->axi_wr_osr_lmt & DMA_AXI_WR_OSR_LMT_MASK) << in dwmac1000_dma_axi()
37 value |= (axi->axi_rd_osr_lmt & DMA_AXI_RD_OSR_LMT_MASK) << in dwmac1000_dma_axi()
40 /* Depending on the UNDEF bit the Master AXI will perform any burst in dwmac1000_dma_axi()
[all …]
H A Dstmmac_pci.c1 // SPDX-License-Identifier: GPL-2.0-only
5 Copyright (C) 2011-2012 Vayavya Labs Pvt Ltd
12 #include <linux/clk-provider.h>
24 plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */ in common_default_data()
25 plat->has_gmac = 1; in common_default_data()
26 plat->force_sf_dma_mode = 1; in common_default_data()
28 plat->mdio_bus_data->needs_reset = true; in common_default_data()
31 plat->multicast_filter_bins = HASH_TABLE_SIZE; in common_default_data()
34 plat->unicast_filter_entries = 1; in common_default_data()
37 plat->maxmtu = JUMBO_LEN; in common_default_data()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/media/
H A Dmarvell,mmp2-ccic.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/media/marvell,mmp2-ccic.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Lubomir Rintel <lkundrak@v3.sk>
15 pattern: '^camera@[a-f0-9]+$'
18 const: marvell,mmp2-ccic
26 power-domains:
30 $ref: /schemas/graph.yaml#/$defs/port-base
35 $ref: video-interfaces.yaml#
[all …]
/openbmc/linux/drivers/clk/imx/
H A Dclk-imx6sll.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2017-2018 NXP.
7 #include <dt-bindings/clock/imx6sll-clock.h>
10 #include <linux/clk-provider.h>
82 void __iomem *base; in imx6sll_clocks_init() local
89 clk_hw_data->num = IMX6SLL_CLK_END; in imx6sll_clocks_init()
90 hws = clk_hw_data->hws; in imx6sll_clocks_init()
101 np = of_find_compatible_node(NULL, NULL, "fsl,imx6sll-anatop"); in imx6sll_clocks_init()
102 base = of_iomap(np, 0); in imx6sll_clocks_init()
104 WARN_ON(!base); in imx6sll_clocks_init()
[all …]
H A Dclk-imx6q.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2011-2013 Freescale Semiconductor, Inc.
12 #include <linux/clk-provider.h>
15 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
20 #include <dt-bindings/clock/imx6qdl-clock.h>
33 static const char *gpu_axi_sels[] = { "axi", "ahb", };
34 static const char *pre_axi_sels[] = { "axi", "ahb", };
35 static const char *gpu2d_core_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m",…
51 static const char *pcie_axi_sels[] = { "axi", "ahb", };
56 static const char *eim_sels[] = { "pll2_pfd2_396m", "pll3_usb_otg", "axi", "pll2_pfd0_352m", };
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H A Dclk-imx6ul.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <dt-bindings/clock/imx6ul-clock.h>
9 #include <linux/clk-provider.h>
13 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
43 static const char *eim_slow_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd2_396m", "pll3_pfd0_720m", …
64 static const char *cko1_sels[] = { "dummy", "dummy", "dummy", "dummy", "dummy", "axi", "enfc", "dum…
131 void __iomem *base; in imx6ul_clocks_init() local
138 clk_hw_data->num = IMX6UL_CLK_END; in imx6ul_clocks_init()
139 hws = clk_hw_data->hws; in imx6ul_clocks_init()
150 np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-anatop"); in imx6ul_clocks_init()
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/openbmc/linux/drivers/clk/
H A Dclk-axi-clkgen.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * AXI clkgen driver
5 * Copyright 2012-2013 Analog Devices Inc.
6 * Author: Lars-Peter Clausen <lars@metafoo.de>
11 #include <linux/clk-provider.h>
58 void __iomem *base; member
144 d_min = max_t(unsigned long, DIV_ROUND_UP(fin, limits->fpfd_max), 1); in axi_clkgen_calc_params()
145 d_max = min_t(unsigned long, fin / limits->fpfd_min, 80); in axi_clkgen_calc_params()
148 fvco_min_fract = limits->fvco_min << fract_shift; in axi_clkgen_calc_params()
149 fvco_max_fract = limits->fvco_max << fract_shift; in axi_clkgen_calc_params()
[all …]
/openbmc/linux/drivers/hwtracing/coresight/
H A Dcoresight-catu.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 #include "coresight-priv.h"
13 /* Register offset from base */
41 * AXI - ARPROT bits:
42 * See AMBA AXI & ACE Protocol specification (ARM IHI 0022E)
45 * Bit 0: 0 - Unprivileged access, 1 - Privileged access
46 * Bit 1: 0 - Secure access, 1 - Non-secure access.
47 * Bit 2: 0 - Data access, 1 - instruction access.
64 void __iomem *base; member
73 return csdev_access_relaxed_read32(&drvdata->csdev->access, offset); \
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/openbmc/linux/drivers/media/platform/samsung/s5p-g2d/
H A Dg2d-regs.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Samsung S5P G2D - 2D Graphics Accelerator Driver
14 #define AXI_ID_MODE_REG 0x0014 /* AXI Read ID Mode reg */
16 #define AXI_MODE_REG 0x001C /* AXI Mode reg */
29 #define SRC_BASE_ADDR_REG 0x0304 /* Src Image Base Address reg */
40 #define DST_BASE_ADDR_REG 0x0404 /* Dest Image Base Address reg */
47 #define PAT_BASE_ADDR_REG 0x0500 /* Pattern Image Base Address reg */
54 #define MASK_BASE_ADDR_REG 0x0520 /* Mask Base Address reg */
/openbmc/linux/drivers/gpu/drm/mxsfb/
H A Dlcdif_drv.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/dma-mapping.h>
49 struct device *dev = lcdif->drm->dev; in lcdif_attach_bridge()
54 for_each_endpoint_of_node(dev->of_node, ep) { in lcdif_attach_bridge()
73 bridge = devm_drm_of_get_bridge(dev, dev->of_node, 0, of_ep.id); in lcdif_attach_bridge()
86 return -ENOMEM; in lcdif_attach_bridge()
89 encoder->possible_crtcs = drm_crtc_mask(&lcdif->crtc); in lcdif_attach_bridge()
90 ret = drm_encoder_init(lcdif->drm, encoder, &lcdif_encoder_funcs, in lcdif_attach_bridge()
114 struct lcdif_drm_private *lcdif = drm->dev_private; in lcdif_irq_handler()
117 stat = readl(lcdif->base + LCDC_V8_INT_STATUS_D0); in lcdif_irq_handler()
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