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/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Daspeed,sdhci.yaml1 # SPDX-License-Identifier: GPL-2.0-or-later
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Andrew Jeffery <andrew@aj.id.au>
12 - Ryan Chen <ryanchen.aspeed@gmail.com>
26 - aspeed,ast2400-sd-controller
27 - aspeed,ast2500-sd-controller
28 - aspeed,ast2600-sd-controller
32 "#address-cells":
34 "#size-cells":
[all …]
H A Dbrcm,iproc-sdhci.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/brcm,iproc-sdhci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ray Jui <ray.jui@broadcom.com>
11 - Scott Branden <scott.branden@broadcom.com>
12 - Nicolas Saenz Julienne <nsaenz@kernel.org>
15 - $ref: mmc-controller.yaml#
20 - brcm,bcm2835-sdhci
21 - brcm,bcm2711-emmc2
[all …]
H A Dbrcm,sdhci-brcmstb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/brcm,sdhci-brcmstb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Al Cooper <alcooperx@gmail.com>
11 - Florian Fainelli <f.fainelli@gmail.com>
16 - items:
17 - enum:
18 - brcm,bcm7216-sdhci
19 - const: brcm,bcm7445-sdhci
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H A Dfsl-esdhc.txt7 by mmc.txt and the properties used by the sdhci-esdhc driver.
10 - compatible : should be "fsl,esdhc", or "fsl,<chip>-esdhc".
12 "fsl,mpc8536-esdhc"
13 "fsl,mpc8378-esdhc"
14 "fsl,p2020-esdhc"
15 "fsl,p4080-esdhc"
16 "fsl,t1040-esdhc"
17 "fsl,t4240-esdhc"
19 "fsl,ls1012a-esdhc"
20 "fsl,ls1028a-esdhc"
[all …]
/openbmc/qemu/include/hw/sd/
H A Dsdhci.h8 * Based on MMC controller for Samsung S5PC1xx-based board emulation
60 uint32_t rspreg[4]; /* Response Registers 0-3 */
75 uint16_t acmd12errsts; /* Auto CMD12 error status register */
80 /* Read-only registers */
90 /* Buffer Data Port Register - virtual access point to R and W buffers */
91 /* Software Reset Register - always reads as 0 */
92 /* Force Event Auto CMD12 Error Interrupt Reg - write only */
93 /* Force Event Error Interrupt Register- write only */
115 * Controller does not provide transfer-complete interrupt when not
123 #define TYPE_PCI_SDHCI "sdhci-pci"
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dfsl-lx2160a.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR X11
11 interrupt-parent = <&gic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
18 /* DRAM space - 1, size : 2 GB DRAM */
22 compatible = "fixed-clock";
23 #clock-cells = <0>;
24 clock-frequency = <100000000>;
25 clock-output-names = "sysclk";
29 compatible = "fsl,ls2080a-clockgen";
[all …]
H A Dast2400.dtsi3 * https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g4.dtsi
10 #address-cells = <1>;
11 #size-cells = <1>;
12 interrupt-parent = <&vic>;
38 #address-cells = <1>;
39 #size-cells = <0>;
42 compatible = "arm,arm926ej-s";
54 compatible = "simple-bus";
55 #address-cells = <1>;
56 #size-cells = <1>;
[all …]
/openbmc/u-boot/drivers/mmc/
H A Dtmio-common.h1 /* SPDX-License-Identifier: GPL-2.0+ */
11 #define TMIO_SD_CMD_NOSTOP BIT(14) /* No automatic CMD12 issue */
16 #define TMIO_SD_CMD_NORMAL (0 << 8)/* auto-detect of resp-type */
25 #define TMIO_SD_STOP_STP BIT(0) /* issue CMD12 */
94 #define TMIO_SD_DMA_CTL_START BIT(0) /* start DMA (auto cleared) */
H A Dsh_mmcif.h1 /* SPDX-License-Identifier: GPL-2.0 */
51 /* 1: CMD12 auto issue */
/openbmc/qemu/hw/sd/
H A Dsdhci-internal.h8 * Based on MMC controller for Samsung S5PC1xx-based board emulation
188 /* ROC Auto CMD12 error status register 0x0 */
197 FIELD(SDHC_HOSTCTL2, V18_ENA, 3, 1); /* UHS-I only */
198 FIELD(SDHC_HOSTCTL2, DRIVER_STRENGTH, 4, 2); /* UHS-I only */
199 FIELD(SDHC_HOSTCTL2, EXECUTE_TUNING, 6, 1); /* UHS-I only */
200 FIELD(SDHC_HOSTCTL2, SAMPLING_CLKSEL, 7, 1); /* UHS-I only */
247 /* W Force Event Auto CMD12 Error Interrupt Register 0x0000 */
296 * - 3.3v and 1.8v voltages
297 * - SDMA/ADMA1/ADMA2
298 * - high-speed
[all …]
H A Dallwinner-sdhost.c27 #include "hw/qdev-properties.h"
29 #include "hw/sd/allwinner-sdhost.h"
34 #define TYPE_AW_SDHOST_BUS "allwinner-sdhost-bus"
60 REG_SD_A12A = 0x58, /* Auto command 12 argument */
80 REG_SD_SAMP_DL = 0x144, /* Sample Delay Control (sun50i-a64) */
189 if (s->global_ctl & SD_GCTL_INT_ENB) { in allwinner_sdhost_update_irq()
190 irq = s->irq_status & s->irq_mask; in allwinner_sdhost_update_irq()
196 qemu_set_irq(s->irq, !!irq); in allwinner_sdhost_update_irq()
202 if (s->transfer_cnt > bytes) { in allwinner_sdhost_update_transfer_cnt()
203 s->transfer_cnt -= bytes; in allwinner_sdhost_update_transfer_cnt()
[all …]
/openbmc/linux/drivers/mmc/host/
H A Dtmio_mmc_core.c1 // SPDX-License-Identifier: GPL-2.0
5 * TC6393XB, TC6391XB, TC6387XB, T7L66XB, ASIC3, SH-Mobile SoCs
7 * Copyright (C) 2015-19 Renesas Electronics Corporation
8 * Copyright (C) 2016-19 Sang Engineering, Wolfram Sang
29 #include <linux/dma-mapping.h>
38 #include <linux/mmc/slot-gpio.h>
56 if (host->dma_ops) in tmio_mmc_start_dma()
57 host->dma_ops->start(host, data); in tmio_mmc_start_dma()
62 if (host->dma_ops && host->dma_ops->end) in tmio_mmc_end_dma()
63 host->dma_ops->end(host); in tmio_mmc_end_dma()
[all …]
H A Dsdhci-pltfm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * sdhci-pltfm.c Support for SDHCI platform devices
16 * Inspired by sdhci-pci.c, by Pierre Ossman
26 #include "sdhci-pltfm.h"
32 return clk_get_rate(pltfm_host->clk); in sdhci_pltfm_clk_get_max_clock()
45 if (device_property_present(dev, "sdhci,wp-inverted") || in sdhci_wp_inverted()
46 device_property_present(dev, "wp-inverted")) in sdhci_wp_inverted()
49 /* Old device trees don't have the wp-inverted property. */ in sdhci_wp_inverted()
60 struct device_node *np = pdev->dev.of_node; in sdhci_get_compatibility()
65 if (of_device_is_compatible(np, "fsl,p2020-rev1-esdhc")) in sdhci_get_compatibility()
[all …]
H A Dsdhci.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver
7 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
103 * VDD2 - UHS2 or PCIe/NVMe
174 #define SDHCI_INT_ALL_MASK ((unsigned int)-1)
196 #define SDHCI_CTRL_HS400 0x0005 /* Non-standard */
243 #define SDHCI_SUPPORT_HS400 0x80000000 /* Non-standard */
252 /* 4C-4F reserved for more max current */
259 /* 55-57 reserved */
264 /* 60-FB reserved */
[all …]
H A Dsdhci-esdhc-imx.c1 // SPDX-License-Identifier: GPL-2.0
5 * derived from the OF-version.
23 #include <linux/mmc/slot-gpio.h>
28 #include "sdhci-cqhci.h"
29 #include "sdhci-pltfm.h"
30 #include "sdhci-esdhc.h"
82 #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1)
139 * "11" when the STOP CMD12 is issued on imx53 to abort one
140 * open ended multi-blk IO. Otherwise the TC INT wouldn't
218 * struct esdhc_platform_data - platform data for esdhc on i.MX
[all …]
/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dc293si-post.dtsi36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,ifc", "simple-bus";
44 compatible = "fsl,qoriq-pcie-v2.2", "fsl,qoriq-pcie";
46 #size-cells = <2>;
47 #address-cells = <3>;
48 bus-range = <0 255>;
49 clock-frequency = <33333333>;
54 #interrupt-cells = <1>;
55 #size-cells = <2>;
[all …]
H A Dbsc9131si-post.dtsi4 * Copyright 2011-2012 Freescale Semiconductor Inc.
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,ifc", "simple-bus";
43 #address-cells = <1>;
44 #size-cells = <1>;
46 compatible = "fsl,bsc9131-immr", "simple-bus";
47 bus-frequency = <0>; // Filled out by uboot.
49 ecm-law@0 {
50 compatible = "fsl,ecm-law";
[all …]
H A Dp1020si-post.dtsi36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,p1020-elbc", "fsl,elbc", "simple-bus";
45 compatible = "fsl,mpc8548-pcie";
47 #size-cells = <2>;
48 #address-cells = <3>;
49 bus-range = <0 255>;
50 clock-frequency = <33333333>;
55 #interrupt-cells = <1>;
56 #size-cells = <2>;
[all …]
H A Dbsc9132si-post.dtsi36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,ifc", "simple-bus";
45 compatible = "fsl,bsc9132-pcie", "fsl,qoriq-pcie-v2.2";
47 #size-cells = <2>;
48 #address-cells = <3>;
49 bus-range = <0 255>;
54 #interrupt-cells = <1>;
55 #size-cells = <2>;
56 #address-cells = <3>;
[all …]
H A Dp1010si-post.dtsi36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,ifc", "simple-bus";
44 compatible = "fsl,p1010-pcie", "fsl,qoriq-pcie-v2.3";
46 #size-cells = <2>;
47 #address-cells = <3>;
48 bus-range = <0 255>;
49 clock-frequency = <33333333>;
54 #interrupt-cells = <1>;
55 #size-cells = <2>;
[all …]
H A Dp1021si-post.dtsi4 * Copyright 2011-2012 Freescale Semiconductor Inc.
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,p1021-elbc", "fsl,elbc", "simple-bus";
45 compatible = "fsl,mpc8548-pcie";
47 #size-cells = <2>;
48 #address-cells = <3>;
49 bus-range = <0 255>;
50 clock-frequency = <33333333>;
55 #interrupt-cells = <1>;
[all …]
H A Dp1022si-post.dtsi36 #address-cells = <2>;
37 #size-cells = <1>;
39 * The localbus on the P1022 is not a simple-bus because of the eLBC
42 compatible = "fsl,p1022-elbc", "fsl,elbc";
49 compatible = "fsl,mpc8548-pcie";
51 #size-cells = <2>;
52 #address-cells = <3>;
53 bus-range = <0 255>;
54 clock-frequency = <33333333>;
59 #interrupt-cells = <1>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1012a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1012A family SoC.
6 * Copyright 2019-2020 NXP
10 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
23 rtic-a = &rtic_a;
[all …]
/openbmc/linux/arch/arm/boot/dts/broadcom/
H A Dbcm-cygnus.dtsi33 #include <dt-bindings/interrupt-controller/arm-gic.h>
34 #include <dt-bindings/interrupt-controller/irq.h>
35 #include <dt-bindings/clock/bcm-cygnus.h>
38 #address-cells = <1>;
39 #size-cells = <1>;
42 interrupt-parent = <&gic>;
54 #address-cells = <1>;
55 #size-cells = <0>;
59 compatible = "arm,cortex-a9";
60 next-level-cache = <&L2>;
[all …]
/openbmc/linux/arch/arm/boot/dts/aspeed/
H A Daspeed-g6.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/interrupt-controller/aspeed-scu-ic.h>
6 #include <dt-bindings/clock/ast2600-clock.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
13 interrupt-parent = <&gic>;
47 #address-cells = <1>;
48 #size-cells = <0>;
49 enable-method = "aspeed,ast2600-smp";
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