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/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dintel,keembay-phy-usb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/intel,keembay-phy-usb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
14 const: intel,keembay-usb-phy
18 - description: USB APB CPR (clock, power, reset) register
19 - description: USB APB slave register
21 reg-names:
23 - const: cpr-apb-base
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/openbmc/linux/drivers/clocksource/
H A Ddw_apb_timer.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Support for the Synopsys DesignWare APB Timers.
51 return readl(timer->base + offs); in apbt_readl()
57 writel(val, timer->base + offs); in apbt_writel()
62 return readl_relaxed(timer->base + offs); in apbt_readl_relaxed()
68 writel_relaxed(val, timer->base + offs); in apbt_writel_relaxed()
80 * dw_apb_clockevent_pause() - stop the clock_event_device from running
82 * @dw_ced: The APB clock to stop generating events.
86 disable_irq(dw_ced->timer.irq); in dw_apb_clockevent_pause()
87 apbt_disable_int(&dw_ced->timer); in dw_apb_clockevent_pause()
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H A Ddw_apb_timer_of.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Modified from mach-picoxcell/time.c
18 void __iomem **base, u32 *rate) in timer_get_base_and_rate() argument
25 *base = of_iomap(np, 0); in timer_get_base_and_rate()
27 if (!*base) in timer_get_base_and_rate()
50 if (!of_property_read_u32(np, "clock-freq", rate) || in timer_get_base_and_rate()
51 !of_property_read_u32(np, "clock-frequency", rate)) in timer_get_base_and_rate()
66 ret = -EINVAL; in timer_get_base_and_rate()
81 iounmap(*base); in timer_get_base_and_rate()
100 ced = dw_apb_clockevent_init(-1, event_timer->name, 300, iobase, irq, in add_clockevent()
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/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dmediatek,smi-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/memory-controllers/mediatek,smi-common.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Yong Wu <yong.wu@mediatek.com>
22 register which control the iommu port is at each larb's register base. But
23 for generation 1, the register is at smi ao base(smi always on register
24 base). Besides that, the smi async clock should be prepared and enabled for
31 - enum:
32 - mediatek,mt2701-smi-common
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/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dlpc1850-cgu.txt5 a base clock and itself is one of the inputs to the two Clock
13 corresponds to one of the base clocks for the LPC18xx.
15 - Above text taken from NXP LPC1850 User Manual.
19 Documentation/devicetree/bindings/clock/clock-bindings.txt
22 - compatible:
23 Should be "nxp,lpc1850-cgu"
24 - reg:
25 Shall define the base and range of the address space
27 - #clock-cells:
28 Shall have value <1>. The permitted clock-specifier values
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/openbmc/linux/drivers/phy/hisilicon/
H A Dphy-hi3670-pcie.c1 // SPDX-License-Identifier: GPL-2.0
154 void __iomem *base; member
155 struct regmap *apb; member
171 writel(val, phy->base + APB_PHY_START_ADDR + reg); in hi3670_apb_phy_writel()
176 return readl(phy->base + APB_PHY_START_ADDR + reg); in hi3670_apb_phy_readl()
193 writel(val, phy->base + reg); in kirin_apb_natural_phy_writel()
199 return readl(phy->base + reg); in kirin_apb_natural_phy_readl()
206 regmap_read(phy->sysctrl, SCTRL_PCIE_OE_OFFSET, &val); in hi3670_pcie_phy_oe_enable()
212 regmap_write(phy->sysctrl, SCTRL_PCIE_OE_OFFSET, val); in hi3670_pcie_phy_oe_enable()
217 struct device *dev = phy->dev; in hi3670_pcie_get_eyeparam()
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/openbmc/linux/drivers/pci/controller/dwc/
H A Dpcie-kirin.c1 // SPDX-License-Identifier: GPL-2.0
29 #include "pcie-designware.h"
31 #define to_kirin_pcie(x) dev_get_drvdata((x)->dev)
38 /* info located in APB */
60 * in-board Ethernet adapter and the other two connected to M.2 and mini
76 struct regmap *apb; member
83 /* Per-slot PERST# */
88 /* Per-slot clkreq */
101 /* PHY info located in APB */
128 void __iomem *base; member
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/openbmc/linux/drivers/clk/mmp/
H A Dclk-apbc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * mmp APB clock operation source file
17 /* Common APB clock register bit definitions */
18 #define APBC_APBCLK (1 << 0) /* APB Bus Clock Enable */
26 void __iomem *base; member
42 if (apbc->lock) in clk_apbc_prepare()
43 spin_lock_irqsave(apbc->lock, flags); in clk_apbc_prepare()
45 data = readl_relaxed(apbc->base); in clk_apbc_prepare()
46 if (apbc->flags & APBC_POWER_CTRL) in clk_apbc_prepare()
49 writel_relaxed(data, apbc->base); in clk_apbc_prepare()
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/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dsnps,dw-apb-ictl.txt1 Synopsys DesignWare APB interrupt controller (dw_apb_ictl)
3 Synopsys DesignWare provides interrupt controller IP for APB known as
5 APB bus, e.g. Marvell Armada 1500. It can also be used as primary interrupt
9 - compatible: shall be "snps,dw-apb-ictl"
10 - reg: physical base address of the controller and length of memory mapped
12 - interrupt-controller: identifies the node as an interrupt controller
13 - #interrupt-cells: number of cells to encode an interrupt-specifier, shall be 1
16 - interrupts: interrupt reference to primary interrupt controller
20 - 0 maps to bit 0 of low interrupts,
21 - 1 maps to bit 1 of low interrupts,
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/openbmc/linux/drivers/clk/sprd/
H A Dsc9860-clk.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
16 #include <dt-bindings/clock/sprd,sc9860-clk.h>
25 static CLK_FIXED_FACTOR(fac_4m, "fac-4m", "ext-26m",
27 static CLK_FIXED_FACTOR(fac_2m, "fac-2m", "ext-26m",
29 static CLK_FIXED_FACTOR(fac_1m, "fac-1m", "ext-26m",
31 static CLK_FIXED_FACTOR(fac_250k, "fac-250k", "ext-26m",
33 static CLK_FIXED_FACTOR(fac_rpll0_26m, "rpll0-26m", "ext-26m",
35 static CLK_FIXED_FACTOR(fac_rpll1_26m, "rpll1-26m", "ext-26m",
37 static CLK_FIXED_FACTOR(fac_rco_25m, "rco-25m", "ext-rc0-100m",
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/openbmc/qemu/hw/arm/
H A Dmps2.c17 * "mps2-an385" -- Cortex-M3 as documented in ARM Application Note AN385
18 * "mps2-an386" -- Cortex-M4 as documented in ARM Application Note AN386
19 * "mps2-an500" -- Cortex-M7 as documented in ARM Application Note AN500
20 * "mps2-an511" -- Cortex-M3 'DesignStart' as documented in AN511
24 * https://developer.arm.com/products/system-design/development-boards/cortex-m-prototyping-system
31 #include "qemu/error-report.h"
34 #include "hw/or-irq.h"
36 #include "exec/address-spaces.h"
38 #include "hw/qdev-properties.h"
40 #include "hw/char/cmsdk-apb-uart.h"
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/openbmc/qemu/include/hw/watchdog/
H A Dcmsdk-apb-watchdog.h2 * ARM CMSDK APB watchdog emulation
13 * This is a model of the "APB watchdog" which is part of the Cortex-M
14 * System Design Kit (CMSDK) and documented in the Cortex-M System
16 * https://developer.arm.com/products/system-design/system-design-kits/cortex-m-system-design-kit
25 * (For instance the IoTKit does this with the non-secure watchdog, so that
26 * secure code can control whether non-secure code can perform a system
39 #define TYPE_CMSDK_APB_WATCHDOG "cmsdk-apb-watchdog"
43 * This shares the same struct (and cast macro) as the base
44 * cmsdk-apb-watchdog device.
46 #define TYPE_LUMINARY_WATCHDOG "luminary-watchdog"
/openbmc/linux/arch/arc/boot/dts/
H A Daxc001.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
15 #address-cells = <2>;
16 #size-cells = <2>;
19 compatible = "simple-bus";
20 #address-cells = <1>;
21 #size-cells = <1>;
26 #clock-cells = <0>;
27 compatible = "fixed-clock";
28 clock-frequency = <750000000>;
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/openbmc/u-boot/drivers/clk/
H A Dclk_stm32f.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
8 #include <clk-uclass.h>
16 #include <dt-bindings/mfd/stm32f7-rcc.h>
132 struct stm32_rcc_regs *base; member
147 struct stm32_rcc_regs *regs = priv->base; in configure_clocks()
148 struct stm32_pwr_regs *pwr = priv->pwr_regs; in configure_clocks()
149 struct pll_psc *sys_pll_psc = &priv->info.sys_pll_psc; in configure_clocks()
152 setbits_le32(&regs->cr, RCC_CR_HSION); in configure_clocks()
153 writel(0, &regs->cfgr); /* Reset CFGR */ in configure_clocks()
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/openbmc/linux/Documentation/devicetree/bindings/display/imx/
H A Dnxp,imx8mq-dcss.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/imx/nxp,imx8mq-dcss.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Laurentiu Palcu <laurentiu.palcu@nxp.com>
17 2.2) or MIPI-DSI. The DCSS is intended to support up to 4kp60 displays. HDR10
23 const: nxp,imx8mq-dcss
27 - description: DCSS base address and size, up to IRQ steer start
28 - description: DCSS BLKCTL base address and size
32 - description: Context loader completion and error interrupt
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/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Drockchip,rk3399-pcie-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Lin <shawn.lin@rock-chips.com>
13 - $ref: /schemas/pci/pci-ep.yaml#
14 - $ref: rockchip,rk3399-pcie-common.yaml#
18 const: rockchip,rk3399-pcie-ep
22 reg-names:
24 - const: apb-base
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H A Drockchip,rk3399-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Lin <shawn.lin@rock-chips.com>
13 - $ref: /schemas/pci/pci-bus.yaml#
14 - $ref: rockchip,rk3399-pcie-common.yaml#
18 const: rockchip,rk3399-pcie
22 reg-names:
24 - const: axi-base
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H A Drcar-pci-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Renesas Electronics Europe GmbH - https://www.renesas.com/eu/en/
4 ---
5 $id: http://devicetree.org/schemas/pci/rcar-pci-ep.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Renesas R-Car PCIe Endpoint
11 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
12 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
17 - enum:
18 - renesas,r8a774a1-pcie-ep # RZ/G2M
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/openbmc/u-boot/drivers/i2c/
H A Daspeed_i2c_global.c1 // SPDX-License-Identifier: GPL-2.0+
27 * APB clk : 100Mhz
28 * div : scl : baseclk [APB/((div/2) + 1)] : tBuf [1/bclk * 16]
29 * I2CG10[31:24] base clk4 for i2c auto recovery timeout counter (0xC6)
30 * I2CG10[23:16] base clk3 for Standard-mode (100Khz) min tBuf 4.7us
36 * I2CG10[15:8] base clk2 for Fast-mode (400Khz) min tBuf 1.3us
38 * I2CG10[7:0] base clk1 for Fast-mode Plus (1Mhz) min tBuf 0.5us
47 i2c_global->regs = devfdt_get_addr_ptr(dev); in aspeed_i2c_global_probe()
48 if (IS_ERR(i2c_global->regs)) in aspeed_i2c_global_probe()
49 return PTR_ERR(i2c_global->regs); in aspeed_i2c_global_probe()
[all …]
/openbmc/linux/drivers/gpu/drm/bridge/imx/
H A Dimx8qxp-pixel-combiner.c1 // SPDX-License-Identifier: GPL-2.0+
11 #include <linux/media-bus-format.h>
52 #define DRIVER_NAME "imx8qxp-pixel-combiner"
73 void __iomem *base; member
78 return readl(pc->base + offset); in imx8qxp_pc_read()
84 writel(value, pc->base + offset); in imx8qxp_pc_write()
104 if (mode->hdisplay > 2560) in imx8qxp_pc_bridge_mode_valid()
113 struct imx8qxp_pc_channel *ch = bridge->driver_private; in imx8qxp_pc_bridge_attach()
114 struct imx8qxp_pc *pc = ch->pc; in imx8qxp_pc_bridge_attach()
117 DRM_DEV_ERROR(pc->dev, in imx8qxp_pc_bridge_attach()
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/openbmc/linux/drivers/phy/intel/
H A Dphy-intel-keembay-usb.c1 // SPDX-License-Identifier: GPL-2.0-only
35 /* USS APB slave registers */
76 ret = regmap_update_bits(priv->regmap_cpr, USS_CPR_CLK_SET, in keembay_usb_clocks_on()
79 dev_err(priv->dev, "error clock set: %d\n", ret); in keembay_usb_clocks_on()
83 ret = regmap_update_bits(priv->regmap_cpr, USS_CPR_RST_SET, in keembay_usb_clocks_on()
86 dev_err(priv->dev, "error reset set: %d\n", ret); in keembay_usb_clocks_on()
90 ret = regmap_update_bits(priv->regmap_slv, in keembay_usb_clocks_on()
95 dev_err(priv->dev, "error iddq disable: %d\n", ret); in keembay_usb_clocks_on()
102 ret = regmap_update_bits(priv->regmap_slv, USS_USB_PHY_CFG0, in keembay_usb_clocks_on()
106 dev_err(priv->dev, "error ref clock select: %d\n", ret); in keembay_usb_clocks_on()
[all …]
/openbmc/linux/arch/arc/plat-axs10x/
H A Daxs10x.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
11 #include <asm/asm-offsets.h>
31 * intermediate DW APB GPIO blocks (mainly for debouncing) in axs10x_enable_gpio_intc_wire()
33 * --------------------- in axs10x_enable_gpio_intc_wire()
34 * | snps,arc700-intc | in axs10x_enable_gpio_intc_wire()
35 * --------------------- in axs10x_enable_gpio_intc_wire()
37 * ------------------- ------------------- in axs10x_enable_gpio_intc_wire()
38 * | snps,dw-apb-gpio | | snps,dw-apb-gpio | in axs10x_enable_gpio_intc_wire()
39 * ------------------- ------------------- in axs10x_enable_gpio_intc_wire()
[all …]
/openbmc/u-boot/drivers/gpio/
H A Ddwapb_gpio.c1 // SPDX-License-Identifier: GPL-2.0+
5 * DesignWare APB GPIO driver
14 #include <dm/device-internal.h>
41 fdt_addr_t base; member
48 clrbits_le32(plat->base + GPIO_SWPORT_DDR(plat->bank), 1 << pin); in dwapb_gpio_direction_input()
57 setbits_le32(plat->base + GPIO_SWPORT_DDR(plat->bank), 1 << pin); in dwapb_gpio_direction_output()
60 setbits_le32(plat->base + GPIO_SWPORT_DR(plat->bank), 1 << pin); in dwapb_gpio_direction_output()
62 clrbits_le32(plat->base + GPIO_SWPORT_DR(plat->bank), 1 << pin); in dwapb_gpio_direction_output()
70 return !!(readl(plat->base + GPIO_EXT_PORT(plat->bank)) & (1 << pin)); in dwapb_gpio_get_value()
79 setbits_le32(plat->base + GPIO_SWPORT_DR(plat->bank), 1 << pin); in dwapb_gpio_set_value()
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-armada100/
H A Darmada100.h1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
14 /* Common APB clock register bit definitions */
15 #define APBC_APBCLK (1<<0) /* APB Bus Clock Enable */
37 /* Register Base Addresses */
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/fsl/
H A Dimx8m-ddrc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/fsl/imx8m-ddrc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peng Fan <peng.fan@nxp.com>
18 switching is implemented by TF-A code which runs from a SRAM area.
27 - enum:
28 - fsl,imx8mn-ddrc
29 - fsl,imx8mm-ddrc
30 - fsl,imx8mq-ddrc
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