173075011SMauro Carvalho Chehab // SPDX-License-Identifier: GPL-2.0
273075011SMauro Carvalho Chehab /*
373075011SMauro Carvalho Chehab * PCIe phy driver for Kirin 970
473075011SMauro Carvalho Chehab *
573075011SMauro Carvalho Chehab * Copyright (C) 2017 HiSilicon Electronics Co., Ltd.
673075011SMauro Carvalho Chehab * https://www.huawei.com
773075011SMauro Carvalho Chehab * Copyright (C) 2021 Huawei Technologies Co., Ltd.
873075011SMauro Carvalho Chehab * https://www.huawei.com
973075011SMauro Carvalho Chehab *
1073075011SMauro Carvalho Chehab * Authors:
1173075011SMauro Carvalho Chehab * Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
1273075011SMauro Carvalho Chehab * Manivannan Sadhasivam <mani@kernel.org>
1373075011SMauro Carvalho Chehab *
1473075011SMauro Carvalho Chehab * Based on:
1573075011SMauro Carvalho Chehab * https://lore.kernel.org/lkml/4c9d6581478aa966698758c0420933f5defab4dd.1612335031.git.mchehab+huawei@kernel.org/
1673075011SMauro Carvalho Chehab */
1773075011SMauro Carvalho Chehab
1873075011SMauro Carvalho Chehab #include <linux/bitfield.h>
1973075011SMauro Carvalho Chehab #include <linux/clk.h>
2073075011SMauro Carvalho Chehab #include <linux/gpio.h>
2173075011SMauro Carvalho Chehab #include <linux/kernel.h>
2273075011SMauro Carvalho Chehab #include <linux/mfd/syscon.h>
2373075011SMauro Carvalho Chehab #include <linux/module.h>
2473075011SMauro Carvalho Chehab #include <linux/of_gpio.h>
2573075011SMauro Carvalho Chehab #include <linux/phy/phy.h>
2673075011SMauro Carvalho Chehab #include <linux/platform_device.h>
2773075011SMauro Carvalho Chehab #include <linux/regmap.h>
2873075011SMauro Carvalho Chehab
2973075011SMauro Carvalho Chehab #define AXI_CLK_FREQ 207500000
3073075011SMauro Carvalho Chehab #define REF_CLK_FREQ 100000000
3173075011SMauro Carvalho Chehab
3273075011SMauro Carvalho Chehab /* PCIe CTRL registers */
3373075011SMauro Carvalho Chehab #define SOC_PCIECTRL_CTRL7_ADDR 0x01c
3473075011SMauro Carvalho Chehab #define SOC_PCIECTRL_CTRL12_ADDR 0x030
3573075011SMauro Carvalho Chehab #define SOC_PCIECTRL_CTRL20_ADDR 0x050
3673075011SMauro Carvalho Chehab #define SOC_PCIECTRL_CTRL21_ADDR 0x054
3773075011SMauro Carvalho Chehab
3873075011SMauro Carvalho Chehab #define PCIE_OUTPUT_PULL_BITS GENMASK(3, 0)
3973075011SMauro Carvalho Chehab #define SOC_PCIECTRL_CTRL20_2P_MEM_CTRL 0x02605550
4073075011SMauro Carvalho Chehab #define SOC_PCIECTRL_CTRL21_DEFAULT 0x20000070
4173075011SMauro Carvalho Chehab #define PCIE_PULL_UP_SYS_AUX_PWR_DET BIT(10)
4273075011SMauro Carvalho Chehab #define PCIE_OUTPUT_PULL_DOWN BIT(1)
4373075011SMauro Carvalho Chehab
4473075011SMauro Carvalho Chehab /* PCIe PHY registers */
4573075011SMauro Carvalho Chehab #define SOC_PCIEPHY_CTRL0_ADDR 0x000
4673075011SMauro Carvalho Chehab #define SOC_PCIEPHY_CTRL1_ADDR 0x004
4773075011SMauro Carvalho Chehab #define SOC_PCIEPHY_CTRL38_ADDR 0x0098
4873075011SMauro Carvalho Chehab #define SOC_PCIEPHY_STATE0_ADDR 0x400
4973075011SMauro Carvalho Chehab
5073075011SMauro Carvalho Chehab #define RAWLANEN_DIG_PCS_XF_TX_OVRD_IN_1 0xc004
5173075011SMauro Carvalho Chehab #define SUP_DIG_LVL_OVRD_IN 0x003c
5273075011SMauro Carvalho Chehab #define LANEN_DIG_ASIC_TX_OVRD_IN_1 0x4008
5373075011SMauro Carvalho Chehab #define LANEN_DIG_ASIC_TX_OVRD_IN_2 0x400c
5473075011SMauro Carvalho Chehab
5573075011SMauro Carvalho Chehab #define PCIEPHY_RESET_BIT BIT(17)
5673075011SMauro Carvalho Chehab #define PCIEPHY_PIPE_LINE0_RESET_BIT BIT(19)
5773075011SMauro Carvalho Chehab #define PCIE_TXDETECT_RX_FAIL BIT(2)
5873075011SMauro Carvalho Chehab #define PCIE_CLK_SOURCE BIT(8)
5973075011SMauro Carvalho Chehab #define PCIE_IS_CLOCK_STABLE BIT(19)
6073075011SMauro Carvalho Chehab #define PCIE_PULL_DOWN_PHY_TEST_POWERDOWN BIT(22)
6173075011SMauro Carvalho Chehab #define PCIE_DEASSERT_CONTROLLER_PERST BIT(2)
6273075011SMauro Carvalho Chehab
6373075011SMauro Carvalho Chehab #define EYEPARAM_NOCFG 0xffffffff
6473075011SMauro Carvalho Chehab #define EYE_PARM0_MASK GENMASK(8, 6)
6573075011SMauro Carvalho Chehab #define EYE_PARM1_MASK GENMASK(11, 8)
6673075011SMauro Carvalho Chehab #define EYE_PARM2_MASK GENMASK(5, 0)
6773075011SMauro Carvalho Chehab #define EYE_PARM3_MASK GENMASK(12, 7)
6873075011SMauro Carvalho Chehab #define EYE_PARM4_MASK GENMASK(14, 9)
6973075011SMauro Carvalho Chehab #define EYE_PARM0_EN BIT(9)
7073075011SMauro Carvalho Chehab #define EYE_PARM1_EN BIT(12)
7173075011SMauro Carvalho Chehab #define EYE_PARM2_EN BIT(6)
7273075011SMauro Carvalho Chehab #define EYE_PARM3_EN BIT(13)
7373075011SMauro Carvalho Chehab #define EYE_PARM4_EN BIT(15)
7473075011SMauro Carvalho Chehab
7573075011SMauro Carvalho Chehab /* hi3670 pciephy register */
7673075011SMauro Carvalho Chehab #define APB_PHY_START_ADDR 0x40000
7773075011SMauro Carvalho Chehab #define SOC_PCIEPHY_MMC1PLL_CTRL1 0xc04
7873075011SMauro Carvalho Chehab #define SOC_PCIEPHY_MMC1PLL_CTRL16 0xC40
7973075011SMauro Carvalho Chehab #define SOC_PCIEPHY_MMC1PLL_CTRL17 0xC44
8073075011SMauro Carvalho Chehab #define SOC_PCIEPHY_MMC1PLL_CTRL20 0xC50
8173075011SMauro Carvalho Chehab #define SOC_PCIEPHY_MMC1PLL_CTRL21 0xC54
8273075011SMauro Carvalho Chehab #define SOC_PCIEPHY_MMC1PLL_STAT0 0xE00
8373075011SMauro Carvalho Chehab
8473075011SMauro Carvalho Chehab #define CRGPERIPH_PEREN12 0x470
8573075011SMauro Carvalho Chehab #define CRGPERIPH_PERDIS12 0x474
8673075011SMauro Carvalho Chehab #define CRGPERIPH_PCIECTRL0 0x800
8773075011SMauro Carvalho Chehab
8873075011SMauro Carvalho Chehab #define PCIE_FNPLL_FBDIV_MASK GENMASK(27, 16)
8973075011SMauro Carvalho Chehab #define PCIE_FNPLL_FRACDIV_MASK GENMASK(23, 0)
9073075011SMauro Carvalho Chehab #define PCIE_FNPLL_POSTDIV1_MASK GENMASK(10, 8)
9173075011SMauro Carvalho Chehab #define PCIE_FNPLL_POSTDIV2_MASK GENMASK(14, 12)
9273075011SMauro Carvalho Chehab #define PCIE_FNPLL_PLL_MODE_MASK BIT(25)
9373075011SMauro Carvalho Chehab
9473075011SMauro Carvalho Chehab #define PCIE_FNPLL_DLL_EN BIT(27)
9573075011SMauro Carvalho Chehab #define PCIE_FNPLL_FBDIV 0xd0
9673075011SMauro Carvalho Chehab #define PCIE_FNPLL_FRACDIV 0x555555
9773075011SMauro Carvalho Chehab #define PCIE_FNPLL_POSTDIV1 0x5
9873075011SMauro Carvalho Chehab #define PCIE_FNPLL_POSTDIV2 0x4
9973075011SMauro Carvalho Chehab #define PCIE_FNPLL_PLL_MODE 0x0
10073075011SMauro Carvalho Chehab
10173075011SMauro Carvalho Chehab #define PCIE_PHY_MMC1PLL 0x20
10273075011SMauro Carvalho Chehab #define PCIE_PHY_CHOOSE_FNPLL BIT(27)
10373075011SMauro Carvalho Chehab #define PCIE_PHY_MMC1PLL_DISABLE BIT(0)
10473075011SMauro Carvalho Chehab #define PCIE_PHY_PCIEPL_BP BIT(16)
10573075011SMauro Carvalho Chehab
10673075011SMauro Carvalho Chehab /* define ie,oe cfg */
10773075011SMauro Carvalho Chehab #define IO_OE_HARD_GT_MODE BIT(1)
10873075011SMauro Carvalho Chehab #define IO_IE_EN_HARD_BYPASS BIT(27)
10973075011SMauro Carvalho Chehab #define IO_OE_EN_HARD_BYPASS BIT(11)
11073075011SMauro Carvalho Chehab #define IO_HARD_CTRL_DEBOUNCE_BYPASS BIT(10)
11173075011SMauro Carvalho Chehab #define IO_OE_GT_MODE BIT(8)
11273075011SMauro Carvalho Chehab #define DEBOUNCE_WAITCFG_IN GENMASK(23, 20)
11373075011SMauro Carvalho Chehab #define DEBOUNCE_WAITCFG_OUT GENMASK(16, 13)
11473075011SMauro Carvalho Chehab
11573075011SMauro Carvalho Chehab #define IO_HP_DEBOUNCE_GT (BIT(12) | BIT(15))
11673075011SMauro Carvalho Chehab #define IO_PHYREF_SOFT_GT_MODE BIT(14)
11773075011SMauro Carvalho Chehab #define IO_REF_SOFT_GT_MODE BIT(13)
11873075011SMauro Carvalho Chehab #define IO_REF_HARD_GT_MODE BIT(0)
11973075011SMauro Carvalho Chehab
12073075011SMauro Carvalho Chehab /* noc power domain */
12173075011SMauro Carvalho Chehab #define NOC_POWER_IDLEREQ_1 0x38c
12273075011SMauro Carvalho Chehab #define NOC_POWER_IDLE_1 0x394
12373075011SMauro Carvalho Chehab #define NOC_PW_MASK 0x10000
12473075011SMauro Carvalho Chehab #define NOC_PW_SET_BIT 0x1
12573075011SMauro Carvalho Chehab
12673075011SMauro Carvalho Chehab #define NUM_EYEPARAM 5
12773075011SMauro Carvalho Chehab
12873075011SMauro Carvalho Chehab /* info located in sysctrl */
12973075011SMauro Carvalho Chehab #define SCTRL_PCIE_CMOS_OFFSET 0x60
13073075011SMauro Carvalho Chehab #define SCTRL_PCIE_CMOS_BIT 0x10
13173075011SMauro Carvalho Chehab #define SCTRL_PCIE_ISO_OFFSET 0x44
13273075011SMauro Carvalho Chehab #define SCTRL_PCIE_ISO_BIT 0x30
13373075011SMauro Carvalho Chehab #define SCTRL_PCIE_HPCLK_OFFSET 0x190
13473075011SMauro Carvalho Chehab #define SCTRL_PCIE_HPCLK_BIT 0x184000
13573075011SMauro Carvalho Chehab #define SCTRL_PCIE_OE_OFFSET 0x14a
13673075011SMauro Carvalho Chehab #define PCIE_DEBOUNCE_PARAM 0xf0f400
13773075011SMauro Carvalho Chehab #define PCIE_OE_BYPASS GENMASK(29, 28)
13873075011SMauro Carvalho Chehab
13973075011SMauro Carvalho Chehab /* peri_crg ctrl */
14073075011SMauro Carvalho Chehab #define CRGCTRL_PCIE_ASSERT_OFFSET 0x88
14173075011SMauro Carvalho Chehab #define CRGCTRL_PCIE_ASSERT_BIT 0x8c000000
14273075011SMauro Carvalho Chehab
14373075011SMauro Carvalho Chehab #define FNPLL_HAS_LOCKED BIT(4)
14473075011SMauro Carvalho Chehab
14573075011SMauro Carvalho Chehab /* Time for delay */
14673075011SMauro Carvalho Chehab #define TIME_CMOS_MIN 100
14773075011SMauro Carvalho Chehab #define TIME_CMOS_MAX 105
14873075011SMauro Carvalho Chehab #define PIPE_CLK_STABLE_TIME 100
14973075011SMauro Carvalho Chehab #define PLL_CTRL_WAIT_TIME 200
15073075011SMauro Carvalho Chehab #define NOC_POWER_TIME 100
15173075011SMauro Carvalho Chehab
15273075011SMauro Carvalho Chehab struct hi3670_pcie_phy {
15373075011SMauro Carvalho Chehab struct device *dev;
15473075011SMauro Carvalho Chehab void __iomem *base;
15573075011SMauro Carvalho Chehab struct regmap *apb;
15673075011SMauro Carvalho Chehab struct regmap *crgctrl;
15773075011SMauro Carvalho Chehab struct regmap *sysctrl;
15873075011SMauro Carvalho Chehab struct regmap *pmctrl;
15973075011SMauro Carvalho Chehab struct clk *apb_sys_clk;
16073075011SMauro Carvalho Chehab struct clk *apb_phy_clk;
16173075011SMauro Carvalho Chehab struct clk *phy_ref_clk;
16273075011SMauro Carvalho Chehab struct clk *aclk;
16373075011SMauro Carvalho Chehab struct clk *aux_clk;
16473075011SMauro Carvalho Chehab u32 eye_param[NUM_EYEPARAM];
16573075011SMauro Carvalho Chehab };
16673075011SMauro Carvalho Chehab
16773075011SMauro Carvalho Chehab /* Registers in PCIePHY */
hi3670_apb_phy_writel(struct hi3670_pcie_phy * phy,u32 val,u32 reg)16873075011SMauro Carvalho Chehab static inline void hi3670_apb_phy_writel(struct hi3670_pcie_phy *phy, u32 val,
16973075011SMauro Carvalho Chehab u32 reg)
17073075011SMauro Carvalho Chehab {
17173075011SMauro Carvalho Chehab writel(val, phy->base + APB_PHY_START_ADDR + reg);
17273075011SMauro Carvalho Chehab }
17373075011SMauro Carvalho Chehab
hi3670_apb_phy_readl(struct hi3670_pcie_phy * phy,u32 reg)17473075011SMauro Carvalho Chehab static inline u32 hi3670_apb_phy_readl(struct hi3670_pcie_phy *phy, u32 reg)
17573075011SMauro Carvalho Chehab {
17673075011SMauro Carvalho Chehab return readl(phy->base + APB_PHY_START_ADDR + reg);
17773075011SMauro Carvalho Chehab }
17873075011SMauro Carvalho Chehab
hi3670_apb_phy_updatel(struct hi3670_pcie_phy * phy,u32 val,u32 mask,u32 reg)17973075011SMauro Carvalho Chehab static inline void hi3670_apb_phy_updatel(struct hi3670_pcie_phy *phy,
18073075011SMauro Carvalho Chehab u32 val, u32 mask, u32 reg)
18173075011SMauro Carvalho Chehab {
18273075011SMauro Carvalho Chehab u32 regval;
18373075011SMauro Carvalho Chehab
18473075011SMauro Carvalho Chehab regval = hi3670_apb_phy_readl(phy, reg);
18573075011SMauro Carvalho Chehab regval &= ~mask;
18673075011SMauro Carvalho Chehab regval |= val;
18773075011SMauro Carvalho Chehab hi3670_apb_phy_writel(phy, regval, reg);
18873075011SMauro Carvalho Chehab }
18973075011SMauro Carvalho Chehab
kirin_apb_natural_phy_writel(struct hi3670_pcie_phy * phy,u32 val,u32 reg)19073075011SMauro Carvalho Chehab static inline void kirin_apb_natural_phy_writel(struct hi3670_pcie_phy *phy,
19173075011SMauro Carvalho Chehab u32 val, u32 reg)
19273075011SMauro Carvalho Chehab {
19373075011SMauro Carvalho Chehab writel(val, phy->base + reg);
19473075011SMauro Carvalho Chehab }
19573075011SMauro Carvalho Chehab
kirin_apb_natural_phy_readl(struct hi3670_pcie_phy * phy,u32 reg)19673075011SMauro Carvalho Chehab static inline u32 kirin_apb_natural_phy_readl(struct hi3670_pcie_phy *phy,
19773075011SMauro Carvalho Chehab u32 reg)
19873075011SMauro Carvalho Chehab {
19973075011SMauro Carvalho Chehab return readl(phy->base + reg);
20073075011SMauro Carvalho Chehab }
20173075011SMauro Carvalho Chehab
hi3670_pcie_phy_oe_enable(struct hi3670_pcie_phy * phy,bool enable)20273075011SMauro Carvalho Chehab static void hi3670_pcie_phy_oe_enable(struct hi3670_pcie_phy *phy, bool enable)
20373075011SMauro Carvalho Chehab {
20473075011SMauro Carvalho Chehab u32 val;
20573075011SMauro Carvalho Chehab
20673075011SMauro Carvalho Chehab regmap_read(phy->sysctrl, SCTRL_PCIE_OE_OFFSET, &val);
20773075011SMauro Carvalho Chehab val |= PCIE_DEBOUNCE_PARAM;
20873075011SMauro Carvalho Chehab if (enable)
20973075011SMauro Carvalho Chehab val &= ~PCIE_OE_BYPASS;
21073075011SMauro Carvalho Chehab else
21173075011SMauro Carvalho Chehab val |= PCIE_OE_BYPASS;
21273075011SMauro Carvalho Chehab regmap_write(phy->sysctrl, SCTRL_PCIE_OE_OFFSET, val);
21373075011SMauro Carvalho Chehab }
21473075011SMauro Carvalho Chehab
hi3670_pcie_get_eyeparam(struct hi3670_pcie_phy * phy)21573075011SMauro Carvalho Chehab static void hi3670_pcie_get_eyeparam(struct hi3670_pcie_phy *phy)
21673075011SMauro Carvalho Chehab {
21773075011SMauro Carvalho Chehab struct device *dev = phy->dev;
21873075011SMauro Carvalho Chehab struct device_node *np;
21973075011SMauro Carvalho Chehab int ret, i;
22073075011SMauro Carvalho Chehab
22173075011SMauro Carvalho Chehab np = dev->of_node;
22273075011SMauro Carvalho Chehab
22373075011SMauro Carvalho Chehab ret = of_property_read_u32_array(np, "hisilicon,eye-diagram-param",
22473075011SMauro Carvalho Chehab phy->eye_param, NUM_EYEPARAM);
22573075011SMauro Carvalho Chehab if (!ret)
22673075011SMauro Carvalho Chehab return;
22773075011SMauro Carvalho Chehab
22873075011SMauro Carvalho Chehab /* There's no optional eye_param property. Set array to default */
22973075011SMauro Carvalho Chehab for (i = 0; i < NUM_EYEPARAM; i++)
23073075011SMauro Carvalho Chehab phy->eye_param[i] = EYEPARAM_NOCFG;
23173075011SMauro Carvalho Chehab }
23273075011SMauro Carvalho Chehab
hi3670_pcie_set_eyeparam(struct hi3670_pcie_phy * phy)23373075011SMauro Carvalho Chehab static void hi3670_pcie_set_eyeparam(struct hi3670_pcie_phy *phy)
23473075011SMauro Carvalho Chehab {
23573075011SMauro Carvalho Chehab u32 val;
23673075011SMauro Carvalho Chehab
23773075011SMauro Carvalho Chehab val = kirin_apb_natural_phy_readl(phy, RAWLANEN_DIG_PCS_XF_TX_OVRD_IN_1);
23873075011SMauro Carvalho Chehab
23973075011SMauro Carvalho Chehab if (phy->eye_param[1] != EYEPARAM_NOCFG) {
24073075011SMauro Carvalho Chehab val &= ~EYE_PARM1_MASK;
24173075011SMauro Carvalho Chehab val |= FIELD_PREP(EYE_PARM1_MASK, phy->eye_param[1]);
24273075011SMauro Carvalho Chehab val |= EYE_PARM1_EN;
24373075011SMauro Carvalho Chehab }
24473075011SMauro Carvalho Chehab kirin_apb_natural_phy_writel(phy, val,
24573075011SMauro Carvalho Chehab RAWLANEN_DIG_PCS_XF_TX_OVRD_IN_1);
24673075011SMauro Carvalho Chehab
24773075011SMauro Carvalho Chehab val = kirin_apb_natural_phy_readl(phy, LANEN_DIG_ASIC_TX_OVRD_IN_2);
24873075011SMauro Carvalho Chehab val &= ~(EYE_PARM2_MASK | EYE_PARM3_MASK);
24973075011SMauro Carvalho Chehab if (phy->eye_param[2] != EYEPARAM_NOCFG) {
25073075011SMauro Carvalho Chehab val |= FIELD_PREP(EYE_PARM2_MASK, phy->eye_param[2]);
25173075011SMauro Carvalho Chehab val |= EYE_PARM2_EN;
25273075011SMauro Carvalho Chehab }
25373075011SMauro Carvalho Chehab
25473075011SMauro Carvalho Chehab if (phy->eye_param[3] != EYEPARAM_NOCFG) {
25573075011SMauro Carvalho Chehab val |= FIELD_PREP(EYE_PARM3_MASK, phy->eye_param[3]);
25673075011SMauro Carvalho Chehab val |= EYE_PARM3_EN;
25773075011SMauro Carvalho Chehab }
25873075011SMauro Carvalho Chehab
25973075011SMauro Carvalho Chehab kirin_apb_natural_phy_writel(phy, val, LANEN_DIG_ASIC_TX_OVRD_IN_2);
26073075011SMauro Carvalho Chehab
26173075011SMauro Carvalho Chehab val = kirin_apb_natural_phy_readl(phy, SUP_DIG_LVL_OVRD_IN);
26273075011SMauro Carvalho Chehab if (phy->eye_param[0] != EYEPARAM_NOCFG) {
26373075011SMauro Carvalho Chehab val &= ~EYE_PARM0_MASK;
26473075011SMauro Carvalho Chehab val |= FIELD_PREP(EYE_PARM0_MASK, phy->eye_param[0]);
26573075011SMauro Carvalho Chehab val |= EYE_PARM0_EN;
26673075011SMauro Carvalho Chehab }
26773075011SMauro Carvalho Chehab kirin_apb_natural_phy_writel(phy, val, SUP_DIG_LVL_OVRD_IN);
26873075011SMauro Carvalho Chehab
26973075011SMauro Carvalho Chehab val = kirin_apb_natural_phy_readl(phy, LANEN_DIG_ASIC_TX_OVRD_IN_1);
27073075011SMauro Carvalho Chehab if (phy->eye_param[4] != EYEPARAM_NOCFG) {
27173075011SMauro Carvalho Chehab val &= ~EYE_PARM4_MASK;
27273075011SMauro Carvalho Chehab val |= FIELD_PREP(EYE_PARM4_MASK, phy->eye_param[4]);
27373075011SMauro Carvalho Chehab val |= EYE_PARM4_EN;
27473075011SMauro Carvalho Chehab }
27573075011SMauro Carvalho Chehab kirin_apb_natural_phy_writel(phy, val, LANEN_DIG_ASIC_TX_OVRD_IN_1);
27673075011SMauro Carvalho Chehab }
27773075011SMauro Carvalho Chehab
hi3670_pcie_natural_cfg(struct hi3670_pcie_phy * phy)27873075011SMauro Carvalho Chehab static void hi3670_pcie_natural_cfg(struct hi3670_pcie_phy *phy)
27973075011SMauro Carvalho Chehab {
28073075011SMauro Carvalho Chehab u32 val;
28173075011SMauro Carvalho Chehab
28273075011SMauro Carvalho Chehab /* change 2p mem_ctrl */
28373075011SMauro Carvalho Chehab regmap_write(phy->apb, SOC_PCIECTRL_CTRL20_ADDR,
28473075011SMauro Carvalho Chehab SOC_PCIECTRL_CTRL20_2P_MEM_CTRL);
28573075011SMauro Carvalho Chehab
28673075011SMauro Carvalho Chehab regmap_read(phy->apb, SOC_PCIECTRL_CTRL7_ADDR, &val);
28773075011SMauro Carvalho Chehab val |= PCIE_PULL_UP_SYS_AUX_PWR_DET;
28873075011SMauro Carvalho Chehab regmap_write(phy->apb, SOC_PCIECTRL_CTRL7_ADDR, val);
28973075011SMauro Carvalho Chehab
29073075011SMauro Carvalho Chehab /* output, pull down */
29173075011SMauro Carvalho Chehab regmap_read(phy->apb, SOC_PCIECTRL_CTRL12_ADDR, &val);
29273075011SMauro Carvalho Chehab val &= ~PCIE_OUTPUT_PULL_BITS;
29373075011SMauro Carvalho Chehab val |= PCIE_OUTPUT_PULL_DOWN;
29473075011SMauro Carvalho Chehab regmap_write(phy->apb, SOC_PCIECTRL_CTRL12_ADDR, val);
29573075011SMauro Carvalho Chehab
29673075011SMauro Carvalho Chehab /* Handle phy_reset and lane0_reset to HW */
29773075011SMauro Carvalho Chehab hi3670_apb_phy_updatel(phy, PCIEPHY_RESET_BIT,
29873075011SMauro Carvalho Chehab PCIEPHY_PIPE_LINE0_RESET_BIT | PCIEPHY_RESET_BIT,
29973075011SMauro Carvalho Chehab SOC_PCIEPHY_CTRL1_ADDR);
30073075011SMauro Carvalho Chehab
30173075011SMauro Carvalho Chehab /* fix chip bug: TxDetectRx fail */
30273075011SMauro Carvalho Chehab hi3670_apb_phy_updatel(phy, PCIE_TXDETECT_RX_FAIL, PCIE_TXDETECT_RX_FAIL,
30373075011SMauro Carvalho Chehab SOC_PCIEPHY_CTRL38_ADDR);
30473075011SMauro Carvalho Chehab }
30573075011SMauro Carvalho Chehab
hi3670_pcie_pll_init(struct hi3670_pcie_phy * phy)30673075011SMauro Carvalho Chehab static void hi3670_pcie_pll_init(struct hi3670_pcie_phy *phy)
30773075011SMauro Carvalho Chehab {
30873075011SMauro Carvalho Chehab hi3670_apb_phy_updatel(phy, PCIE_PHY_CHOOSE_FNPLL, PCIE_PHY_CHOOSE_FNPLL,
30973075011SMauro Carvalho Chehab SOC_PCIEPHY_MMC1PLL_CTRL1);
31073075011SMauro Carvalho Chehab
31173075011SMauro Carvalho Chehab hi3670_apb_phy_updatel(phy,
31273075011SMauro Carvalho Chehab FIELD_PREP(PCIE_FNPLL_FBDIV_MASK, PCIE_FNPLL_FBDIV),
31373075011SMauro Carvalho Chehab PCIE_FNPLL_FBDIV_MASK,
31473075011SMauro Carvalho Chehab SOC_PCIEPHY_MMC1PLL_CTRL16);
31573075011SMauro Carvalho Chehab
31673075011SMauro Carvalho Chehab hi3670_apb_phy_updatel(phy,
31773075011SMauro Carvalho Chehab FIELD_PREP(PCIE_FNPLL_FRACDIV_MASK, PCIE_FNPLL_FRACDIV),
31873075011SMauro Carvalho Chehab PCIE_FNPLL_FRACDIV_MASK, SOC_PCIEPHY_MMC1PLL_CTRL17);
31973075011SMauro Carvalho Chehab
32073075011SMauro Carvalho Chehab hi3670_apb_phy_updatel(phy,
32173075011SMauro Carvalho Chehab PCIE_FNPLL_DLL_EN |
32273075011SMauro Carvalho Chehab FIELD_PREP(PCIE_FNPLL_POSTDIV1_MASK, PCIE_FNPLL_POSTDIV1) |
32373075011SMauro Carvalho Chehab FIELD_PREP(PCIE_FNPLL_POSTDIV2_MASK, PCIE_FNPLL_POSTDIV2) |
32473075011SMauro Carvalho Chehab FIELD_PREP(PCIE_FNPLL_PLL_MODE_MASK, PCIE_FNPLL_PLL_MODE),
32573075011SMauro Carvalho Chehab PCIE_FNPLL_POSTDIV1_MASK |
32673075011SMauro Carvalho Chehab PCIE_FNPLL_POSTDIV2_MASK |
32773075011SMauro Carvalho Chehab PCIE_FNPLL_PLL_MODE_MASK | PCIE_FNPLL_DLL_EN,
32873075011SMauro Carvalho Chehab SOC_PCIEPHY_MMC1PLL_CTRL20);
32973075011SMauro Carvalho Chehab
33073075011SMauro Carvalho Chehab hi3670_apb_phy_writel(phy, PCIE_PHY_MMC1PLL,
33173075011SMauro Carvalho Chehab SOC_PCIEPHY_MMC1PLL_CTRL21);
33273075011SMauro Carvalho Chehab }
33373075011SMauro Carvalho Chehab
hi3670_pcie_pll_ctrl(struct hi3670_pcie_phy * phy,bool enable)33473075011SMauro Carvalho Chehab static int hi3670_pcie_pll_ctrl(struct hi3670_pcie_phy *phy, bool enable)
33573075011SMauro Carvalho Chehab {
33673075011SMauro Carvalho Chehab struct device *dev = phy->dev;
33773075011SMauro Carvalho Chehab u32 val;
33873075011SMauro Carvalho Chehab int time = PLL_CTRL_WAIT_TIME;
33973075011SMauro Carvalho Chehab
34073075011SMauro Carvalho Chehab if (enable) {
34173075011SMauro Carvalho Chehab /* pd = 0 */
34273075011SMauro Carvalho Chehab hi3670_apb_phy_updatel(phy, 0, PCIE_PHY_MMC1PLL_DISABLE,
34373075011SMauro Carvalho Chehab SOC_PCIEPHY_MMC1PLL_CTRL16);
34473075011SMauro Carvalho Chehab
34573075011SMauro Carvalho Chehab /* choose FNPLL */
34673075011SMauro Carvalho Chehab val = hi3670_apb_phy_readl(phy, SOC_PCIEPHY_MMC1PLL_STAT0);
34773075011SMauro Carvalho Chehab while (!(val & FNPLL_HAS_LOCKED)) {
34873075011SMauro Carvalho Chehab if (!time) {
34973075011SMauro Carvalho Chehab dev_err(dev, "wait for pll_lock timeout\n");
35073075011SMauro Carvalho Chehab return -EINVAL;
35173075011SMauro Carvalho Chehab }
35273075011SMauro Carvalho Chehab time--;
35373075011SMauro Carvalho Chehab udelay(1);
35473075011SMauro Carvalho Chehab val = hi3670_apb_phy_readl(phy, SOC_PCIEPHY_MMC1PLL_STAT0);
35573075011SMauro Carvalho Chehab }
35673075011SMauro Carvalho Chehab
35773075011SMauro Carvalho Chehab hi3670_apb_phy_updatel(phy, 0, PCIE_PHY_PCIEPL_BP,
35873075011SMauro Carvalho Chehab SOC_PCIEPHY_MMC1PLL_CTRL20);
35973075011SMauro Carvalho Chehab
36073075011SMauro Carvalho Chehab } else {
36173075011SMauro Carvalho Chehab hi3670_apb_phy_updatel(phy,
36273075011SMauro Carvalho Chehab PCIE_PHY_MMC1PLL_DISABLE,
36373075011SMauro Carvalho Chehab PCIE_PHY_MMC1PLL_DISABLE,
36473075011SMauro Carvalho Chehab SOC_PCIEPHY_MMC1PLL_CTRL16);
36573075011SMauro Carvalho Chehab
36673075011SMauro Carvalho Chehab hi3670_apb_phy_updatel(phy, PCIE_PHY_PCIEPL_BP,
36773075011SMauro Carvalho Chehab PCIE_PHY_PCIEPL_BP,
36873075011SMauro Carvalho Chehab SOC_PCIEPHY_MMC1PLL_CTRL20);
36973075011SMauro Carvalho Chehab }
37073075011SMauro Carvalho Chehab
37173075011SMauro Carvalho Chehab return 0;
37273075011SMauro Carvalho Chehab }
37373075011SMauro Carvalho Chehab
hi3670_pcie_hp_debounce_gt(struct hi3670_pcie_phy * phy,bool open)37473075011SMauro Carvalho Chehab static void hi3670_pcie_hp_debounce_gt(struct hi3670_pcie_phy *phy, bool open)
37573075011SMauro Carvalho Chehab {
37673075011SMauro Carvalho Chehab if (open)
37773075011SMauro Carvalho Chehab /* gt_clk_pcie_hp/gt_clk_pcie_debounce open */
37873075011SMauro Carvalho Chehab regmap_write(phy->crgctrl, CRGPERIPH_PEREN12,
37973075011SMauro Carvalho Chehab IO_HP_DEBOUNCE_GT);
38073075011SMauro Carvalho Chehab else
38173075011SMauro Carvalho Chehab /* gt_clk_pcie_hp/gt_clk_pcie_debounce close */
38273075011SMauro Carvalho Chehab regmap_write(phy->crgctrl, CRGPERIPH_PERDIS12,
38373075011SMauro Carvalho Chehab IO_HP_DEBOUNCE_GT);
38473075011SMauro Carvalho Chehab }
38573075011SMauro Carvalho Chehab
hi3670_pcie_phyref_gt(struct hi3670_pcie_phy * phy,bool open)38673075011SMauro Carvalho Chehab static void hi3670_pcie_phyref_gt(struct hi3670_pcie_phy *phy, bool open)
38773075011SMauro Carvalho Chehab {
38873075011SMauro Carvalho Chehab unsigned int val;
38973075011SMauro Carvalho Chehab
39073075011SMauro Carvalho Chehab regmap_read(phy->crgctrl, CRGPERIPH_PCIECTRL0, &val);
39173075011SMauro Carvalho Chehab
39273075011SMauro Carvalho Chehab if (open)
39373075011SMauro Carvalho Chehab val &= ~IO_OE_HARD_GT_MODE; /* enable hard gt mode */
39473075011SMauro Carvalho Chehab else
39573075011SMauro Carvalho Chehab val |= IO_OE_HARD_GT_MODE; /* disable hard gt mode */
39673075011SMauro Carvalho Chehab
39773075011SMauro Carvalho Chehab regmap_write(phy->crgctrl, CRGPERIPH_PCIECTRL0, val);
39873075011SMauro Carvalho Chehab
39973075011SMauro Carvalho Chehab /* disable soft gt mode */
40073075011SMauro Carvalho Chehab regmap_write(phy->crgctrl, CRGPERIPH_PERDIS12, IO_PHYREF_SOFT_GT_MODE);
40173075011SMauro Carvalho Chehab }
40273075011SMauro Carvalho Chehab
hi3670_pcie_oe_ctrl(struct hi3670_pcie_phy * phy,bool en_flag)40373075011SMauro Carvalho Chehab static void hi3670_pcie_oe_ctrl(struct hi3670_pcie_phy *phy, bool en_flag)
40473075011SMauro Carvalho Chehab {
40573075011SMauro Carvalho Chehab unsigned int val;
40673075011SMauro Carvalho Chehab
40773075011SMauro Carvalho Chehab regmap_read(phy->crgctrl, CRGPERIPH_PCIECTRL0, &val);
40873075011SMauro Carvalho Chehab
40973075011SMauro Carvalho Chehab /* set ie cfg */
41073075011SMauro Carvalho Chehab val |= IO_IE_EN_HARD_BYPASS;
41173075011SMauro Carvalho Chehab
41273075011SMauro Carvalho Chehab /* set oe cfg */
41373075011SMauro Carvalho Chehab val &= ~IO_HARD_CTRL_DEBOUNCE_BYPASS;
41473075011SMauro Carvalho Chehab
41573075011SMauro Carvalho Chehab /* set phy_debounce in&out time */
41673075011SMauro Carvalho Chehab val |= (DEBOUNCE_WAITCFG_IN | DEBOUNCE_WAITCFG_OUT);
41773075011SMauro Carvalho Chehab
41873075011SMauro Carvalho Chehab /* select oe_gt_mode */
41973075011SMauro Carvalho Chehab val |= IO_OE_GT_MODE;
42073075011SMauro Carvalho Chehab
42173075011SMauro Carvalho Chehab if (en_flag)
42273075011SMauro Carvalho Chehab val &= ~IO_OE_EN_HARD_BYPASS;
42373075011SMauro Carvalho Chehab else
42473075011SMauro Carvalho Chehab val |= IO_OE_EN_HARD_BYPASS;
42573075011SMauro Carvalho Chehab
42673075011SMauro Carvalho Chehab regmap_write(phy->crgctrl, CRGPERIPH_PCIECTRL0, val);
42773075011SMauro Carvalho Chehab }
42873075011SMauro Carvalho Chehab
hi3670_pcie_ioref_gt(struct hi3670_pcie_phy * phy,bool open)42973075011SMauro Carvalho Chehab static void hi3670_pcie_ioref_gt(struct hi3670_pcie_phy *phy, bool open)
43073075011SMauro Carvalho Chehab {
43173075011SMauro Carvalho Chehab unsigned int val;
43273075011SMauro Carvalho Chehab
43373075011SMauro Carvalho Chehab if (open) {
43473075011SMauro Carvalho Chehab regmap_write(phy->apb, SOC_PCIECTRL_CTRL21_ADDR,
43573075011SMauro Carvalho Chehab SOC_PCIECTRL_CTRL21_DEFAULT);
43673075011SMauro Carvalho Chehab
43773075011SMauro Carvalho Chehab hi3670_pcie_oe_ctrl(phy, true);
43873075011SMauro Carvalho Chehab
43973075011SMauro Carvalho Chehab /* en hard gt mode */
44073075011SMauro Carvalho Chehab regmap_read(phy->crgctrl, CRGPERIPH_PCIECTRL0, &val);
44173075011SMauro Carvalho Chehab val &= ~IO_REF_HARD_GT_MODE;
44273075011SMauro Carvalho Chehab regmap_write(phy->crgctrl, CRGPERIPH_PCIECTRL0, val);
44373075011SMauro Carvalho Chehab
44473075011SMauro Carvalho Chehab /* disable soft gt mode */
44573075011SMauro Carvalho Chehab regmap_write(phy->crgctrl, CRGPERIPH_PERDIS12,
44673075011SMauro Carvalho Chehab IO_REF_SOFT_GT_MODE);
44773075011SMauro Carvalho Chehab
44873075011SMauro Carvalho Chehab } else {
44973075011SMauro Carvalho Chehab /* disable hard gt mode */
45073075011SMauro Carvalho Chehab regmap_read(phy->crgctrl, CRGPERIPH_PCIECTRL0, &val);
45173075011SMauro Carvalho Chehab val |= IO_REF_HARD_GT_MODE;
45273075011SMauro Carvalho Chehab regmap_write(phy->crgctrl, CRGPERIPH_PCIECTRL0, val);
45373075011SMauro Carvalho Chehab
45473075011SMauro Carvalho Chehab /* disable soft gt mode */
45573075011SMauro Carvalho Chehab regmap_write(phy->crgctrl, CRGPERIPH_PERDIS12,
45673075011SMauro Carvalho Chehab IO_REF_SOFT_GT_MODE);
45773075011SMauro Carvalho Chehab
45873075011SMauro Carvalho Chehab hi3670_pcie_oe_ctrl(phy, false);
45973075011SMauro Carvalho Chehab }
46073075011SMauro Carvalho Chehab }
46173075011SMauro Carvalho Chehab
hi3670_pcie_allclk_ctrl(struct hi3670_pcie_phy * phy,bool clk_on)46273075011SMauro Carvalho Chehab static int hi3670_pcie_allclk_ctrl(struct hi3670_pcie_phy *phy, bool clk_on)
46373075011SMauro Carvalho Chehab {
46473075011SMauro Carvalho Chehab struct device *dev = phy->dev;
46573075011SMauro Carvalho Chehab int ret = 0;
46673075011SMauro Carvalho Chehab
46773075011SMauro Carvalho Chehab if (!clk_on)
46873075011SMauro Carvalho Chehab goto close_clocks;
46973075011SMauro Carvalho Chehab
47073075011SMauro Carvalho Chehab /* choose 100MHz clk src: Bit[8]==1 pad, Bit[8]==0 pll */
47173075011SMauro Carvalho Chehab hi3670_apb_phy_updatel(phy, 0, PCIE_CLK_SOURCE,
47273075011SMauro Carvalho Chehab SOC_PCIEPHY_CTRL1_ADDR);
47373075011SMauro Carvalho Chehab
47473075011SMauro Carvalho Chehab hi3670_pcie_pll_init(phy);
47573075011SMauro Carvalho Chehab
47673075011SMauro Carvalho Chehab ret = hi3670_pcie_pll_ctrl(phy, true);
47773075011SMauro Carvalho Chehab if (ret) {
47873075011SMauro Carvalho Chehab dev_err(dev, "Failed to enable pll\n");
47973075011SMauro Carvalho Chehab return -EINVAL;
48073075011SMauro Carvalho Chehab }
48173075011SMauro Carvalho Chehab hi3670_pcie_hp_debounce_gt(phy, true);
48273075011SMauro Carvalho Chehab hi3670_pcie_phyref_gt(phy, true);
48373075011SMauro Carvalho Chehab hi3670_pcie_ioref_gt(phy, true);
48473075011SMauro Carvalho Chehab
48573075011SMauro Carvalho Chehab ret = clk_set_rate(phy->aclk, AXI_CLK_FREQ);
48673075011SMauro Carvalho Chehab if (ret) {
48773075011SMauro Carvalho Chehab dev_err(dev, "Failed to set rate\n");
48873075011SMauro Carvalho Chehab goto close_clocks;
48973075011SMauro Carvalho Chehab }
49073075011SMauro Carvalho Chehab
49173075011SMauro Carvalho Chehab return 0;
49273075011SMauro Carvalho Chehab
49373075011SMauro Carvalho Chehab close_clocks:
49473075011SMauro Carvalho Chehab hi3670_pcie_ioref_gt(phy, false);
49573075011SMauro Carvalho Chehab hi3670_pcie_phyref_gt(phy, false);
49673075011SMauro Carvalho Chehab hi3670_pcie_hp_debounce_gt(phy, false);
49773075011SMauro Carvalho Chehab
49873075011SMauro Carvalho Chehab hi3670_pcie_pll_ctrl(phy, false);
49973075011SMauro Carvalho Chehab
50073075011SMauro Carvalho Chehab return ret;
50173075011SMauro Carvalho Chehab }
50273075011SMauro Carvalho Chehab
is_pipe_clk_stable(struct hi3670_pcie_phy * phy)50373075011SMauro Carvalho Chehab static bool is_pipe_clk_stable(struct hi3670_pcie_phy *phy)
50473075011SMauro Carvalho Chehab {
50573075011SMauro Carvalho Chehab struct device *dev = phy->dev;
50673075011SMauro Carvalho Chehab u32 val;
50773075011SMauro Carvalho Chehab u32 time = PIPE_CLK_STABLE_TIME;
50873075011SMauro Carvalho Chehab u32 pipe_clk_stable = PCIE_IS_CLOCK_STABLE;
50973075011SMauro Carvalho Chehab
51073075011SMauro Carvalho Chehab val = hi3670_apb_phy_readl(phy, SOC_PCIEPHY_STATE0_ADDR);
51173075011SMauro Carvalho Chehab while (val & pipe_clk_stable) {
51273075011SMauro Carvalho Chehab mdelay(1);
51373075011SMauro Carvalho Chehab if (!time) {
51473075011SMauro Carvalho Chehab dev_err(dev, "PIPE clk is not stable\n");
51573075011SMauro Carvalho Chehab return false;
51673075011SMauro Carvalho Chehab }
51773075011SMauro Carvalho Chehab time--;
51873075011SMauro Carvalho Chehab val = hi3670_apb_phy_readl(phy, SOC_PCIEPHY_STATE0_ADDR);
51973075011SMauro Carvalho Chehab }
52073075011SMauro Carvalho Chehab
52173075011SMauro Carvalho Chehab return true;
52273075011SMauro Carvalho Chehab }
52373075011SMauro Carvalho Chehab
hi3670_pcie_noc_power(struct hi3670_pcie_phy * phy,bool enable)52473075011SMauro Carvalho Chehab static int hi3670_pcie_noc_power(struct hi3670_pcie_phy *phy, bool enable)
52573075011SMauro Carvalho Chehab {
52673075011SMauro Carvalho Chehab struct device *dev = phy->dev;
52773075011SMauro Carvalho Chehab u32 time = NOC_POWER_TIME;
52873075011SMauro Carvalho Chehab unsigned int val = NOC_PW_MASK;
52973075011SMauro Carvalho Chehab int rst;
53073075011SMauro Carvalho Chehab
53173075011SMauro Carvalho Chehab if (enable)
53273075011SMauro Carvalho Chehab val = NOC_PW_MASK | NOC_PW_SET_BIT;
53373075011SMauro Carvalho Chehab else
53473075011SMauro Carvalho Chehab val = NOC_PW_MASK;
53573075011SMauro Carvalho Chehab rst = enable ? 1 : 0;
53673075011SMauro Carvalho Chehab
53773075011SMauro Carvalho Chehab regmap_write(phy->pmctrl, NOC_POWER_IDLEREQ_1, val);
53873075011SMauro Carvalho Chehab
53973075011SMauro Carvalho Chehab time = NOC_POWER_TIME;
54073075011SMauro Carvalho Chehab regmap_read(phy->pmctrl, NOC_POWER_IDLE_1, &val);
54173075011SMauro Carvalho Chehab while ((val & NOC_PW_SET_BIT) != rst) {
54273075011SMauro Carvalho Chehab udelay(10);
54373075011SMauro Carvalho Chehab if (!time) {
54473075011SMauro Carvalho Chehab dev_err(dev, "Failed to reverse noc power-status\n");
54573075011SMauro Carvalho Chehab return -EINVAL;
54673075011SMauro Carvalho Chehab }
54773075011SMauro Carvalho Chehab time--;
54873075011SMauro Carvalho Chehab regmap_read(phy->pmctrl, NOC_POWER_IDLE_1, &val);
54973075011SMauro Carvalho Chehab }
55073075011SMauro Carvalho Chehab
55173075011SMauro Carvalho Chehab return 0;
55273075011SMauro Carvalho Chehab }
55373075011SMauro Carvalho Chehab
hi3670_pcie_get_resources_from_pcie(struct hi3670_pcie_phy * phy)55473075011SMauro Carvalho Chehab static int hi3670_pcie_get_resources_from_pcie(struct hi3670_pcie_phy *phy)
55573075011SMauro Carvalho Chehab {
55673075011SMauro Carvalho Chehab struct device_node *pcie_port;
55773075011SMauro Carvalho Chehab struct device *dev = phy->dev;
55873075011SMauro Carvalho Chehab struct device *pcie_dev;
55973075011SMauro Carvalho Chehab
56073075011SMauro Carvalho Chehab pcie_port = of_get_child_by_name(dev->parent->of_node, "pcie");
56173075011SMauro Carvalho Chehab if (!pcie_port) {
56273075011SMauro Carvalho Chehab dev_err(dev, "no pcie node found in %s\n",
56373075011SMauro Carvalho Chehab dev->parent->of_node->full_name);
56473075011SMauro Carvalho Chehab return -ENODEV;
56573075011SMauro Carvalho Chehab }
56673075011SMauro Carvalho Chehab
56773075011SMauro Carvalho Chehab pcie_dev = bus_find_device_by_of_node(&platform_bus_type, pcie_port);
56873075011SMauro Carvalho Chehab if (!pcie_dev) {
56973075011SMauro Carvalho Chehab dev_err(dev, "Didn't find pcie device\n");
57073075011SMauro Carvalho Chehab return -ENODEV;
57173075011SMauro Carvalho Chehab }
57273075011SMauro Carvalho Chehab
57373075011SMauro Carvalho Chehab /*
57473075011SMauro Carvalho Chehab * We might just use NULL instead of the APB name, as the
57573075011SMauro Carvalho Chehab * pcie-kirin currently registers directly just one regmap (although
57673075011SMauro Carvalho Chehab * the DWC driver register other regmaps).
57773075011SMauro Carvalho Chehab *
57873075011SMauro Carvalho Chehab * Yet, it sounds safer to warrant that it will be accessing the
57973075011SMauro Carvalho Chehab * right regmap. So, let's use the named version.
58073075011SMauro Carvalho Chehab */
58173075011SMauro Carvalho Chehab phy->apb = dev_get_regmap(pcie_dev, "kirin_pcie_apb");
58273075011SMauro Carvalho Chehab if (!phy->apb) {
58373075011SMauro Carvalho Chehab dev_err(dev, "Failed to get APB regmap\n");
58473075011SMauro Carvalho Chehab return -ENODEV;
58573075011SMauro Carvalho Chehab }
58673075011SMauro Carvalho Chehab
58773075011SMauro Carvalho Chehab return 0;
58873075011SMauro Carvalho Chehab }
58973075011SMauro Carvalho Chehab
kirin_pcie_clk_ctrl(struct hi3670_pcie_phy * phy,bool enable)59073075011SMauro Carvalho Chehab static int kirin_pcie_clk_ctrl(struct hi3670_pcie_phy *phy, bool enable)
59173075011SMauro Carvalho Chehab {
59273075011SMauro Carvalho Chehab int ret = 0;
59373075011SMauro Carvalho Chehab
59473075011SMauro Carvalho Chehab if (!enable)
59573075011SMauro Carvalho Chehab goto close_clk;
59673075011SMauro Carvalho Chehab
59773075011SMauro Carvalho Chehab ret = clk_set_rate(phy->phy_ref_clk, REF_CLK_FREQ);
59873075011SMauro Carvalho Chehab if (ret)
59973075011SMauro Carvalho Chehab return ret;
60073075011SMauro Carvalho Chehab
60173075011SMauro Carvalho Chehab ret = clk_prepare_enable(phy->phy_ref_clk);
60273075011SMauro Carvalho Chehab if (ret)
60373075011SMauro Carvalho Chehab return ret;
60473075011SMauro Carvalho Chehab
60573075011SMauro Carvalho Chehab ret = clk_prepare_enable(phy->apb_sys_clk);
60673075011SMauro Carvalho Chehab if (ret)
60773075011SMauro Carvalho Chehab goto apb_sys_fail;
60873075011SMauro Carvalho Chehab
60973075011SMauro Carvalho Chehab ret = clk_prepare_enable(phy->apb_phy_clk);
61073075011SMauro Carvalho Chehab if (ret)
61173075011SMauro Carvalho Chehab goto apb_phy_fail;
61273075011SMauro Carvalho Chehab
61373075011SMauro Carvalho Chehab ret = clk_prepare_enable(phy->aclk);
61473075011SMauro Carvalho Chehab if (ret)
61573075011SMauro Carvalho Chehab goto aclk_fail;
61673075011SMauro Carvalho Chehab
61773075011SMauro Carvalho Chehab ret = clk_prepare_enable(phy->aux_clk);
61873075011SMauro Carvalho Chehab if (ret)
61973075011SMauro Carvalho Chehab goto aux_clk_fail;
62073075011SMauro Carvalho Chehab
62173075011SMauro Carvalho Chehab return 0;
62273075011SMauro Carvalho Chehab
62373075011SMauro Carvalho Chehab close_clk:
62473075011SMauro Carvalho Chehab clk_disable_unprepare(phy->aux_clk);
62573075011SMauro Carvalho Chehab aux_clk_fail:
62673075011SMauro Carvalho Chehab clk_disable_unprepare(phy->aclk);
62773075011SMauro Carvalho Chehab aclk_fail:
62873075011SMauro Carvalho Chehab clk_disable_unprepare(phy->apb_phy_clk);
62973075011SMauro Carvalho Chehab apb_phy_fail:
63073075011SMauro Carvalho Chehab clk_disable_unprepare(phy->apb_sys_clk);
63173075011SMauro Carvalho Chehab apb_sys_fail:
63273075011SMauro Carvalho Chehab clk_disable_unprepare(phy->phy_ref_clk);
63373075011SMauro Carvalho Chehab
63473075011SMauro Carvalho Chehab return ret;
63573075011SMauro Carvalho Chehab }
63673075011SMauro Carvalho Chehab
hi3670_pcie_phy_init(struct phy * generic_phy)63773075011SMauro Carvalho Chehab static int hi3670_pcie_phy_init(struct phy *generic_phy)
63873075011SMauro Carvalho Chehab {
63973075011SMauro Carvalho Chehab struct hi3670_pcie_phy *phy = phy_get_drvdata(generic_phy);
64073075011SMauro Carvalho Chehab int ret;
64173075011SMauro Carvalho Chehab
64273075011SMauro Carvalho Chehab /*
64373075011SMauro Carvalho Chehab * The code under hi3670_pcie_get_resources_from_pcie() need to
64473075011SMauro Carvalho Chehab * access the reset-gpios and the APB registers, both from the
64573075011SMauro Carvalho Chehab * pcie-kirin driver.
64673075011SMauro Carvalho Chehab *
64773075011SMauro Carvalho Chehab * The APB is obtained via the pcie driver's regmap
64873075011SMauro Carvalho Chehab * Such kind of resource can only be obtained during the PCIe
64973075011SMauro Carvalho Chehab * power_on sequence, as the code inside pcie-kirin needs to
65073075011SMauro Carvalho Chehab * be already probed, as it needs to register the APB regmap.
65173075011SMauro Carvalho Chehab */
65273075011SMauro Carvalho Chehab
65373075011SMauro Carvalho Chehab ret = hi3670_pcie_get_resources_from_pcie(phy);
65473075011SMauro Carvalho Chehab if (ret)
65573075011SMauro Carvalho Chehab return ret;
65673075011SMauro Carvalho Chehab
65773075011SMauro Carvalho Chehab return 0;
65873075011SMauro Carvalho Chehab }
65973075011SMauro Carvalho Chehab
hi3670_pcie_phy_power_on(struct phy * generic_phy)66073075011SMauro Carvalho Chehab static int hi3670_pcie_phy_power_on(struct phy *generic_phy)
66173075011SMauro Carvalho Chehab {
66273075011SMauro Carvalho Chehab struct hi3670_pcie_phy *phy = phy_get_drvdata(generic_phy);
66373075011SMauro Carvalho Chehab int val, ret;
66473075011SMauro Carvalho Chehab
66573075011SMauro Carvalho Chehab /* Power supply for Host */
66673075011SMauro Carvalho Chehab regmap_write(phy->sysctrl, SCTRL_PCIE_CMOS_OFFSET, SCTRL_PCIE_CMOS_BIT);
66773075011SMauro Carvalho Chehab usleep_range(TIME_CMOS_MIN, TIME_CMOS_MAX);
66873075011SMauro Carvalho Chehab
66973075011SMauro Carvalho Chehab hi3670_pcie_phy_oe_enable(phy, true);
67073075011SMauro Carvalho Chehab
67173075011SMauro Carvalho Chehab ret = kirin_pcie_clk_ctrl(phy, true);
67273075011SMauro Carvalho Chehab if (ret)
67373075011SMauro Carvalho Chehab return ret;
67473075011SMauro Carvalho Chehab
67573075011SMauro Carvalho Chehab /* ISO disable, PCIeCtrl, PHY assert and clk gate clear */
67673075011SMauro Carvalho Chehab regmap_write(phy->sysctrl, SCTRL_PCIE_ISO_OFFSET, SCTRL_PCIE_ISO_BIT);
67773075011SMauro Carvalho Chehab regmap_write(phy->crgctrl, CRGCTRL_PCIE_ASSERT_OFFSET,
67873075011SMauro Carvalho Chehab CRGCTRL_PCIE_ASSERT_BIT);
67973075011SMauro Carvalho Chehab regmap_write(phy->sysctrl, SCTRL_PCIE_HPCLK_OFFSET,
68073075011SMauro Carvalho Chehab SCTRL_PCIE_HPCLK_BIT);
68173075011SMauro Carvalho Chehab
68273075011SMauro Carvalho Chehab hi3670_pcie_natural_cfg(phy);
68373075011SMauro Carvalho Chehab
68473075011SMauro Carvalho Chehab ret = hi3670_pcie_allclk_ctrl(phy, true);
68573075011SMauro Carvalho Chehab if (ret)
68673075011SMauro Carvalho Chehab goto disable_clks;
68773075011SMauro Carvalho Chehab
68873075011SMauro Carvalho Chehab /* pull down phy_test_powerdown signal */
68973075011SMauro Carvalho Chehab hi3670_apb_phy_updatel(phy, 0, PCIE_PULL_DOWN_PHY_TEST_POWERDOWN,
69073075011SMauro Carvalho Chehab SOC_PCIEPHY_CTRL0_ADDR);
69173075011SMauro Carvalho Chehab
69273075011SMauro Carvalho Chehab /* deassert controller perst_n */
69373075011SMauro Carvalho Chehab regmap_read(phy->apb, SOC_PCIECTRL_CTRL12_ADDR, &val);
69473075011SMauro Carvalho Chehab val |= PCIE_DEASSERT_CONTROLLER_PERST;
69573075011SMauro Carvalho Chehab regmap_write(phy->apb, SOC_PCIECTRL_CTRL12_ADDR, val);
69673075011SMauro Carvalho Chehab udelay(10);
69773075011SMauro Carvalho Chehab
69873075011SMauro Carvalho Chehab ret = is_pipe_clk_stable(phy);
69973075011SMauro Carvalho Chehab if (!ret)
70073075011SMauro Carvalho Chehab goto disable_clks;
70173075011SMauro Carvalho Chehab
70273075011SMauro Carvalho Chehab hi3670_pcie_set_eyeparam(phy);
70373075011SMauro Carvalho Chehab
70473075011SMauro Carvalho Chehab ret = hi3670_pcie_noc_power(phy, false);
70573075011SMauro Carvalho Chehab if (ret)
70673075011SMauro Carvalho Chehab goto disable_clks;
70773075011SMauro Carvalho Chehab
70873075011SMauro Carvalho Chehab return 0;
70973075011SMauro Carvalho Chehab
71073075011SMauro Carvalho Chehab disable_clks:
71173075011SMauro Carvalho Chehab kirin_pcie_clk_ctrl(phy, false);
71273075011SMauro Carvalho Chehab return ret;
71373075011SMauro Carvalho Chehab }
71473075011SMauro Carvalho Chehab
hi3670_pcie_phy_power_off(struct phy * generic_phy)71573075011SMauro Carvalho Chehab static int hi3670_pcie_phy_power_off(struct phy *generic_phy)
71673075011SMauro Carvalho Chehab {
71773075011SMauro Carvalho Chehab struct hi3670_pcie_phy *phy = phy_get_drvdata(generic_phy);
71873075011SMauro Carvalho Chehab
71973075011SMauro Carvalho Chehab hi3670_pcie_phy_oe_enable(phy, false);
72073075011SMauro Carvalho Chehab
72173075011SMauro Carvalho Chehab hi3670_pcie_allclk_ctrl(phy, false);
72273075011SMauro Carvalho Chehab
72373075011SMauro Carvalho Chehab /* Drop power supply for Host */
72473075011SMauro Carvalho Chehab regmap_write(phy->sysctrl, SCTRL_PCIE_CMOS_OFFSET, 0);
72573075011SMauro Carvalho Chehab
72673075011SMauro Carvalho Chehab /*
72773075011SMauro Carvalho Chehab * FIXME: The enabled clocks should be disabled here by calling
72873075011SMauro Carvalho Chehab * kirin_pcie_clk_ctrl(phy, false);
72973075011SMauro Carvalho Chehab * However, some clocks used at Kirin 970 should be marked as
73073075011SMauro Carvalho Chehab * CLK_IS_CRITICAL at clk-hi3670 driver, as powering such clocks off
73173075011SMauro Carvalho Chehab * cause an Asynchronous SError interrupt, which produces panic().
73273075011SMauro Carvalho Chehab * While clk-hi3670 is not fixed, we cannot risk disabling clocks here.
73373075011SMauro Carvalho Chehab */
73473075011SMauro Carvalho Chehab
73573075011SMauro Carvalho Chehab return 0;
73673075011SMauro Carvalho Chehab }
73773075011SMauro Carvalho Chehab
73873075011SMauro Carvalho Chehab static const struct phy_ops hi3670_phy_ops = {
73973075011SMauro Carvalho Chehab .init = hi3670_pcie_phy_init,
74073075011SMauro Carvalho Chehab .power_on = hi3670_pcie_phy_power_on,
74173075011SMauro Carvalho Chehab .power_off = hi3670_pcie_phy_power_off,
74273075011SMauro Carvalho Chehab .owner = THIS_MODULE,
74373075011SMauro Carvalho Chehab };
74473075011SMauro Carvalho Chehab
hi3670_pcie_phy_get_resources(struct hi3670_pcie_phy * phy,struct platform_device * pdev)74573075011SMauro Carvalho Chehab static int hi3670_pcie_phy_get_resources(struct hi3670_pcie_phy *phy,
74673075011SMauro Carvalho Chehab struct platform_device *pdev)
74773075011SMauro Carvalho Chehab {
74873075011SMauro Carvalho Chehab struct device *dev = &pdev->dev;
74973075011SMauro Carvalho Chehab
75073075011SMauro Carvalho Chehab /* syscon */
75173075011SMauro Carvalho Chehab phy->crgctrl = syscon_regmap_lookup_by_compatible("hisilicon,hi3670-crgctrl");
75273075011SMauro Carvalho Chehab if (IS_ERR(phy->crgctrl))
75373075011SMauro Carvalho Chehab return PTR_ERR(phy->crgctrl);
75473075011SMauro Carvalho Chehab
75573075011SMauro Carvalho Chehab phy->sysctrl = syscon_regmap_lookup_by_compatible("hisilicon,hi3670-sctrl");
75673075011SMauro Carvalho Chehab if (IS_ERR(phy->sysctrl))
75773075011SMauro Carvalho Chehab return PTR_ERR(phy->sysctrl);
75873075011SMauro Carvalho Chehab
75973075011SMauro Carvalho Chehab phy->pmctrl = syscon_regmap_lookup_by_compatible("hisilicon,hi3670-pmctrl");
760*f0ae8685SDan Carpenter if (IS_ERR(phy->pmctrl))
761*f0ae8685SDan Carpenter return PTR_ERR(phy->pmctrl);
76273075011SMauro Carvalho Chehab
76373075011SMauro Carvalho Chehab /* clocks */
76473075011SMauro Carvalho Chehab phy->phy_ref_clk = devm_clk_get(dev, "phy_ref");
76573075011SMauro Carvalho Chehab if (IS_ERR(phy->phy_ref_clk))
76673075011SMauro Carvalho Chehab return PTR_ERR(phy->phy_ref_clk);
76773075011SMauro Carvalho Chehab
76873075011SMauro Carvalho Chehab phy->aux_clk = devm_clk_get(dev, "aux");
76973075011SMauro Carvalho Chehab if (IS_ERR(phy->aux_clk))
77073075011SMauro Carvalho Chehab return PTR_ERR(phy->aux_clk);
77173075011SMauro Carvalho Chehab
77273075011SMauro Carvalho Chehab phy->apb_phy_clk = devm_clk_get(dev, "apb_phy");
77373075011SMauro Carvalho Chehab if (IS_ERR(phy->apb_phy_clk))
77473075011SMauro Carvalho Chehab return PTR_ERR(phy->apb_phy_clk);
77573075011SMauro Carvalho Chehab
77673075011SMauro Carvalho Chehab phy->apb_sys_clk = devm_clk_get(dev, "apb_sys");
77773075011SMauro Carvalho Chehab if (IS_ERR(phy->apb_sys_clk))
77873075011SMauro Carvalho Chehab return PTR_ERR(phy->apb_sys_clk);
77973075011SMauro Carvalho Chehab
78073075011SMauro Carvalho Chehab phy->aclk = devm_clk_get(dev, "aclk");
78173075011SMauro Carvalho Chehab if (IS_ERR(phy->aclk))
78273075011SMauro Carvalho Chehab return PTR_ERR(phy->aclk);
78373075011SMauro Carvalho Chehab
78473075011SMauro Carvalho Chehab /* registers */
78573075011SMauro Carvalho Chehab phy->base = devm_platform_ioremap_resource(pdev, 0);
78673075011SMauro Carvalho Chehab if (IS_ERR(phy->base))
78773075011SMauro Carvalho Chehab return PTR_ERR(phy->base);
78873075011SMauro Carvalho Chehab
78973075011SMauro Carvalho Chehab hi3670_pcie_get_eyeparam(phy);
79073075011SMauro Carvalho Chehab
79173075011SMauro Carvalho Chehab return 0;
79273075011SMauro Carvalho Chehab }
79373075011SMauro Carvalho Chehab
hi3670_pcie_phy_probe(struct platform_device * pdev)79473075011SMauro Carvalho Chehab static int hi3670_pcie_phy_probe(struct platform_device *pdev)
79573075011SMauro Carvalho Chehab {
79673075011SMauro Carvalho Chehab struct phy_provider *phy_provider;
79773075011SMauro Carvalho Chehab struct device *dev = &pdev->dev;
79873075011SMauro Carvalho Chehab struct hi3670_pcie_phy *phy;
79973075011SMauro Carvalho Chehab struct phy *generic_phy;
80073075011SMauro Carvalho Chehab int ret;
80173075011SMauro Carvalho Chehab
80273075011SMauro Carvalho Chehab phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
80373075011SMauro Carvalho Chehab if (!phy)
80473075011SMauro Carvalho Chehab return -ENOMEM;
80573075011SMauro Carvalho Chehab
80673075011SMauro Carvalho Chehab phy->dev = dev;
80773075011SMauro Carvalho Chehab
80873075011SMauro Carvalho Chehab ret = hi3670_pcie_phy_get_resources(phy, pdev);
80973075011SMauro Carvalho Chehab if (ret)
81073075011SMauro Carvalho Chehab return ret;
81173075011SMauro Carvalho Chehab
81273075011SMauro Carvalho Chehab generic_phy = devm_phy_create(dev, dev->of_node, &hi3670_phy_ops);
81373075011SMauro Carvalho Chehab if (IS_ERR(generic_phy)) {
81473075011SMauro Carvalho Chehab dev_err(dev, "failed to create PHY\n");
81573075011SMauro Carvalho Chehab return PTR_ERR(generic_phy);
81673075011SMauro Carvalho Chehab }
81773075011SMauro Carvalho Chehab
81873075011SMauro Carvalho Chehab phy_set_drvdata(generic_phy, phy);
81973075011SMauro Carvalho Chehab phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
82073075011SMauro Carvalho Chehab
82173075011SMauro Carvalho Chehab return PTR_ERR_OR_ZERO(phy_provider);
82273075011SMauro Carvalho Chehab }
82373075011SMauro Carvalho Chehab
82473075011SMauro Carvalho Chehab static const struct of_device_id hi3670_pcie_phy_match[] = {
82573075011SMauro Carvalho Chehab {
82673075011SMauro Carvalho Chehab .compatible = "hisilicon,hi970-pcie-phy",
82773075011SMauro Carvalho Chehab },
82873075011SMauro Carvalho Chehab {},
82973075011SMauro Carvalho Chehab };
83073075011SMauro Carvalho Chehab
83173075011SMauro Carvalho Chehab static struct platform_driver hi3670_pcie_phy_driver = {
83273075011SMauro Carvalho Chehab .probe = hi3670_pcie_phy_probe,
83373075011SMauro Carvalho Chehab .driver = {
83473075011SMauro Carvalho Chehab .of_match_table = hi3670_pcie_phy_match,
83573075011SMauro Carvalho Chehab .name = "hi3670_pcie_phy",
83673075011SMauro Carvalho Chehab .suppress_bind_attrs = true,
83773075011SMauro Carvalho Chehab }
83873075011SMauro Carvalho Chehab };
83973075011SMauro Carvalho Chehab builtin_platform_driver(hi3670_pcie_phy_driver);
84073075011SMauro Carvalho Chehab
84173075011SMauro Carvalho Chehab MODULE_DEVICE_TABLE(of, hi3670_pcie_phy_match);
84273075011SMauro Carvalho Chehab MODULE_DESCRIPTION("PCIe phy driver for Kirin 970");
84373075011SMauro Carvalho Chehab MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@kernel.org>");
84473075011SMauro Carvalho Chehab MODULE_AUTHOR("Manivannan Sadhasivam <mani@kernel.org>");
84573075011SMauro Carvalho Chehab MODULE_LICENSE("GPL v2");
846