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/openbmc/linux/Documentation/devicetree/bindings/soc/imx/
H A Dfsl,aips-bus.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,aips-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peng Fan <peng.fan@nxp.com>
14 AHB bus and peripherals with the lower bandwidth IP Slave (IPS)
21 const: fsl,aips-bus
23 - compatible
28 - const: fsl,aips-bus
29 - const: simple-bus
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dvf.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR X11
6 #include <dt-bindings/gpio/gpio.h>
28 #address-cells = <1>;
29 #size-cells = <1>;
30 compatible = "simple-bus";
33 aips0: aips-bus@40000000 {
34 compatible = "fsl,aips-bus", "simple-bus";
35 #address-cells = <1>;
36 #size-cells = <1>;
41 compatible = "fsl,vf610-lpuart";
[all …]
H A Dimx6qdl-u-boot.dtsi1 // SPDX-License-Identifier: GPL-2.0+
8 u-boot,dm-spl;
10 aips-bus@2000000 {
11 u-boot,dm-spl;
12 spba-bus@2000000 {
13 u-boot,dm-spl;
17 aips-bus@2100000 {
18 u-boot,dm-spl;
24 u-boot,dm-spl;
28 u-boot,dm-spl;
H A Dimx53.dtsi10 * http://www.opensource.org/licenses/gpl-license.html
15 #include "imx53-pinfunc.h"
16 #include <dt-bindings/clock/imx5-clock.h>
17 #include <dt-bindings/gpio/gpio.h>
18 #include <dt-bindings/input/input.h>
19 #include <dt-bindings/interrupt-controller/irq.h>
38 tzic: tz-interrupt-controller@fffc000 {
39 compatible = "fsl,imx53-tzic", "fsl,tzic";
40 interrupt-controller;
41 #interrupt-cells = <1>;
[all …]
H A Dimx7s.dtsi5 * This file is dual-licensed: you can use it either under the terms
44 #include <dt-bindings/clock/imx7d-clock.h>
45 #include <dt-bindings/power/imx7-power.h>
46 #include <dt-bindings/gpio/gpio.h>
47 #include <dt-bindings/input/input.h>
48 #include <dt-bindings/interrupt-controller/arm-gic.h>
49 #include "imx7d-pinfunc.h"
52 #address-cells = <1>;
53 #size-cells = <1>;
56 * pre-existing /chosen node to be available to insert the
[all …]
H A Dimx6sx.dtsi9 #include <dt-bindings/clock/imx6sx-clock.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include "imx6sx-pinfunc.h"
55 #address-cells = <1>;
56 #size-cells = <0>;
59 compatible = "arm,cortex-a9";
62 next-level-cache = <&L2>;
63 operating-points = <
[all …]
H A Dimx6ull.dtsi2 * Copyright 2015-2016 Freescale Semiconductor, Inc.
9 #include <dt-bindings/clock/imx6ul-clock.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include "imx6ull-pinfunc.h"
14 #include "imx6ull-pinfunc-snvs.h"
52 #address-cells = <1>;
53 #size-cells = <0>;
56 compatible = "arm,cortex-a7";
[all …]
H A Dimx6sll.dtsi9 #include <dt-bindings/clock/imx6sll-clock.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "imx6sll-pinfunc.h"
43 #address-cells = <1>;
44 #size-cells = <0>;
47 compatible = "arm,cortex-a9";
50 next-level-cache = <&L2>;
51 operating-points = <
58 fsl,soc-operating-points = <
[all …]
H A Dimx6ul.dtsi9 #include <dt-bindings/clock/imx6ul-clock.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include "imx6ul-pinfunc.h"
54 #address-cells = <1>;
55 #size-cells = <0>;
58 compatible = "arm,cortex-a7";
61 clock-latency = <61036>; /* two CLK32 periods */
62 operating-points = <
[all …]
H A Dimx6sl.dtsi10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include "imx6sl-pinfunc.h"
12 #include <dt-bindings/clock/imx6sl-clock.h>
15 #address-cells = <1>;
16 #size-cells = <1>;
19 * pre-existing /chosen node to be available to insert the
21 * Also for U-Boot there must be a pre-existing /memory node.
47 #address-cells = <1>;
48 #size-cells = <0>;
51 compatible = "arm,cortex-a9";
[all …]
H A Dimx6qp.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 compatible = "mmio-sram";
16 compatible = "mmio-sram";
21 aips-bus@2100000 {
23 compatible = "fsl,imx6qp-pre";
27 clock-names = "axi";
32 compatible = "fsl,imx6qp-pre";
36 clock-names = "axi";
41 compatible = "fsl,imx6qp-pre";
45 clock-names = "axi";
[all …]
H A Dimx6dl.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/interrupt-controller/irq.h>
6 #include "imx6dl-pinfunc.h"
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "arm,cortex-a9";
22 next-level-cache = <&L2>;
23 operating-points = <
29 fsl,soc-operating-points = <
30 /* ARM kHz SOC-PU uV */
[all …]
H A Dimx6qdl.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/imx6qdl-clock.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 * pre-existing /chosen node to be available to insert the
16 * Also for U-Boot there must be a pre-existing /memory node.
55 compatible = "fsl,imx-ckil", "fixed-clock";
56 #clock-cells = <0>;
57 clock-frequency = <32768>;
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6ull.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 #include "imx6ull-pinfunc.h"
7 #include "imx6ull-pinfunc-snvs.h"
9 /* Delete UART8 in AIPS-1 (i.MX6UL specific) */
10 /delete-node/ &uart8;
11 /* Delete CAAM node in AIPS-2 (i.MX6UL specific) */
12 /delete-node/ &crypto;
15 clock-frequency = <900000000>;
16 operating-points = <
24 fsl,soc-operating-points = <
[all …]
H A Dimx25.dtsi1 // SPDX-License-Identifier: GPL-2.0+
5 #include <dt-bindings/gpio/gpio.h>
6 #include "imx25-pinfunc.h"
9 #address-cells = <1>;
10 #size-cells = <1>;
13 * pre-existing /chosen node to be available to insert the
46 #address-cells = <1>;
47 #size-cells = <0>;
50 compatible = "arm,arm926ej-s";
56 asic: asic-interrupt-controller@68000000 {
[all …]
H A Dimx31.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 // Copyright 2016-2018 Vladimir Zapolskiy <vz@mleia.com>
4 // Copyright 2012 Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
7 #address-cells = <1>;
8 #size-cells = <1>;
11 * pre-existing /chosen node to be available to insert the
34 #address-cells = <1>;
35 #size-cells = <0>;
38 compatible = "arm,arm1136jf-s";
44 avic: interrupt-controller@68000000 {
[all …]
H A Dimx35.dtsi1 // SPDX-License-Identifier: GPL-2.0
7 #include "imx35-pinfunc.h"
10 #address-cells = <1>;
11 #size-cells = <1>;
14 * pre-existing /chosen node to be available to insert the
38 #address-cells = <1>;
39 #size-cells = <0>;
42 compatible = "arm,arm1136jf-s";
48 avic: avic-interrupt-controller@68000000 {
49 compatible = "fsl,imx35-avic", "fsl,avic";
[all …]
H A Dimx50.dtsi1 // SPDX-License-Identifier: GPL-2.0+
7 #include "imx50-pinfunc.h"
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/imx5-clock.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
16 * pre-existing /chosen node to be available to insert the
47 #address-cells = <1>;
48 #size-cells = <0>;
51 compatible = "arm,cortex-a8";
[all …]
/openbmc/qemu/include/hw/arm/
H A Dfsl-imx25.h4 * Copyright (C) 2015 Jean-Christophe Dubois <jcd@tribudubois.net>
36 #define TYPE_FSL_IMX25 "fsl-imx25"
82 * 0x43F0_0000 0x43F0_3FFF 16 Kbytes AIPS A control registers
89 * 0x43F8_0000 0x43F8_3FFF 16 Kbytes I2C-1
90 * 0x43F8_4000 0x43F8_7FFF 16 Kbytes I2C-3
91 * 0x43F8_8000 0x43F8_BFFF 16 Kbytes CAN-1
92 * 0x43F8_C000 0x43F8_FFFF 16 Kbytes CAN-2
93 * 0x43F9_0000 0x43F9_3FFF 16 Kbytes UART-1
94 * 0x43F9_4000 0x43F9_7FFF 16 Kbytes UART-2
95 * 0x43F9_8000 0x43F9_BFFF 16 Kbytes I2C-2
[all …]
/openbmc/linux/Documentation/devicetree/bindings/iio/dac/
H A Dfsl,vf610-dac.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/dac/fsl,vf610-dac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sanchayan Maity <maitysanchayan@gmail.com>
14 const: fsl,vf610-dac
25 clock-names:
29 - compatible
30 - reg
31 - interrupts
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-mx35/
H A Dimx-regs.h1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
22 * AIPS 1
49 * AIPS 2
139 #define _PLL_PD(x) (((x) - 1) << 26)
140 #define _PLL_MFD(x) (((x) - 1) << 16)
278 u32 cmp[3]; /* output compare 1-3 */
279 u32 capt[2]; /* input capture 1-2 */
312 /* Multi-Layer AHB Crossbar Switch (MAX) registers */
347 /* AHB <-> IP-Bus Interface (AIPS) */
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mn.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8mn-clock.h>
7 #include <dt-bindings/power/imx8mn-power.h>
8 #include <dt-bindings/reset/imx8mq-reset.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h>
14 #include "imx8mn-pinfunc.h"
17 interrupt-parent = <&gic>;
[all …]
H A Dimx93.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx93-clock.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/fsl,imx93-power.h>
11 #include <dt-bindings/thermal/thermal.h>
13 #include "imx93-pinfunc.h"
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
[all …]
/openbmc/u-boot/board/tqc/tqma6/
H A Dtqma6.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Author: Markus Niebel <markus.niebel@tq-group.com>
11 #include <asm/arch/mx6-pins.h>
12 #include <asm/arch/imx-regs.h>
18 #include <asm/mach-imx/mxc_i2c.h>
19 #include <asm/mach-imx/spi.h>
54 gd->ram_size = imx_ddr_size(); in dram_init()
79 * (U-Boot device node) (Physical Port)
90 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; in board_mmc_getcd()
93 if (cfg->esdhc_base == USDHC3_BASE_ADDR) in board_mmc_getcd()
[all …]
/openbmc/u-boot/board/phytec/pcl063/
H A Dspl.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
13 #include <asm/arch/mx6-ddr.h>
14 #include <asm/arch/mx6-pins.h>
18 /* Configuration for Micron MT41K256M16TW-107 IT:P, 32M x 16 x 8 -> 256MiB */
53 .dsize = 0, /* Bus size = 16bit */
88 writel(0xFFFFFFFF, &ccm->CCGR0); in ccgr_init()
89 writel(0xFFFFFFFF, &ccm->CCGR1); in ccgr_init()
90 writel(0xFFFFFFFF, &ccm->CCGR2); in ccgr_init()
91 writel(0xFFFFFFFF, &ccm->CCGR3); in ccgr_init()
[all …]

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