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Searched +full:ahb +full:- +full:addr +full:- +full:masks (Results 1 – 9 of 9) sorted by relevance

/openbmc/linux/Documentation/devicetree/bindings/dma/
H A Dst,stm32-mdma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/st,stm32-mdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The STM32 MDMA is a general-purpose direct memory access controller capable of
13 described in the dma.txt file, using a five-cell specifier for each channel:
22 -bit 0-1: Source increment mode
26 -bit 2-3: Destination increment mode
30 -bit 8-9: Source increment offset size
32 0x1: half-word (16bit)
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/openbmc/linux/drivers/soc/aspeed/
H A Daspeed-lpc-ctrl.c1 // SPDX-License-Identifier: GPL-2.0-or-later
17 #include <linux/aspeed-lpc-ctrl.h>
19 #define DEVICE_NAME "aspeed-lpc-ctrl"
45 return container_of(file->private_data, struct aspeed_lpc_ctrl, in file_aspeed_lpc_ctrl()
52 unsigned long vsize = vma->vm_end - vma->vm_start; in aspeed_lpc_ctrl_mmap()
53 pgprot_t prot = vma->vm_page_prot; in aspeed_lpc_ctrl_mmap()
55 if (vma->vm_pgoff + vma_pages(vma) > lpc_ctrl->mem_size >> PAGE_SHIFT) in aspeed_lpc_ctrl_mmap()
56 return -EINVAL; in aspeed_lpc_ctrl_mmap()
58 /* ast2400/2500 AHB accesses are not cache coherent */ in aspeed_lpc_ctrl_mmap()
61 if (remap_pfn_range(vma, vma->vm_start, in aspeed_lpc_ctrl_mmap()
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/openbmc/linux/drivers/usb/gadget/udc/aspeed-vhub/
H A Dvhub.h1 /* SPDX-License-Identifier: GPL-2.0+ */
83 /* EP ACK/NACK IRQ masks */
107 * per-device register definitions *
146 * per-endpoint register definitions *
213 #define AST_VHUB_NUM_GEN_EPs 15 /* Generic non-0 EPs */
233 /* A transfer request, either core-originated or internal */
242 * Desc number of the final packet or -1. For non-desc
315 /* Index in global pool (zero-based) */
345 /* Device index (zero-based) and name string */
402 /* Per-port info */
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/openbmc/linux/drivers/dma/
H A Dstm32-mdma.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Pierre-Yves Mordret <pierre-yves.mordret@st.com>
10 * Inspired by stm32-dma.c and dma-jz4780.c
17 #include <linux/dma-mapping.h>
33 #include "virt-dma.h"
265 return container_of(chan->vchan.chan.device, struct stm32_mdma_device, in stm32_mdma_get_dev()
281 return &chan->vchan.chan.dev->device; in chan2dev()
286 return mdma_dev->ddev.dev; in mdma2dev()
291 return readl_relaxed(dmadev->base + reg); in stm32_mdma_read()
296 writel_relaxed(val, dmadev->base + reg); in stm32_mdma_write()
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H A Dat_hdmac.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Driver for the Atmel AHB DMA Controller (aka HDMA or DMAC on AT91 systems)
8 * This supports the Atmel AHB DMA Controller found in several Atmel SoCs.
13 #include <dt-bindings/dma/at91.h>
18 #include <linux/dma-mapping.h>
29 #include "virt-dma.h"
33 * --------
35 * at_hdmac : Name of the ATmel AHB DMA Controller
44 #define AT_DMA_IF_BIGEND(i) BIT((i)) /* AHB-Lite Interface i in Big-endian mode */
99 #define ch_regs(x) (AT_DMA_CH_REGS_BASE + (x) * 0x28) /* Channel x base addr */
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H A Damba-pl08x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (c) 2010 ST-Ericsson SA
27 * - CH_CONFIG register at different offset,
28 * - separate CH_CONTROL2 register for transfer size,
29 * - bigger maximum transfer size,
30 * - 8-word aligned LLI, instead of 4-word, due to extra CCTL2 word,
31 * - no support for peripheral flow control.
45 * (Bursts are irrelevant for mem to mem transfers - there are no burst
46 * signals, the DMA controller will simply facilitate its AHB master.)
51 * - DMAC flow control: the transfer size defines the number of transfers
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/openbmc/u-boot/drivers/net/
H A Dzynq_gem.c1 // SPDX-License-Identifier: GPL-2.0+
81 #define ZYNQ_GEM_DMACR_BLENGTH 0x00000004 /* INCR4 AHB bursts */
114 * 0x0008: Auto-negotiation support
118 /* TX BD status masks */
130 u32 nwctrl; /* 0x0 - Network Control reg */
131 u32 nwcfg; /* 0x4 - Network Config reg */
132 u32 nwsr; /* 0x8 - Network Status reg */
134 u32 dmacr; /* 0x10 - DMA Control reg */
135 u32 txsr; /* 0x14 - TX Status reg */
136 u32 rxqbase; /* 0x18 - RX Q Base address reg */
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/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mq.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
7 #include <dt-bindings/clock/imx8mq-clock.h>
8 #include <dt-bindings/power/imx8mq-power.h>
9 #include <dt-bindings/reset/imx8mq-reset.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include "dt-bindings/input/input.h"
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include <dt-bindings/interconnect/imx8mq.h>
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/openbmc/linux/drivers/net/ethernet/stmicro/stmmac/
H A Dstmmac_main.c1 // SPDX-License-Identifier: GPL-2.0-only
3 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
6 Copyright(C) 2007-2011 STMicroelectronics Ltd
29 #include <linux/dma-mapping.h>
55 * with fine resolution and binary rollover. This avoid non-monotonic behavior
62 #define TSO_MAX_BUFF_SIZE (SZ_16K - 1)
70 static int debug = -1;
72 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
74 static int phyaddr = -1;
78 #define STMMAC_TX_THRESH(x) ((x)->dma_conf.dma_tx_size / 4)
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