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/openbmc/linux/drivers/thermal/qcom/
H A Dtsens.h88 #define REG_FIELD_FOR_EACH_SENSOR11(_name, _offset, _startbit, _stopbit) \ argument
89 [_name##_##0] = REG_FIELD(_offset, _startbit, _stopbit), \
90 [_name##_##1] = REG_FIELD(_offset + 4, _startbit, _stopbit), \
91 [_name##_##2] = REG_FIELD(_offset + 8, _startbit, _stopbit), \
92 [_name##_##3] = REG_FIELD(_offset + 12, _startbit, _stopbit), \
93 [_name##_##4] = REG_FIELD(_offset + 16, _startbit, _stopbit), \
94 [_name##_##5] = REG_FIELD(_offset + 20, _startbit, _stopbit), \
95 [_name##_##6] = REG_FIELD(_offset + 24, _startbit, _stopbit), \
96 [_name##_##7] = REG_FIELD(_offset + 28, _startbit, _stopbit), \
97 [_name##_##8] = REG_FIELD(_offset + 32, _startbit, _stopbit), \
[all …]
/openbmc/linux/drivers/net/ethernet/mellanox/mlxsw/
H A Dcore_acl_flex_keys.h56 #define MLXSW_AFK_ELEMENT_INFO(_type, _element, _offset, _shift, _size) \ argument
61 .offset = _offset, \
68 #define MLXSW_AFK_ELEMENT_INFO_U32(_element, _offset, _shift, _size) \ argument
70 _element, _offset, _shift, _size)
72 #define MLXSW_AFK_ELEMENT_INFO_BUF(_element, _offset, _size) \ argument
74 _element, _offset, 0, _size)
88 #define MLXSW_AFK_ELEMENT_INST(_type, _element, _offset, \ argument
94 .offset = _offset, \
103 #define MLXSW_AFK_ELEMENT_INST_U32(_element, _offset, _shift, _size) \ argument
105 _element, _offset, _shift, _size, 0, false)
[all …]
H A Ditem.h266 #define MLXSW_ITEM8(_type, _cname, _iname, _offset, _shift, _sizebits) \ argument
268 .offset = _offset, \
284 #define MLXSW_ITEM8_INDEXED(_type, _cname, _iname, _offset, _shift, _sizebits, \ argument
287 .offset = _offset, \
309 #define MLXSW_ITEM16(_type, _cname, _iname, _offset, _shift, _sizebits) \ argument
311 .offset = _offset, \
327 #define MLXSW_ITEM16_INDEXED(_type, _cname, _iname, _offset, _shift, _sizebits, \ argument
330 .offset = _offset, \
352 #define MLXSW_ITEM32(_type, _cname, _iname, _offset, _shift, _sizebits) \ argument
354 .offset = _offset, \
[all …]
/openbmc/linux/drivers/clk/bcm/
H A Dclk-kona.h91 #define POLICY(_offset, _bit) \ argument
93 .offset = (_offset), \
151 #define HW_SW_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ argument
153 .offset = (_offset), \
163 #define HW_SW_GATE_AUTO(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ argument
165 .offset = (_offset), \
174 #define HW_ENABLE_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ argument
176 .offset = (_offset), \
185 #define SW_ONLY_GATE(_offset, _status_bit, _en_bit) \ argument
187 .offset = (_offset), \
[all …]
/openbmc/openpower-hw-diags/attn/pel/
H A Dstream.hpp64 explicit Stream(std::vector<uint8_t>& data) : _data(data), _offset(0) {} in Stream()
73 _data(data), _offset(offset) in Stream()
75 if (_offset >= _data.size()) in Stream()
287 _offset = newOffset; in offset()
297 return _offset; in offset()
308 assert(_data.size() >= _offset); in remaining()
309 return _data.size() - _offset; in remaining()
321 memcpy(out, &_data[_offset], size); in read()
322 _offset += size; in read()
333 size_t newSize = _offset + size; in write()
[all …]
/openbmc/phosphor-logging/extensions/openpower-pels/
H A Dstream.hpp64 explicit Stream(std::vector<uint8_t>& data) : _data(data), _offset(0) {} in Stream()
73 _data(data), _offset(offset) in Stream()
75 if (_offset >= _data.size()) in Stream()
287 _offset = newOffset; in offset()
297 return _offset; in offset()
308 assert(_data.size() >= _offset); in remaining()
309 return _data.size() - _offset; in remaining()
321 memcpy(out, &_data[_offset], size); in read()
322 _offset += size; in read()
333 size_t newSize = _offset + size; in write()
[all …]
/openbmc/linux/drivers/clk/renesas/
H A Drcar-gen4-cpg.h36 #define DEF_GEN4_SDH(_name, _id, _parent, _offset) \ argument
37 DEF_BASE(_name, _id, CLK_TYPE_GEN4_SDH, _parent, .offset = _offset)
39 #define DEF_GEN4_SD(_name, _id, _parent, _offset) \ argument
40 DEF_BASE(_name, _id, CLK_TYPE_GEN4_SD, _parent, .offset = _offset)
50 #define DEF_GEN4_Z(_name, _id, _type, _parent, _div, _offset) \ argument
51 DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset)
H A Drcar-gen3-cpg.h37 #define DEF_GEN3_SDH(_name, _id, _parent, _offset) \ argument
38 DEF_BASE(_name, _id, CLK_TYPE_GEN3_SDH, _parent, .offset = _offset)
40 #define DEF_GEN3_SD(_name, _id, _parent, _offset) \ argument
41 DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
60 #define DEF_GEN3_Z(_name, _id, _type, _parent, _div, _offset) \ argument
61 DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset)
/openbmc/u-boot/arch/arm/cpu/armv7/bcm235xx/
H A Dclk-core.h174 #define HW_SW_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ argument
176 .offset = (_offset), \
186 #define HW_SW_GATE_AUTO(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ argument
188 .offset = (_offset), \
197 #define HW_ENABLE_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ argument
199 .offset = (_offset), \
208 #define SW_ONLY_GATE(_offset, _status_bit, _en_bit) \ argument
210 .offset = (_offset), \
218 #define HW_ONLY_GATE(_offset, _status_bit) \ argument
220 .offset = (_offset), \
[all …]
/openbmc/u-boot/arch/arm/cpu/armv7/bcm281xx/
H A Dclk-core.h174 #define HW_SW_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ argument
176 .offset = (_offset), \
186 #define HW_SW_GATE_AUTO(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ argument
188 .offset = (_offset), \
197 #define HW_ENABLE_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ argument
199 .offset = (_offset), \
208 #define SW_ONLY_GATE(_offset, _status_bit, _en_bit) \ argument
210 .offset = (_offset), \
218 #define HW_ONLY_GATE(_offset, _status_bit) \ argument
220 .offset = (_offset), \
[all …]
/openbmc/u-boot/tools/dtoc/
H A Dfdt.py42 self._offset = offset
54 self._offset = poffset
162 return self._node._fdt.GetStructOffset(self._offset)
201 if self._offset is None or self.dirty:
228 self._offset = offset
258 This should be used instead of self._offset directly, to ensure that
262 return self._offset
288 """Fix up the _offset for each node, recursively
294 if self._offset != my_offset:
295 self._offset = my_offset
[all …]
/openbmc/u-boot/include/fsl-mc/
H A Dfsl_mc_cmd.h80 #define MC_PREP_OP(_ext, _param, _offset, _width, _type, _arg) \ argument
81 ((_ext)[_param] |= cpu_to_le64(mc_enc((_offset), (_width), _arg)))
83 #define MC_EXT_OP(_ext, _param, _offset, _width, _type, _arg) \ argument
84 (_arg = (_type)mc_dec(cpu_to_le64(_ext[_param]), (_offset), (_width)))
86 #define MC_CMD_OP(_cmd, _param, _offset, _width, _type, _arg) \ argument
87 ((_cmd).params[_param] |= mc_enc((_offset), (_width), _arg))
89 #define MC_RSP_OP(_cmd, _param, _offset, _width, _type, _arg) \ argument
90 (_arg = (_type)mc_dec(_cmd.params[_param], (_offset), (_width)))
/openbmc/qemu/tests/tcg/s390x/
H A Dshift.c19 #define DEFINE_SHIFT_SINGLE_2(_insn, _offset) \ argument
20 DEFINE_SHIFT_SINGLE_COMMON(_insn ## _ ## _offset, \
21 #_insn " %[op1]," #_offset "(%[op2])")
22 #define DEFINE_SHIFT_SINGLE_3(_insn, _offset) \ argument
23 DEFINE_SHIFT_SINGLE_COMMON(_insn ## _ ## _offset, \
24 #_insn " %[op1],%[op1]," #_offset "(%[op2])")
25 #define DEFINE_SHIFT_DOUBLE(_insn, _offset) \ argument
26 static uint64_t _insn ## _ ## _offset(uint64_t op1, uint64_t op2, \
36 " " #_insn " %[r2]," #_offset "(%[op2])\n" \
/openbmc/u-boot/include/
H A Dfm_eth.h75 .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
89 .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
103 .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
116 .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
132 .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
147 .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
160 .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
/openbmc/linux/drivers/clk/tegra/
H A Dclk-tegra-periph.c132 #define MUX(_name, _parents, _offset, \ argument
134 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
139 #define MUX_FLAGS(_name, _parents, _offset,\ argument
141 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
146 #define MUX8(_name, _parents, _offset, \ argument
148 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
153 #define MUX8_NOGATE_LOCK(_name, _parents, _offset, _clk_id, _lock) \ argument
154 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset, \
159 #define MUX8_NOGATE(_name, _parents, _offset, _clk_id) \ argument
160 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset, \
[all …]
/openbmc/linux/drivers/clk/sunxi-ng/
H A Dccu_mult.h17 #define _SUNXI_CCU_MULT_OFFSET_MIN_MAX(_shift, _width, _offset, _min, _max) \ argument
21 .offset = _offset, \
29 #define _SUNXI_CCU_MULT_OFFSET(_shift, _width, _offset) \ argument
30 _SUNXI_CCU_MULT_OFFSET_MIN_MAX(_shift, _width, _offset, 1, 0)
/openbmc/u-boot/drivers/clk/renesas/
H A Drcar-gen3-cpg.h28 #define DEF_GEN3_SD(_name, _id, _parent, _offset) \ argument
29 DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
30 #define DEF_GEN3_RPC(_name, _id, _parent, _offset) \ argument
31 DEF_BASE(_name, _id, CLK_TYPE_GEN3_RPC, _parent, .offset = _offset)
H A Drenesas-cpg-mssr.h74 #define DEF_DIV6P1(_name, _id, _parent, _offset) \ argument
75 DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset)
76 #define DEF_DIV6_RO(_name, _id, _parent, _offset, _div) \ argument
77 DEF_BASE(_name, _id, CLK_TYPE_DIV6_RO, _parent, .offset = _offset, .div = _div, .mult = 1)
/openbmc/u-boot/arch/powerpc/include/asm/
H A Dfsl_liodn.h98 CONFIG_SYS_MPC85xx_USB##usbNum##_OFFSET)
102 CONFIG_SYS_MPC85xx_SATA##sataNum##_OFFSET)
106 CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET)
110 offsetof(ccsr_pcix_t, liodn_base) + CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET,\
111 CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET)
116 CONFIG_SYS_MPC85xx_DMA##dmaNum##_OFFSET + 0x300)
150 CONFIG_SYS_FSL_CORENET_PMAN##num##_OFFSET, \
151 CONFIG_SYS_FSL_CORENET_PMAN##num##_OFFSET)
155 CONFIG_SYS_FSL_FM##fmNum##_OFFSET + \
/openbmc/u-boot/drivers/net/
H A Dmacb.h285 (1 << MACB_##name##_OFFSET)
288 << MACB_##name##_OFFSET)
290 (((value) >> MACB_##name##_OFFSET) \
294 << MACB_##name##_OFFSET)) \
298 (1 << GEM_##name##_OFFSET)
301 << GEM_##name##_OFFSET)
303 (((value) >> GEM_##name##_OFFSET) \
307 << GEM_##name##_OFFSET)) \
/openbmc/u-boot/drivers/usb/musb-new/
H A Dmusb_regs.h268 #define MUSB_INDEXED_OFFSET(_epnum, _offset) \ argument
269 (0x10 + (_offset))
272 #define MUSB_FLAT_OFFSET(_epnum, _offset) \ argument
273 (0x100 + (0x10*(_epnum)) + (_offset))
278 #define MUSB_TUSB_OFFSET(_epnum, _offset) \ argument
279 (0x10 + _offset)
294 #define MUSB_BUSCTL_OFFSET(_epnum, _offset) \ argument
295 (0x80 + (8*(_epnum)) + (_offset))
358 #define MUSB_INDEXED_OFFSET(_epnum, _offset) (_offset) argument
372 #define MUSB_BUSCTL_OFFSET(_epnum, _offset) (_offset) argument
/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt6795-apmixedsys.c76 #define _FH(_pllid, _fhid, _slope, _offset) { \ argument
81 .fhx_offset = _offset, \
99 #define FH(_pllid, _fhid, _offset) _FH(_pllid, _fhid, 0x6003c97, _offset) argument
100 #define FH_M(_pllid, _fhid, _offset) _FH(_pllid, _fhid, 0x6000140, _offset) argument
/openbmc/linux/drivers/bcma/
H A Dsprom.c185 #define SPEX(_field, _offset, _mask, _shift) \ argument
186 bus->sprom._field = ((sprom[SPOFF(_offset)] & (_mask)) >> (_shift))
188 #define SPEX32(_field, _offset, _mask, _shift) \ argument
189 bus->sprom._field = ((((u32)sprom[SPOFF((_offset)+2)] << 16 | \
190 sprom[SPOFF(_offset)]) & (_mask)) >> (_shift))
192 #define SPEX_ARRAY8(_field, _offset, _mask, _shift) \ argument
194 SPEX(_field[0], _offset + 0, _mask, _shift); \
195 SPEX(_field[1], _offset + 2, _mask, _shift); \
196 SPEX(_field[2], _offset + 4, _mask, _shift); \
197 SPEX(_field[3], _offset + 6, _mask, _shift); \
[all …]
/openbmc/linux/drivers/pinctrl/mediatek/
H A Dpinctrl-mtk-common.h109 #define MTK_PIN_DRV_GRP(_pin, _offset, _bit, _grp) \ argument
112 .offset = _offset, \
134 #define MTK_PIN_PUPD_SPEC_SR(_pin, _offset, _pupd, _r1, _r0) \ argument
137 .offset = _offset, \
157 #define MTK_PIN_IES_SMT_SPEC(_start, _end, _offset, _bit) \ argument
162 .offset = _offset, \
/openbmc/linux/drivers/video/fbdev/vermilion/
H A Dvermilion.h240 #define VML_READ32(_par, _offset) \ argument
241 (ioread32((_par)->vdc_mem + (_offset)))
242 #define VML_WRITE32(_par, _offset, _value) \ argument
243 iowrite32(_value, (_par)->vdc_mem + (_offset))

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