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/openbmc/u-boot/arch/arm/include/asm/arch-imx8m/
H A Dddr.h15 #define IP2APB_DDRPHY_IPS_BASE_ADDR(X) (0x3c000000 + (X * 0x2000000)) argument
16 #define DDRPHY_MEM(X) (0x3c000000 + (X * 0x2000000) + 0x50000) argument
359 #define DDRC_MSTR(X) (DDRC_IPS_BASE_ADDR(X) + 0x00) argument
360 #define DDRC_STAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x04) argument
361 #define DDRC_MSTR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x08) argument
362 #define DDRC_MRCTRL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x10) argument
363 #define DDRC_MRCTRL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x14) argument
364 #define DDRC_MRSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x18) argument
365 #define DDRC_MRCTRL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1c) argument
366 #define DDRC_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x20) argument
[all …]
/openbmc/qemu/hw/intc/
H A Dtrace-events7 pic_ioport_write(bool master, uint64_t addr, uint64_t val) "master %d addr 0x%"PRIx64" val 0x%"PRIx…
8 pic_ioport_read(bool master, uint64_t addr, int val) "master %d addr 0x%"PRIx64" val 0x%x"
11 cpu_set_apic_base(uint64_t val) "0x%016"PRIx64
12 cpu_get_apic_base(uint64_t val) "0x%016"PRIx64
17 apic_register_read(uint8_t reg, uint64_t val) "register 0x%02x = 0x%"PRIx64
18 apic_register_write(uint8_t reg, uint64_t val) "register 0x%02x = 0x%"PRIx64
25 …nt8_t size, uint32_t val) "ioapic mem read addr 0x%"PRIx8" regsel: 0x%"PRIx8" size 0x%"PRIx8" retv…
26 …int8_t size, uint32_t val) "ioapic mem write addr 0x%"PRIx8" regsel: 0x%"PRIx8" size 0x%"PRIx8" va…
35 …io_intctl_mem_readl(uint32_t cpu, uint64_t addr, uint32_t ret) "read cpu %d reg 0x%"PRIx64" = 0x%x"
36 …_intctl_mem_writel(uint32_t cpu, uint64_t addr, uint32_t val) "write cpu %d reg 0x%"PRIx64" = 0x%x"
[all …]
/openbmc/qemu/hw/net/can/
H A Dtrace-events2 xlnx_can_update_irq(uint32_t isr, uint32_t ier, uint32_t irq) "ISR: 0x%08x IER: 0x%08x IRQ: 0x%08x"
3 xlnx_can_reset(uint32_t val) "Resetting controller with value = 0x%08x"
4 xlnx_can_rx_fifo_filter_reject(uint32_t id, uint8_t dlc) "Frame: ID: 0x%08x DLC: 0x%02x"
5 xlnx_can_filter_id_pre_write(uint8_t filter_num, uint32_t value) "Filter%d ID: 0x%08x"
6 xlnx_can_filter_mask_pre_write(uint8_t filter_num, uint32_t value) "Filter%d MASK: 0x%08x"
7 …nt8_t db6, uint8_t db7) "Frame: ID: 0x%08x DLC: 0x%02x DATA: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x…
8 …nt8_t db6, uint8_t db7) "Frame: ID: 0x%08x DLC: 0x%02x DATA: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x…
9 …discard(uint32_t status) "Controller is not enabled for bus communication. Status Register: 0x%08x"
12 …irq(char *path, uint32_t isr, uint32_t ier, uint32_t irq) "%s: ISR: 0x%08x IER: 0x%08x IRQ: 0x%08x"
13 …nfd_rx_fifo_filter_reject(char *path, uint32_t id, uint8_t dlc) "%s: Frame: ID: 0x%08x DLC: 0x%02x"
[all …]
/openbmc/u-boot/include/synopsys/
H A Ddwcddr21mctl.h47 #define DWCDDR21MCTL_CCR_ECCEN(x) ((x) << 0) argument
48 #define DWCDDR21MCTL_CCR_NOMRWR(x) ((x) << 1) argument
49 #define DWCDDR21MCTL_CCR_HOSTEN(x) ((x) << 2) argument
50 #define DWCDDR21MCTL_CCR_XBISC(x) ((x) << 3) argument
51 #define DWCDDR21MCTL_CCR_NOAPD(x) ((x) << 4) argument
52 #define DWCDDR21MCTL_CCR_RRB(x) ((x) << 13) argument
53 #define DWCDDR21MCTL_CCR_DQSCFG(x) ((x) << 14) argument
54 #define DWCDDR21MCTL_CCR_DFTLM(x) (((x) & 0x3) << 15) argument
55 #define DWCDDR21MCTL_CCR_DFTCMP(x) ((x) << 17) argument
56 #define DWCDDR21MCTL_CCR_FLUSH(x) ((x) << 27) argument
[all …]
/openbmc/qemu/hw/ppc/
H A Dtrace-events4 spapr_pci_msi(const char *msg, uint32_t ca) "%s (cfg=0x%x)"
5 spapr_pci_msi_setup(const char *name, unsigned vector, uint64_t addr) "dev\"%s\" vector %u, addr=0x…
6 …e_msi(unsigned cfg, unsigned func, unsigned req, unsigned first) "cfgaddr 0x%x func %u, requested …
8 spapr_pci_msi_write(uint64_t addr, uint64_t data, uint32_t dt_irq) "@0x%"PRIx64"<=0x%"PRIx64" IRQ %…
10 …signed config_addr, unsigned req_num, unsigned max_irqs) "Guest device at 0x%x asked %u, have only…
14 …int32_t cur_pvr, bool explicit_match, uint32_t new_pvr) "current=0x%x, explicit_match=%u, new=0x%x"
15 spapr_h_resize_hpt_prepare(uint64_t flags, uint64_t shift) "flags=0x%"PRIx64", shift=%"PRIu64
16 spapr_h_resize_hpt_commit(uint64_t flags, uint64_t shift) "flags=0x%"PRIx64", shift=%"PRIu64
18 …(unsigned cbold, unsigned cbnew, unsigned magic) "Old blob %u bytes, new blob %u bytes, magic 0x%x"
19 …(unsigned cbold, unsigned cbnew, unsigned magic) "Old blob %u bytes, new blob %u bytes, magic 0x%x"
[all …]
/openbmc/u-boot/include/andestech/
H A Dandes_pcu.h79 #define ANDES_PCU_REV_NUMBER_PCS(x) (((x) >> 0) & 0xff) argument
80 #define ANDES_PCU_REV_VER(x) (((x) >> 16) & 0xffff) argument
85 #define ANDES_PCU_SPINFO_SIZE(x) (((x) >> 0) & 0xff) argument
86 #define ANDES_PCU_SPINFO_OFFSET(x) (((x) >> 8) & 0xf) argument
91 #define ANDES_PCU_SOC_ID_VER_MINOR(x) (((x) >> 0) & 0xf) argument
92 #define ANDES_PCU_SOC_ID_VER_MAJOR(x) (((x) >> 4) & 0xfff) argument
93 #define ANDES_PCU_SOC_ID_DEVICEID(x) (((x) >> 16) & 0xffff) argument
98 #define ANDES_PCU_SOC_AHB_AHBC(x) ((x) << 0) argument
99 #define ANDES_PCU_SOC_AHB_APBREG(x) ((x) << 1) argument
100 #define ANDES_PCU_SOC_AHB_APB(x) ((x) << 2) argument
[all …]
/openbmc/u-boot/board/samsung/odroid/
H A Dsetup.h11 #define SDIV(x) ((x) & 0x7) argument
12 #define PDIV(x) (((x) & 0x3f) << 8) argument
13 #define MDIV(x) (((x) & 0x3ff) << 16) argument
14 #define FSEL(x) (((x) & 0x1) << 27) argument
16 #define PLL_ENABLE(x) (((x) & 0x1) << 31) argument
19 #define MUX_APLL_SEL(x) ((x) & 0x1) argument
20 #define MUX_CORE_SEL(x) (((x) & 0x1) << 16) argument
21 #define MUX_HPM_SEL(x) (((x) & 0x1) << 20) argument
22 #define MUX_MPLL_USER_SEL_C(x) (((x) & 0x1) << 24) argument
27 #define APLL_SEL(x) ((x) & 0x7) argument
[all …]
/openbmc/qemu/hw/isa/
H A Dtrace-events4 superio_create_parallel(int id, uint16_t base, unsigned int irq) "id=%d, base 0x%03x, irq %u"
5 superio_create_serial(int id, uint16_t base, unsigned int irq) "id=%d, base 0x%03x, irq %u"
6 superio_create_floppy(int id, uint16_t base, unsigned int irq) "id=%d, base 0x%03x, irq %u"
7 superio_create_ide(int id, uint16_t base, unsigned int irq) "id=%d, base 0x%03x, irq %u"
10 pc87312_io_read(uint32_t addr, uint32_t val) "read addr=0x%x val=0x%x"
11 pc87312_io_write(uint32_t addr, uint32_t val) "write addr=0x%x val=0x%x"
14 apm_io_read(uint8_t addr, uint8_t val) "read addr=0x%x val=0x%02x"
15 apm_io_write(uint8_t addr, uint8_t val) "write addr=0x%x val=0x%02x"
18 via_isa_write(uint32_t addr, uint32_t val, int len) "addr 0x%x val 0x%x len 0x%x"
19 via_pm_read(uint32_t addr, uint32_t val, int len) "addr 0x%x val 0x%x len 0x%x"
[all …]
/openbmc/qemu/hw/usb/
H A Dtrace-events17 usb_ohci_iso_td_read_failed(uint32_t addr) "ISO_TD read error at 0x%x"
18 …_TD ED head 0x%.8x tailp 0x%.8x, flags 0x%.8x bp 0x%.8x next 0x%.8x be 0x%.8x, frame_number 0x%.8x…
19 …2_t o4, uint32_t o5, uint32_t o6, uint32_t o7) "0x%.8x 0x%.8x 0x%.8x 0x%.8x 0x%.8x 0x%.8x 0x%.8x 0…
23 usb_ohci_iso_td_bad_bp_be(uint32_t bp, uint32_t be) "ISO_TD bp 0x%.8x be 0x%.8x"
24 …iso_td_bad_cc_not_accessed(uint32_t start, uint32_t next) "ISO_TD cc != not accessed 0x%.8x 0x%.8x"
25 …_td_bad_cc_overrun(uint32_t start, uint32_t next) "ISO_TD start_offset=0x%.8x > next_offset=0x%.8x"
26 …_t s, uint32_t e, const char *str, ssize_t len, int ret) "0x%.8x eo 0x%.8x sa 0x%.8x ea 0x%.8x dir…
31 …hci_td_bad_pid(const char *s, uint32_t edf, uint32_t tdf) "Bad pid %s: ed.flags 0x%x td.flags 0x%x"
32 usb_ohci_td_bad_buf(uint32_t cbp, uint32_t be) "Bad cbp = 0x%x > be = 0x%x"
43 usb_ohci_set_ctl(const char *s, uint32_t new_state) "%s: new state 0x%x"
[all …]
/openbmc/qemu/tests/qemu-iotests/
H A D013.out8 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
10 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
12 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
14 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
16 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
18 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
20 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
22 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
24 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
26 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
[all …]
H A D022.out8 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
10 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
12 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
14 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
16 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
18 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
20 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
22 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
24 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
26 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
[all …]
H A D023.out10 1 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
12 1 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
14 1 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
16 1 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
18 1 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
20 1 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
22 1 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
24 1 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
26 1 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
28 1 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
[all …]
H A D014.out8 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
10 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
12 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
14 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
16 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
18 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
20 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
22 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
24 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
26 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
[all …]
H A D037.out6 512 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
8 512 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
10 512 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
12 512 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
14 512 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
16 512 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
18 512 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
20 512 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
22 512 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
24 512 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
[all …]
H A D019.out7 512 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
9 512 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
11 512 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
13 512 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
15 512 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
17 512 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
19 512 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
21 512 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
23 512 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
25 512 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
[all …]
H A D020.out7 512 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
9 512 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
11 512 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
13 512 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
15 512 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
17 512 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
19 512 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
21 512 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
23 512 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
25 512 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
[all …]
H A D017.out7 512 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
9 512 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
11 512 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
13 512 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
15 512 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
17 512 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
19 512 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
21 512 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
23 512 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
25 512 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
[all …]
H A D018.out7 512 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
9 512 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
11 512 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
13 512 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
15 512 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
17 512 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
19 512 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
21 512 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
23 512 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
25 512 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
[all …]
H A D038.out6 64 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
8 64 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
10 64 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
12 64 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
14 64 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
16 64 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
18 64 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
20 64 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
22 64 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
24 64 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
[all …]
/openbmc/qemu/hw/net/
H A Dtrace-events4 …8i_emac_mii_write_reg(uint32_t reg, uint32_t value) "MII write: reg=0x%" PRIx32 " value=0x%" PRIx32
5 …un8i_emac_mii_read_reg(uint32_t reg, uint32_t value) "MII read: reg=0x%" PRIx32 " value=0x%" PRIx32
6 …(uint32_t desc, uint32_t paddr, uint32_t bytes) "RX packet: desc=0x%" PRIx32 " paddr=0x%" PRIx32 "…
7 …(uint32_t desc, uint32_t paddr, uint32_t bytes) "TX packet: desc=0x%" PRIx32 " paddr=0x%" PRIx32 "…
10 allwinner_sun8i_emac_read(uint64_t offset, uint64_t val) "MMIO read: offset=0x%" PRIx64 " value=0x%…
11 …sun8i_emac_write(uint64_t offset, uint64_t val) "MMIO write: offset=0x%" PRIx64 " value=0x%" PRIx64
14 lan9118_phy_read(uint16_t val, int reg) "[0x%02x] -> 0x%04" PRIx16
15 lan9118_phy_write(uint16_t val, int reg) "[0x%02x] <- 0x%04" PRIx16
20 lance_mem_readw(uint64_t addr, uint32_t ret) "addr=0x%"PRIx64"val=0x%04x"
21 lance_mem_writew(uint64_t addr, uint32_t val) "addr=0x%"PRIx64"val=0x%04x"
[all …]
/openbmc/qemu/hw/i386/
H A Dtrace-events7 …onst char *type, uint64_t hi, uint64_t lo) "invalidate desc type %s high 0x%"PRIx64" low 0x%"PRIx64
8 vtd_inv_desc_cc_domain(uint16_t domain) "context invalidate domain 0x%"PRIx16
11 …_devices(uint16_t sid, uint16_t fmask) "context invalidate devices sid 0x%"PRIx16" fmask 0x%"PRIx16
13 vtd_inv_desc_iotlb_domain(uint16_t domain) "iotlb invalidate whole domain 0x%"PRIx16
14 …in, uint64_t addr, uint8_t mask) "iotlb invalidate domain 0x%"PRIx16" addr 0x%"PRIx64" mask 0x%"PR…
15 …t mask, uint32_t pasid) "iotlb invalidate domain 0x%"PRIx16" addr 0x%"PRIx64" mask 0x%"PRIx8" pasi…
16 …_iotlb_pasid(uint16_t domain, uint32_t pasid) "iotlb invalidate domain 0x%"PRIx16" pasid 0x%"PRIx32
17 …ait_sw(uint64_t addr, uint32_t data) "wait invalidate status write addr 0x%"PRIx64" data 0x%"PRIx32
19 …sc_wait_write_fail(uint64_t hi, uint64_t lo) "write fail for wait desc hi 0x%"PRIx64" lo 0x%"PRIx64
20 …granularity, uint32_t index, uint32_t mask) "granularity 0x%"PRIx32" index 0x%"PRIx32" mask 0x%"PR…
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dvop_rk3288.h122 #define V_AUTO_GATING_EN(x) (((x) & 1) << 23) argument
123 #define V_STANDBY_EN(x) (((x) & 1) << 22) argument
124 #define V_DMA_STOP(x) (((x) & 1) << 21) argument
125 #define V_MMU_EN(x) (((x) & 1) << 20) argument
126 #define V_DMA_BURST_LENGTH(x) (((x) & 3) << 18) argument
127 #define V_MIPI_OUT_EN(x) (((x) & 1) << 15) argument
128 #define V_EDP_OUT_EN(x) (((x) & 1) << 14) argument
129 #define V_HDMI_OUT_EN(x) (((x) & 1) << 13) argument
130 #define V_RGB_OUT_EN(x) (((x) & 1) << 12) argument
131 #define V_EDPI_WMS_FS(x) (((x) & 1) << 10) argument
[all …]
/openbmc/qemu/hw/display/
H A Dtrace-events4 jazz_led_read(uint64_t addr, uint8_t val) "read addr=0x%"PRIx64": 0x%x"
5 jazz_led_write(uint64_t addr, uint8_t new) "write addr=0x%"PRIx64": 0x%x"
8 …nt dx, int dy, int dz, int button_state, int abs_pointer_wanted) "%p x %d y %d z %d bs 0x%x abs %d"
9 xenfb_key_event(void *opaque, int scancode, int button_state) "%p scancode %d bs 0x%x"
13 g364fb_read(uint64_t addr, uint32_t val) "read addr=0x%"PRIx64": 0x%x"
14 g364fb_write(uint64_t addr, uint32_t new) "write addr=0x%"PRIx64": 0x%x"
17 vmware_value_read(uint32_t index, uint32_t value) "index %d, value 0x%x"
18 vmware_value_write(uint32_t index, uint32_t value) "index %d, value 0x%x"
19 vmware_palette_read(uint32_t index, uint32_t value) "index %d, value 0x%x"
20 vmware_palette_write(uint32_t index, uint32_t value) "index %d, value 0x%x"
[all …]
/openbmc/qemu/hw/misc/
H A Dtrace-events4 allwinner_cpucfg_cpu_reset(uint8_t cpu_id, uint32_t reset_addr) "id %u, reset_addr 0x%" PRIx32
5 allwinner_cpucfg_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%…
6 allwinner_cpucfg_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x…
10 allwinner_h3_dramc_rowmirror_enable(uint64_t addr) "Enable row mirror: addr 0x%" PRIx64
11 …ead(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " …
12 …te(uint64_t offset, uint64_t data, unsigned size) "Write: offset 0x%" PRIx64 " data 0x%" PRIx64 " …
13 …ead(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " …
14 …te(uint64_t offset, uint64_t data, unsigned size) "Write: offset 0x%" PRIx64 " data 0x%" PRIx64 " …
15 …ead(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " …
16 …te(uint64_t offset, uint64_t data, unsigned size) "write: offset 0x%" PRIx64 " data 0x%" PRIx64 " …
[all …]
/openbmc/qemu/hw/scsi/
H A Dtrace-events16 …n, int tag, int key, int asc, int ascq) "target %d lun %d tag %d key 0x%02x asc 0x%02x ascq 0x%02x"
17 …t target, int lun, int key, int asc, int ascq) "target %d lun %d key 0x%02x asc 0x%02x ascq 0x%02x"
19 …uiry(int target, int lun, int tag, int cdb1, int cdb2) "target %d lun %d tag %d page 0x%02x/0x%02x"
24 …d *dev, uint32_t ctx, uint32_t status, uint32_t resid) "dev %p context 0x%08x status 0x%x resid %d"
25 mptsas_diag_read(void *dev, uint32_t addr, uint32_t val) "dev %p addr 0x%08x value 0x%08x"
26 mptsas_diag_write(void *dev, uint32_t addr, uint32_t val) "dev %p addr 0x%08x value 0x%08x"
29 mptsas_mmio_read(void *dev, uint32_t addr, uint32_t val) "dev %p addr 0x%08x value 0x%x"
30 mptsas_mmio_unhandled_read(void *dev, uint32_t addr) "dev %p addr 0x%08x"
31 mptsas_mmio_unhandled_write(void *dev, uint32_t addr, uint32_t val) "dev %p addr 0x%08x value 0x%x"
32 mptsas_mmio_write(void *dev, uint32_t addr, uint32_t val) "dev %p addr 0x%08x value 0x%x"
[all …]

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