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/openbmc/linux/arch/mips/kernel/
H A Dvpe-mt.c18 #include <asm/vpe.h>
25 /* We are prepared so configure and start the VPE... */
26 int vpe_run(struct vpe *v) in vpe_run()
33 /* check we are the Master VPE */ in vpe_run()
37 pr_warn("VPE loader: only Master VPE's are able to config MT\n"); in vpe_run()
51 pr_warn("VPE loader: No TC's associated with VPE %d\n", in vpe_run()
71 pr_warn("VPE loader: TC %d is already active!\n", in vpe_run()
95 * We don't pass the memsize here, so VPE programs need to be in vpe_run()
103 * bind the TC to VPE 1 as late as possible so we only have the final in vpe_run()
104 * VPE registers to set up, and so an EJTAG probe can trigger on it in vpe_run()
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H A Dvpe.c9 * VPE spport module for loading a MIPS SP program into VPE1. The SP
36 #include <asm/vpe.h>
52 /* get the vpe associated with this minor */
53 struct vpe *get_vpe(int minor) in get_vpe()
55 struct vpe *res, *v; in get_vpe()
73 /* get the vpe associated with this minor */
91 /* allocate a vpe and associate it with this minor (or index) */
92 struct vpe *alloc_vpe(int minor) in alloc_vpe()
94 struct vpe *v; in alloc_vpe()
96 v = kzalloc(sizeof(struct vpe), GFP_KERNEL); in alloc_vpe()
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H A Dcps-vec.S169 * deactivate this VPE if it should be offline.
234 /* Only allow 1 TC per VPE to execute... */
237 /* ...and for the moment only 1 VPE */
243 /* Enter VPE configuration state */
258 /* Loop through each VPE within this core */
265 /* Bind TC to VPE (1:1 TC:VPE mapping) */
281 /* Next VPE */
287 /* Leave VPE configuration state */
302 * struct vpe_boot_config in v1, VPE ID in t9
334 /* Calculate a mask for the VPE ID from EBase.CPUNum */
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H A Dsmp-mt.c53 /* Deactivate all but VPE 0 */ in smvp_vpe_init()
59 /* master VPE */ in smvp_vpe_init()
88 /* bind a TC to each VPE, May as well put all excess TC's in smvp_tc_init()
89 on the last VPE */ in smvp_tc_init()
141 * assumes a 1:1 mapping of TC => VPE
154 /* enable the tc this vpe/cpu will be running */ in vsmp_boot_secondary()
159 /* enable the VPE */ in vsmp_boot_secondary()
210 /* we'll always have more TC's than VPE's, so loop setting everything in vsmp_smp_setup()
H A Dmips-mt.c71 printk("-- per-VPE State --\n"); in mips_mt_regdump()
76 printk(" VPE %d\n", i); in mips_mt_regdump()
81 printk(" VPE%d.Status : %08lx\n", in mips_mt_regdump()
83 printk(" VPE%d.EPC : %08lx %pS\n", in mips_mt_regdump()
86 printk(" VPE%d.Cause : %08lx\n", in mips_mt_regdump()
88 printk(" VPE%d.Config7 : %08lx\n", in mips_mt_regdump()
90 break; /* Next VPE */ in mips_mt_regdump()
101 printk(" TC %d (current TC with VPE EPC above)\n", tc); in mips_mt_regdump()
H A Dsmp-cps.c43 /* Detect & record VPE topology */ in cps_smp_setup()
46 pr_info("%s topology ", cpu_has_mips_r6 ? "VP" : "VPE"); in cps_smp_setup()
77 /* Indicate present CPUs (CPU being synonymous with VPE) */ in cps_smp_setup()
172 /* Allocate VPE boot configuration structs */ in cps_prepare_cpus()
179 pr_err("Failed to allocate %u VPE boot configs\n", in cps_prepare_cpus()
313 /* Boot a VPE on a powered down core */ in cps_boot_secondary()
326 /* Boot a VPE on another powered up core */ in cps_boot_secondary()
348 /* Boot a VPE on this core */ in cps_boot_secondary()
359 /* Disable MT - we only want to run 1 TC per VPE */ in cps_init_secondary()
484 /* Look for another online VPE within the core */ in play_dead()
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H A Dpm-cps.c35 * VPE left it. Returns garbage if coupled_coherence is zero or this is not
141 /* Setup the VPE to run mips_cps_pm_restore when started again */ in cps_pm_enter_state()
179 * If this VPE is the first to leave the non-coherent wait state then in cps_pm_enter_state()
394 * but in the coupled case the enable step will only run on one VPE. in cps_gen_entry_code()
412 * If this is the last VPE to become ready for non-coherence in cps_gen_entry_code()
420 * Otherwise this is not the last VPE to become ready in cps_gen_entry_code()
436 * The core will lose power & this VPE will not continue in cps_gen_entry_code()
440 /* Halt the VPE via C0 tchalt register */ in cps_gen_entry_code()
461 * This is the point of no return - this VPE will now proceed to in cps_gen_entry_code()
463 * VPE within the core will interfere with the L1 dcache. in cps_gen_entry_code()
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H A Drtlx-mt.c18 #include <asm/vpe.h>
74 pr_warn("VPE loader: not a MIPS MT capable processor\n"); in rtlx_module_init()
H A DMakefile65 obj-$(CONFIG_MIPS_VPE_LOADER) += vpe.o
66 obj-$(CONFIG_MIPS_VPE_LOADER_MT) += vpe-mt.o
H A Drtlx.c22 #include <asm/vpe.h>
68 void rtlx_starting(int vpe) in rtlx_starting() argument
81 void rtlx_stopping(int vpe) in rtlx_stopping() argument
/openbmc/linux/drivers/irqchip/
H A Dirq-gic-v4.c54 * with the actual vPE affinity, and not the braindead concept of
64 * The choice made here is that each vcpu (VPE in old northern GICv4
67 * interrupt becomes a handle for the VPE, and that the hypervisor
71 * contain an irq domain where each interrupt maps to a VPE. In
77 * - irq_set_affinity is used to move a VPE from one redistributor to
81 * creating a new sub-API, namely scheduling/descheduling a VPE
118 static int its_alloc_vcpu_sgis(struct its_vpe *vpe, int idx) in its_alloc_vcpu_sgis() argument
130 vpe->fwnode = irq_domain_alloc_named_id_fwnode(name, idx); in its_alloc_vcpu_sgis()
131 if (!vpe->fwnode) in its_alloc_vcpu_sgis()
137 vpe->sgi_domain = irq_domain_create_linear(vpe->fwnode, 16, in its_alloc_vcpu_sgis()
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H A Dirq-gic-v3-its.c266 static int vpe_to_cpuid_lock(struct its_vpe *vpe, unsigned long *flags) in vpe_to_cpuid_lock() argument
268 raw_spin_lock_irqsave(&vpe->vpe_lock, *flags); in vpe_to_cpuid_lock()
269 return vpe->col_idx; in vpe_to_cpuid_lock()
272 static void vpe_to_cpuid_unlock(struct its_vpe *vpe, unsigned long flags) in vpe_to_cpuid_unlock() argument
274 raw_spin_unlock_irqrestore(&vpe->vpe_lock, flags); in vpe_to_cpuid_unlock()
281 struct its_vpe *vpe = NULL; in irq_to_cpuid_lock() local
285 vpe = irq_data_get_irq_chip_data(d); in irq_to_cpuid_lock()
289 vpe = map->vpe; in irq_to_cpuid_lock()
292 if (vpe) { in irq_to_cpuid_lock()
293 cpu = vpe_to_cpuid_lock(vpe, flags); in irq_to_cpuid_lock()
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/openbmc/linux/arch/mips/lantiq/
H A Dirq.c50 #define ltq_icu_w32(vpe, m, x, y) \ argument
51 ltq_w32((x), ltq_icu_membase[vpe] + m*LTQ_ICU_IM_SIZE + (y))
53 #define ltq_icu_r32(vpe, m, x) \ argument
54 ltq_r32(ltq_icu_membase[vpe] + m*LTQ_ICU_IM_SIZE + (x))
83 int vpe; in ltq_disable_irq() local
88 for_each_present_cpu(vpe) { in ltq_disable_irq()
89 ltq_icu_w32(vpe, im, in ltq_disable_irq()
90 ltq_icu_r32(vpe, im, LTQ_ICU_IER) & ~BIT(offset), in ltq_disable_irq()
101 int vpe; in ltq_mask_and_ack_irq() local
106 for_each_present_cpu(vpe) { in ltq_mask_and_ack_irq()
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/openbmc/linux/include/linux/irqchip/
H A Darm-gic-v4.h35 /* per-vPE VLPI tracking */
40 /* VPE resident */
47 /* VPE proxy mapping */
64 /* Track the VPE being mapped */
69 * vPE and vLPI operations using vpe->col_idx.
74 * redistributor for this VPE. The ID itself isn't involved in
78 /* Unique (system-wide) VPE identifier */
91 * @vpe: Pointer to the GICv4 notion of a virtual CPU (VPE)
94 * @db_enabled: Is the VPE doorbell to be generated?
98 struct its_vpe *vpe; member
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/openbmc/linux/arch/mips/include/asm/
H A Dvpe.h17 #define VPE_MODULE_NAME "vpe"
49 struct vpe { struct
52 /* (device) minor associated with this vpe */
63 /* tc's associated with this vpe */ argument
66 /* The list of vpe's */ argument
82 struct vpe *pvpe; /* parent VPE */ argument
83 struct list_head tc; /* The list of TC's with this VPE */
88 void (*start)(int vpe);
89 void (*stop)(int vpe);
108 struct vpe *get_vpe(int minor);
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H A Drtlx.h30 void rtlx_starting(int vpe);
31 void rtlx_stopping(int vpe);
H A Dsmp-cps.h30 extern void mips_cps_boot_vpes(struct core_boot_config *cfg, unsigned vpe);
/openbmc/linux/Documentation/devicetree/bindings/media/
H A Dti,vpe.yaml4 $id: http://devicetree.org/schemas/media/ti,vpe.yaml#
7 title: Texas Instruments DRA7x Video Processing Engine (VPE)
13 The Video Processing Engine (VPE) is a key component for image post
14 processing applications. VPE consist of a single memory to memory
20 const: ti,dra7-vpe
24 - description: The VPE main register region
51 vpe: vpe@489d0000 {
52 compatible = "ti,dra7-vpe";
/openbmc/linux/arch/arm64/kvm/vgic/
H A Dvgic-v4.c94 * The v4.1 doorbell can fire concurrently with the vPE being in vgic_v4_doorbell_handler()
108 static void vgic_v4_sync_sgi_config(struct its_vpe *vpe, struct vgic_irq *irq) in vgic_v4_sync_sgi_config() argument
110 vpe->sgi_config[irq->intid].enabled = irq->enabled; in vgic_v4_sync_sgi_config()
111 vpe->sgi_config[irq->intid].group = irq->group; in vgic_v4_sync_sgi_config()
112 vpe->sgi_config[irq->intid].priority = irq->priority; in vgic_v4_sync_sgi_config()
117 struct its_vpe *vpe = &vcpu->arch.vgic_cpu.vgic_v3.its_vpe; in vgic_v4_enable_vsgis() local
137 irq->host_irq = irq_find_mapping(vpe->sgi_domain, i); in vgic_v4_enable_vsgis()
139 /* Transfer the full irq state to the vPE */ in vgic_v4_enable_vsgis()
140 vgic_v4_sync_sgi_config(vpe, irq); in vgic_v4_enable_vsgis()
208 * Must be called with GICv4.1 and the vPE unmapped, which
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/openbmc/linux/drivers/media/platform/ti/
H A DKconfig6 # These will be selected by VPE and VIP
47 tristate "TI VPE (Video Processing Engine) driver"
57 Support for the TI VPE(Video Processing Engine) block
61 bool "VPE debug messages"
64 Enable debug messages on VPE driver.
H A DMakefile4 obj-y += vpe/
/openbmc/linux/drivers/media/platform/ti/vpe/
H A DMakefile2 obj-$(CONFIG_VIDEO_TI_VPE) += ti-vpe.o
7 ti-vpe-y := vpe.o
H A Dvpe_regs.h13 /* VPE register offsets and field selectors */
15 /* VPE top level regs */
121 /* VPE chrominance upsampler regs */
192 /* VPE de-interlacer regs */
/openbmc/qemu/target/mips/
H A Dinternal.h251 /* Check that the VPE is enabled. */ in mips_vpe_active()
255 /* Check that the VPE is activated. */ in mips_vpe_active()
261 * Now verify that there are active thread contexts in the VPE. in mips_vpe_active()
266 * the entire VPE. in mips_vpe_active()
/openbmc/linux/Documentation/admin-guide/media/
H A Dplatform-cardlist.rst69 ti-vpe TI VPE (Video Processing Engine)

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