35  * VPE left it. Returns garbage if coupled_coherence is zero or this is not
141 	/* Setup the VPE to run mips_cps_pm_restore when started again */  in cps_pm_enter_state()
179 	 * If this VPE is the first to leave the non-coherent wait state then  in cps_pm_enter_state()
394 	 * but in the coupled case the enable step will only run on one VPE.  in cps_gen_entry_code()
412 		 * If this is the last VPE to become ready for non-coherence  in cps_gen_entry_code()
420 			 * Otherwise this is not the last VPE to become ready  in cps_gen_entry_code()
436 			 * The core will lose power & this VPE will not continue  in cps_gen_entry_code()
440 				/* Halt the VPE via C0 tchalt register */  in cps_gen_entry_code()
461 	 * This is the point of no return - this VPE will now proceed to  in cps_gen_entry_code()
463 	 * VPE within the core will interfere with the L1 dcache.  in cps_gen_entry_code()
544 		 * execution. This VPE will set the top bit of ready_count  in cps_gen_entry_code()
595 		 * execution. This VPE will set the top bit of ready_count  in cps_gen_entry_code()
603 		 * Thus an arbitrary VPE can't trigger the core leaving the  in cps_gen_entry_code()
708 	 * non-coherent core then the VPE may end up processing interrupts  in cps_pm_init()