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/openbmc/linux/Documentation/devicetree/bindings/media/
H A Dqcom,sdm660-venus.yaml150 power-domains = <&mmcc VENUS_CORE0_GDSC>;
157 power-domains = <&mmcc VENUS_CORE0_GDSC>;
H A Dqcom,msm8996-venus.yaml146 power-domains = <&mmcc VENUS_CORE0_GDSC>;
/openbmc/linux/include/dt-bindings/clock/
H A Dqcom,mmcc-msm8994.h140 #define VENUS_CORE0_GDSC 1 macro
H A Dqcom,mmcc-sdm660.h151 #define VENUS_CORE0_GDSC 1 macro
H A Dqcom,gcc-msm8917.h186 #define VENUS_CORE0_GDSC 4 macro
H A Dqcom,gcc-msm8939.h204 #define VENUS_CORE0_GDSC 6 macro
H A Dqcom,gcc-msm8909.h215 #define VENUS_CORE0_GDSC 3 macro
H A Dqcom,gcc-msm8953.h229 #define VENUS_CORE0_GDSC 6 macro
H A Dqcom,gcc-msm8976.h231 #define VENUS_CORE0_GDSC 1 macro
H A Dqcom,mmcc-msm8996.h283 #define VENUS_CORE0_GDSC 5 macro
/openbmc/linux/drivers/clk/qcom/
H A Dgcc-msm8909.c2469 static struct gdsc venus_core0_gdsc = { variable
2474 .name = "venus_core0_gdsc",
2629 [VENUS_CORE0_GDSC] = &venus_core0_gdsc,
H A Dmmcc-msm8994.c2268 static struct gdsc venus_core0_gdsc = { variable
2273 .name = "venus_core0_gdsc",
2517 [VENUS_CORE0_GDSC] = &venus_core0_gdsc,
H A Dgcc-msm8917.c2967 static struct gdsc venus_core0_gdsc = { variable
3231 [VENUS_CORE0_GDSC] = &venus_core0_gdsc,
H A Dmmcc-sdm660.c2571 static struct gdsc venus_core0_gdsc = { variable
2779 [VENUS_CORE0_GDSC] = &venus_core0_gdsc,
H A Dgcc-msm8976.c3749 static struct gdsc venus_core0_gdsc = { variable
3754 .name = "venus_core0_gdsc",
4064 [VENUS_CORE0_GDSC] = &venus_core0_gdsc,
H A Dmmcc-msm8996.c3209 static struct gdsc venus_core0_gdsc = { variable
3514 [VENUS_CORE0_GDSC] = &venus_core0_gdsc,
H A Dgcc-msm8953.c3869 static struct gdsc venus_core0_gdsc = { variable
4191 [VENUS_CORE0_GDSC] = &venus_core0_gdsc,
H A Dgcc-msm8939.c3653 static struct gdsc venus_core0_gdsc = { variable
3865 [VENUS_CORE0_GDSC] = &venus_core0_gdsc,
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dsdm630.dtsi2131 power-domains = <&mmcc VENUS_CORE0_GDSC>;
2138 power-domains = <&mmcc VENUS_CORE0_GDSC>;
H A Dmsm8996.dtsi2365 power-domains = <&mmcc VENUS_CORE0_GDSC>;