1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
4 */
5
6 #include <linux/kernel.h>
7 #include <linux/bitops.h>
8 #include <linux/err.h>
9 #include <linux/platform_device.h>
10 #include <linux/module.h>
11 #include <linux/of.h>
12 #include <linux/clk-provider.h>
13 #include <linux/regmap.h>
14 #include <linux/reset-controller.h>
15 #include <linux/clk.h>
16
17 #include <dt-bindings/clock/qcom,mmcc-msm8994.h>
18
19 #include "common.h"
20 #include "clk-regmap.h"
21 #include "clk-regmap-divider.h"
22 #include "clk-alpha-pll.h"
23 #include "clk-rcg.h"
24 #include "clk-branch.h"
25 #include "reset.h"
26 #include "gdsc.h"
27
28
29 enum {
30 P_XO,
31 P_GPLL0,
32 P_MMPLL0,
33 P_MMPLL1,
34 P_MMPLL3,
35 P_MMPLL4,
36 P_MMPLL5, /* Is this one even used by anything? Downstream doesn't tell. */
37 P_DSI0PLL,
38 P_DSI1PLL,
39 P_DSI0PLL_BYTE,
40 P_DSI1PLL_BYTE,
41 P_HDMIPLL,
42 };
43 static const struct parent_map mmcc_xo_gpll0_map[] = {
44 { P_XO, 0 },
45 { P_GPLL0, 5 }
46 };
47
48 static const struct clk_parent_data mmcc_xo_gpll0[] = {
49 { .fw_name = "xo" },
50 { .fw_name = "gpll0" },
51 };
52
53 static const struct parent_map mmss_xo_hdmi_map[] = {
54 { P_XO, 0 },
55 { P_HDMIPLL, 3 }
56 };
57
58 static const struct clk_parent_data mmss_xo_hdmi[] = {
59 { .fw_name = "xo" },
60 { .fw_name = "hdmipll" },
61 };
62
63 static const struct parent_map mmcc_xo_dsi0pll_dsi1pll_map[] = {
64 { P_XO, 0 },
65 { P_DSI0PLL, 1 },
66 { P_DSI1PLL, 2 }
67 };
68
69 static const struct clk_parent_data mmcc_xo_dsi0pll_dsi1pll[] = {
70 { .fw_name = "xo" },
71 { .fw_name = "dsi0pll" },
72 { .fw_name = "dsi1pll" },
73 };
74
75 static const struct parent_map mmcc_xo_dsibyte_map[] = {
76 { P_XO, 0 },
77 { P_DSI0PLL_BYTE, 1 },
78 { P_DSI1PLL_BYTE, 2 }
79 };
80
81 static const struct clk_parent_data mmcc_xo_dsibyte[] = {
82 { .fw_name = "xo" },
83 { .fw_name = "dsi0pllbyte" },
84 { .fw_name = "dsi1pllbyte" },
85 };
86
87 static struct pll_vco mmpll_p_vco[] = {
88 { 250000000, 500000000, 3 },
89 { 500000000, 1000000000, 2 },
90 { 1000000000, 1500000000, 1 },
91 { 1500000000, 2000000000, 0 },
92 };
93
94 static struct pll_vco mmpll_t_vco[] = {
95 { 500000000, 1500000000, 0 },
96 };
97
98 static const struct alpha_pll_config mmpll_p_config = {
99 .post_div_mask = 0xf00,
100 };
101
102 static struct clk_alpha_pll mmpll0_early = {
103 .offset = 0x0,
104 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
105 .vco_table = mmpll_p_vco,
106 .num_vco = ARRAY_SIZE(mmpll_p_vco),
107 .clkr = {
108 .enable_reg = 0x100,
109 .enable_mask = BIT(0),
110 .hw.init = &(struct clk_init_data){
111 .name = "mmpll0_early",
112 .parent_data = &(const struct clk_parent_data){
113 .fw_name = "xo",
114 },
115 .num_parents = 1,
116 .ops = &clk_alpha_pll_ops,
117 },
118 },
119 };
120
121 static struct clk_alpha_pll_postdiv mmpll0 = {
122 .offset = 0x0,
123 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
124 .width = 4,
125 .clkr.hw.init = &(struct clk_init_data){
126 .name = "mmpll0",
127 .parent_hws = (const struct clk_hw *[]){ &mmpll0_early.clkr.hw },
128 .num_parents = 1,
129 .ops = &clk_alpha_pll_postdiv_ops,
130 .flags = CLK_SET_RATE_PARENT,
131 },
132 };
133
134 static struct clk_alpha_pll mmpll1_early = {
135 .offset = 0x30,
136 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
137 .vco_table = mmpll_p_vco,
138 .num_vco = ARRAY_SIZE(mmpll_p_vco),
139 .clkr = {
140 .enable_reg = 0x100,
141 .enable_mask = BIT(1),
142 .hw.init = &(struct clk_init_data){
143 .name = "mmpll1_early",
144 .parent_data = &(const struct clk_parent_data){
145 .fw_name = "xo",
146 },
147 .num_parents = 1,
148 .ops = &clk_alpha_pll_ops,
149 }
150 },
151 };
152
153 static struct clk_alpha_pll_postdiv mmpll1 = {
154 .offset = 0x30,
155 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
156 .width = 4,
157 .clkr.hw.init = &(struct clk_init_data){
158 .name = "mmpll1",
159 .parent_hws = (const struct clk_hw *[]){ &mmpll1_early.clkr.hw },
160 .num_parents = 1,
161 .ops = &clk_alpha_pll_postdiv_ops,
162 .flags = CLK_SET_RATE_PARENT,
163 },
164 };
165
166 static struct clk_alpha_pll mmpll3_early = {
167 .offset = 0x60,
168 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
169 .vco_table = mmpll_p_vco,
170 .num_vco = ARRAY_SIZE(mmpll_p_vco),
171 .clkr.hw.init = &(struct clk_init_data){
172 .name = "mmpll3_early",
173 .parent_data = &(const struct clk_parent_data){
174 .fw_name = "xo",
175 },
176 .num_parents = 1,
177 .ops = &clk_alpha_pll_ops,
178 },
179 };
180
181 static struct clk_alpha_pll_postdiv mmpll3 = {
182 .offset = 0x60,
183 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
184 .width = 4,
185 .clkr.hw.init = &(struct clk_init_data){
186 .name = "mmpll3",
187 .parent_hws = (const struct clk_hw *[]){ &mmpll3_early.clkr.hw },
188 .num_parents = 1,
189 .ops = &clk_alpha_pll_postdiv_ops,
190 .flags = CLK_SET_RATE_PARENT,
191 },
192 };
193
194 static struct clk_alpha_pll mmpll4_early = {
195 .offset = 0x90,
196 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
197 .vco_table = mmpll_t_vco,
198 .num_vco = ARRAY_SIZE(mmpll_t_vco),
199 .clkr.hw.init = &(struct clk_init_data){
200 .name = "mmpll4_early",
201 .parent_data = &(const struct clk_parent_data){
202 .fw_name = "xo",
203 },
204 .num_parents = 1,
205 .ops = &clk_alpha_pll_ops,
206 },
207 };
208
209 static struct clk_alpha_pll_postdiv mmpll4 = {
210 .offset = 0x90,
211 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
212 .width = 2,
213 .clkr.hw.init = &(struct clk_init_data){
214 .name = "mmpll4",
215 .parent_hws = (const struct clk_hw *[]){ &mmpll4_early.clkr.hw },
216 .num_parents = 1,
217 .ops = &clk_alpha_pll_postdiv_ops,
218 .flags = CLK_SET_RATE_PARENT,
219 },
220 };
221
222 static const struct parent_map mmcc_xo_gpll0_mmpll1_map[] = {
223 { P_XO, 0 },
224 { P_GPLL0, 5 },
225 { P_MMPLL1, 2 }
226 };
227
228 static const struct clk_parent_data mmcc_xo_gpll0_mmpll1[] = {
229 { .fw_name = "xo" },
230 { .fw_name = "gpll0" },
231 { .hw = &mmpll1.clkr.hw },
232 };
233
234 static const struct parent_map mmcc_xo_gpll0_mmpll0_map[] = {
235 { P_XO, 0 },
236 { P_GPLL0, 5 },
237 { P_MMPLL0, 1 }
238 };
239
240 static const struct clk_parent_data mmcc_xo_gpll0_mmpll0[] = {
241 { .fw_name = "xo" },
242 { .fw_name = "gpll0" },
243 { .hw = &mmpll0.clkr.hw },
244 };
245
246 static const struct parent_map mmcc_xo_gpll0_mmpll0_mmpll3_map[] = {
247 { P_XO, 0 },
248 { P_GPLL0, 5 },
249 { P_MMPLL0, 1 },
250 { P_MMPLL3, 3 }
251 };
252
253 static const struct clk_parent_data mmcc_xo_gpll0_mmpll0_mmpll3[] = {
254 { .fw_name = "xo" },
255 { .fw_name = "gpll0" },
256 { .hw = &mmpll0.clkr.hw },
257 { .hw = &mmpll3.clkr.hw },
258 };
259
260 static const struct parent_map mmcc_xo_gpll0_mmpll0_mmpll4_map[] = {
261 { P_XO, 0 },
262 { P_GPLL0, 5 },
263 { P_MMPLL0, 1 },
264 { P_MMPLL4, 3 }
265 };
266
267 static const struct clk_parent_data mmcc_xo_gpll0_mmpll0_mmpll4[] = {
268 { .fw_name = "xo" },
269 { .fw_name = "gpll0" },
270 { .hw = &mmpll0.clkr.hw },
271 { .hw = &mmpll4.clkr.hw },
272 };
273
274 static struct clk_alpha_pll mmpll5_early = {
275 .offset = 0xc0,
276 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
277 .vco_table = mmpll_p_vco,
278 .num_vco = ARRAY_SIZE(mmpll_p_vco),
279 .clkr.hw.init = &(struct clk_init_data){
280 .name = "mmpll5_early",
281 .parent_data = &(const struct clk_parent_data){
282 .fw_name = "xo",
283 },
284 .num_parents = 1,
285 .ops = &clk_alpha_pll_ops,
286 },
287 };
288
289 static struct clk_alpha_pll_postdiv mmpll5 = {
290 .offset = 0xc0,
291 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
292 .width = 4,
293 .clkr.hw.init = &(struct clk_init_data){
294 .name = "mmpll5",
295 .parent_hws = (const struct clk_hw *[]){ &mmpll5_early.clkr.hw },
296 .num_parents = 1,
297 .ops = &clk_alpha_pll_postdiv_ops,
298 .flags = CLK_SET_RATE_PARENT,
299 },
300 };
301
302 static const struct freq_tbl ftbl_ahb_clk_src[] = {
303 /* Note: There might be more frequencies desired here. */
304 F(19200000, P_XO, 1, 0, 0),
305 F(40000000, P_GPLL0, 15, 0, 0),
306 F(80000000, P_MMPLL0, 10, 0, 0),
307 { }
308 };
309
310 static struct clk_rcg2 ahb_clk_src = {
311 .cmd_rcgr = 0x5000,
312 .hid_width = 5,
313 .parent_map = mmcc_xo_gpll0_mmpll0_map,
314 .freq_tbl = ftbl_ahb_clk_src,
315 .clkr.hw.init = &(struct clk_init_data){
316 .name = "ahb_clk_src",
317 .parent_data = mmcc_xo_gpll0_mmpll0,
318 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
319 .ops = &clk_rcg2_ops,
320 },
321 };
322
323 static const struct freq_tbl ftbl_axi_clk_src[] = {
324 F(75000000, P_GPLL0, 8, 0, 0),
325 F(150000000, P_GPLL0, 4, 0, 0),
326 F(333430000, P_MMPLL1, 3.5, 0, 0),
327 F(466800000, P_MMPLL1, 2.5, 0, 0),
328 { }
329 };
330
331 static const struct freq_tbl ftbl_axi_clk_src_8992[] = {
332 F(75000000, P_GPLL0, 8, 0, 0),
333 F(150000000, P_GPLL0, 4, 0, 0),
334 F(300000000, P_GPLL0, 2, 0, 0),
335 F(404000000, P_MMPLL1, 2, 0, 0),
336 { }
337 };
338
339 static struct clk_rcg2 axi_clk_src = {
340 .cmd_rcgr = 0x5040,
341 .hid_width = 5,
342 .parent_map = mmcc_xo_gpll0_mmpll1_map,
343 .freq_tbl = ftbl_axi_clk_src,
344 .clkr.hw.init = &(struct clk_init_data){
345 .name = "axi_clk_src",
346 .parent_data = mmcc_xo_gpll0_mmpll1,
347 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll1),
348 .ops = &clk_rcg2_ops,
349 },
350 };
351
352 static const struct freq_tbl ftbl_csi0_1_2_3_clk_src[] = {
353 F(100000000, P_GPLL0, 6, 0, 0),
354 F(240000000, P_GPLL0, 2.5, 0, 0),
355 F(266670000, P_MMPLL0, 3, 0, 0),
356 { }
357 };
358
359 static const struct freq_tbl ftbl_csi0_1_2_3_clk_src_8992[] = {
360 F(100000000, P_GPLL0, 6, 0, 0),
361 F(266670000, P_MMPLL0, 3, 0, 0),
362 { }
363 };
364
365 static struct clk_rcg2 csi0_clk_src = {
366 .cmd_rcgr = 0x3090,
367 .hid_width = 5,
368 .parent_map = mmcc_xo_gpll0_mmpll0_map,
369 .freq_tbl = ftbl_csi0_1_2_3_clk_src,
370 .clkr.hw.init = &(struct clk_init_data){
371 .name = "csi0_clk_src",
372 .parent_data = mmcc_xo_gpll0_mmpll0,
373 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
374 .ops = &clk_rcg2_ops,
375 },
376 };
377
378 static const struct freq_tbl ftbl_vcodec0_clk_src[] = {
379 F(66670000, P_GPLL0, 9, 0, 0),
380 F(100000000, P_GPLL0, 6, 0, 0),
381 F(133330000, P_GPLL0, 4.5, 0, 0),
382 F(150000000, P_GPLL0, 4, 0, 0),
383 F(200000000, P_MMPLL0, 4, 0, 0),
384 F(240000000, P_GPLL0, 2.5, 0, 0),
385 F(266670000, P_MMPLL0, 3, 0, 0),
386 F(320000000, P_MMPLL0, 2.5, 0, 0),
387 F(510000000, P_MMPLL3, 2, 0, 0),
388 { }
389 };
390
391 static const struct freq_tbl ftbl_vcodec0_clk_src_8992[] = {
392 F(66670000, P_GPLL0, 9, 0, 0),
393 F(100000000, P_GPLL0, 6, 0, 0),
394 F(133330000, P_GPLL0, 4.5, 0, 0),
395 F(200000000, P_MMPLL0, 4, 0, 0),
396 F(320000000, P_MMPLL0, 2.5, 0, 0),
397 F(510000000, P_MMPLL3, 2, 0, 0),
398 { }
399 };
400
401 static struct clk_rcg2 vcodec0_clk_src = {
402 .cmd_rcgr = 0x1000,
403 .mnd_width = 8,
404 .hid_width = 5,
405 .parent_map = mmcc_xo_gpll0_mmpll0_mmpll3_map,
406 .freq_tbl = ftbl_vcodec0_clk_src,
407 .clkr.hw.init = &(struct clk_init_data){
408 .name = "vcodec0_clk_src",
409 .parent_data = mmcc_xo_gpll0_mmpll0_mmpll3,
410 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0_mmpll3),
411 .ops = &clk_rcg2_ops,
412 },
413 };
414
415 static struct clk_rcg2 csi1_clk_src = {
416 .cmd_rcgr = 0x3100,
417 .hid_width = 5,
418 .parent_map = mmcc_xo_gpll0_mmpll0_map,
419 .freq_tbl = ftbl_csi0_1_2_3_clk_src,
420 .clkr.hw.init = &(struct clk_init_data){
421 .name = "csi1_clk_src",
422 .parent_data = mmcc_xo_gpll0_mmpll0,
423 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
424 .ops = &clk_rcg2_ops,
425 },
426 };
427
428 static struct clk_rcg2 csi2_clk_src = {
429 .cmd_rcgr = 0x3160,
430 .hid_width = 5,
431 .parent_map = mmcc_xo_gpll0_mmpll0_map,
432 .freq_tbl = ftbl_csi0_1_2_3_clk_src,
433 .clkr.hw.init = &(struct clk_init_data){
434 .name = "csi2_clk_src",
435 .parent_data = mmcc_xo_gpll0_mmpll0,
436 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
437 .ops = &clk_rcg2_ops,
438 },
439 };
440
441 static struct clk_rcg2 csi3_clk_src = {
442 .cmd_rcgr = 0x31c0,
443 .hid_width = 5,
444 .parent_map = mmcc_xo_gpll0_mmpll0_map,
445 .freq_tbl = ftbl_csi0_1_2_3_clk_src,
446 .clkr.hw.init = &(struct clk_init_data){
447 .name = "csi3_clk_src",
448 .parent_data = mmcc_xo_gpll0_mmpll0,
449 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
450 .ops = &clk_rcg2_ops,
451 },
452 };
453
454 static const struct freq_tbl ftbl_vfe0_clk_src[] = {
455 F(80000000, P_GPLL0, 7.5, 0, 0),
456 F(100000000, P_GPLL0, 6, 0, 0),
457 F(200000000, P_GPLL0, 3, 0, 0),
458 F(320000000, P_MMPLL0, 2.5, 0, 0),
459 F(400000000, P_MMPLL0, 2, 0, 0),
460 F(480000000, P_MMPLL4, 2, 0, 0),
461 F(533330000, P_MMPLL0, 1.5, 0, 0),
462 F(600000000, P_GPLL0, 1, 0, 0),
463 { }
464 };
465
466 static const struct freq_tbl ftbl_vfe0_1_clk_src_8992[] = {
467 F(80000000, P_GPLL0, 7.5, 0, 0),
468 F(100000000, P_GPLL0, 6, 0, 0),
469 F(200000000, P_GPLL0, 3, 0, 0),
470 F(320000000, P_MMPLL0, 2.5, 0, 0),
471 F(480000000, P_MMPLL4, 2, 0, 0),
472 F(600000000, P_GPLL0, 1, 0, 0),
473 { }
474 };
475
476 static struct clk_rcg2 vfe0_clk_src = {
477 .cmd_rcgr = 0x3600,
478 .hid_width = 5,
479 .parent_map = mmcc_xo_gpll0_mmpll0_mmpll4_map,
480 .freq_tbl = ftbl_vfe0_clk_src,
481 .clkr.hw.init = &(struct clk_init_data){
482 .name = "vfe0_clk_src",
483 .parent_data = mmcc_xo_gpll0_mmpll0_mmpll4,
484 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0_mmpll4),
485 .ops = &clk_rcg2_ops,
486 },
487 };
488
489 static const struct freq_tbl ftbl_vfe1_clk_src[] = {
490 F(80000000, P_GPLL0, 7.5, 0, 0),
491 F(100000000, P_GPLL0, 6, 0, 0),
492 F(200000000, P_GPLL0, 3, 0, 0),
493 F(320000000, P_MMPLL0, 2.5, 0, 0),
494 F(400000000, P_MMPLL0, 2, 0, 0),
495 F(533330000, P_MMPLL0, 1.5, 0, 0),
496 { }
497 };
498
499 static struct clk_rcg2 vfe1_clk_src = {
500 .cmd_rcgr = 0x3620,
501 .hid_width = 5,
502 .parent_map = mmcc_xo_gpll0_mmpll0_mmpll4_map,
503 .freq_tbl = ftbl_vfe1_clk_src,
504 .clkr.hw.init = &(struct clk_init_data){
505 .name = "vfe1_clk_src",
506 .parent_data = mmcc_xo_gpll0_mmpll0_mmpll4,
507 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0_mmpll4),
508 .ops = &clk_rcg2_ops,
509 },
510 };
511
512 static const struct freq_tbl ftbl_cpp_clk_src[] = {
513 F(100000000, P_GPLL0, 6, 0, 0),
514 F(200000000, P_GPLL0, 3, 0, 0),
515 F(320000000, P_MMPLL0, 2.5, 0, 0),
516 F(480000000, P_MMPLL4, 2, 0, 0),
517 F(600000000, P_GPLL0, 1, 0, 0),
518 F(640000000, P_MMPLL4, 1.5, 0, 0),
519 { }
520 };
521
522 static const struct freq_tbl ftbl_cpp_clk_src_8992[] = {
523 F(100000000, P_GPLL0, 6, 0, 0),
524 F(200000000, P_GPLL0, 3, 0, 0),
525 F(320000000, P_MMPLL0, 2.5, 0, 0),
526 F(480000000, P_MMPLL4, 2, 0, 0),
527 F(640000000, P_MMPLL4, 1.5, 0, 0),
528 { }
529 };
530
531 static struct clk_rcg2 cpp_clk_src = {
532 .cmd_rcgr = 0x3640,
533 .hid_width = 5,
534 .parent_map = mmcc_xo_gpll0_mmpll0_mmpll4_map,
535 .freq_tbl = ftbl_cpp_clk_src,
536 .clkr.hw.init = &(struct clk_init_data){
537 .name = "cpp_clk_src",
538 .parent_data = mmcc_xo_gpll0_mmpll0_mmpll4,
539 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0_mmpll4),
540 .ops = &clk_rcg2_ops,
541 },
542 };
543
544 static const struct freq_tbl ftbl_jpeg0_1_clk_src[] = {
545 F(75000000, P_GPLL0, 8, 0, 0),
546 F(150000000, P_GPLL0, 4, 0, 0),
547 F(228570000, P_MMPLL0, 3.5, 0, 0),
548 F(266670000, P_MMPLL0, 3, 0, 0),
549 F(320000000, P_MMPLL0, 2.5, 0, 0),
550 F(480000000, P_MMPLL4, 2, 0, 0),
551 { }
552 };
553
554 static struct clk_rcg2 jpeg1_clk_src = {
555 .cmd_rcgr = 0x3520,
556 .hid_width = 5,
557 .parent_map = mmcc_xo_gpll0_mmpll0_mmpll4_map,
558 .freq_tbl = ftbl_jpeg0_1_clk_src,
559 .clkr.hw.init = &(struct clk_init_data){
560 .name = "jpeg1_clk_src",
561 .parent_data = mmcc_xo_gpll0_mmpll0_mmpll4,
562 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0_mmpll4),
563 .ops = &clk_rcg2_ops,
564 },
565 };
566
567 static const struct freq_tbl ftbl_jpeg2_clk_src[] = {
568 F(75000000, P_GPLL0, 8, 0, 0),
569 F(133330000, P_GPLL0, 4.5, 0, 0),
570 F(150000000, P_GPLL0, 4, 0, 0),
571 F(228570000, P_MMPLL0, 3.5, 0, 0),
572 F(266670000, P_MMPLL0, 3, 0, 0),
573 F(320000000, P_MMPLL0, 2.5, 0, 0),
574 { }
575 };
576
577 static struct clk_rcg2 jpeg2_clk_src = {
578 .cmd_rcgr = 0x3540,
579 .hid_width = 5,
580 .parent_map = mmcc_xo_gpll0_mmpll0_map,
581 .freq_tbl = ftbl_jpeg2_clk_src,
582 .clkr.hw.init = &(struct clk_init_data){
583 .name = "jpeg2_clk_src",
584 .parent_data = mmcc_xo_gpll0_mmpll0,
585 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
586 .ops = &clk_rcg2_ops,
587 },
588 };
589
590 static const struct freq_tbl ftbl_csi2phytimer_clk_src[] = {
591 F(50000000, P_GPLL0, 12, 0, 0),
592 F(100000000, P_GPLL0, 6, 0, 0),
593 F(200000000, P_MMPLL0, 4, 0, 0),
594 { }
595 };
596
597 static struct clk_rcg2 csi2phytimer_clk_src = {
598 .cmd_rcgr = 0x3060,
599 .hid_width = 5,
600 .parent_map = mmcc_xo_gpll0_mmpll0_map,
601 .freq_tbl = ftbl_csi2phytimer_clk_src,
602 .clkr.hw.init = &(struct clk_init_data){
603 .name = "csi2phytimer_clk_src",
604 .parent_data = mmcc_xo_gpll0_mmpll0,
605 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
606 .ops = &clk_rcg2_ops,
607 },
608 };
609
610 static const struct freq_tbl ftbl_fd_core_clk_src[] = {
611 F(60000000, P_GPLL0, 10, 0, 0),
612 F(200000000, P_GPLL0, 3, 0, 0),
613 F(320000000, P_MMPLL0, 2.5, 0, 0),
614 F(400000000, P_MMPLL0, 2, 0, 0),
615 { }
616 };
617
618 static struct clk_rcg2 fd_core_clk_src = {
619 .cmd_rcgr = 0x3b00,
620 .hid_width = 5,
621 .parent_map = mmcc_xo_gpll0_mmpll0_map,
622 .freq_tbl = ftbl_fd_core_clk_src,
623 .clkr.hw.init = &(struct clk_init_data){
624 .name = "fd_core_clk_src",
625 .parent_data = mmcc_xo_gpll0_mmpll0,
626 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
627 .ops = &clk_rcg2_ops,
628 },
629 };
630
631 static const struct freq_tbl ftbl_mdp_clk_src[] = {
632 F(85710000, P_GPLL0, 7, 0, 0),
633 F(100000000, P_GPLL0, 6, 0, 0),
634 F(120000000, P_GPLL0, 5, 0, 0),
635 F(150000000, P_GPLL0, 4, 0, 0),
636 F(171430000, P_GPLL0, 3.5, 0, 0),
637 F(200000000, P_GPLL0, 3, 0, 0),
638 F(240000000, P_GPLL0, 2.5, 0, 0),
639 F(266670000, P_MMPLL0, 3, 0, 0),
640 F(300000000, P_GPLL0, 2, 0, 0),
641 F(320000000, P_MMPLL0, 2.5, 0, 0),
642 F(400000000, P_MMPLL0, 2, 0, 0),
643 { }
644 };
645
646 static const struct freq_tbl ftbl_mdp_clk_src_8992[] = {
647 F(85710000, P_GPLL0, 7, 0, 0),
648 F(171430000, P_GPLL0, 3.5, 0, 0),
649 F(200000000, P_GPLL0, 3, 0, 0),
650 F(240000000, P_GPLL0, 2.5, 0, 0),
651 F(266670000, P_MMPLL0, 3, 0, 0),
652 F(320000000, P_MMPLL0, 2.5, 0, 0),
653 F(400000000, P_MMPLL0, 2, 0, 0),
654 { }
655 };
656
657 static struct clk_rcg2 mdp_clk_src = {
658 .cmd_rcgr = 0x2040,
659 .hid_width = 5,
660 .parent_map = mmcc_xo_gpll0_mmpll0_map,
661 .freq_tbl = ftbl_mdp_clk_src,
662 .clkr.hw.init = &(struct clk_init_data){
663 .name = "mdp_clk_src",
664 .parent_data = mmcc_xo_gpll0_mmpll0,
665 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
666 .ops = &clk_rcg2_ops,
667 },
668 };
669
670 static struct clk_rcg2 pclk0_clk_src = {
671 .cmd_rcgr = 0x2000,
672 .mnd_width = 8,
673 .hid_width = 5,
674 .parent_map = mmcc_xo_dsi0pll_dsi1pll_map,
675 .clkr.hw.init = &(struct clk_init_data){
676 .name = "pclk0_clk_src",
677 .parent_data = mmcc_xo_dsi0pll_dsi1pll,
678 .num_parents = ARRAY_SIZE(mmcc_xo_dsi0pll_dsi1pll),
679 .ops = &clk_pixel_ops,
680 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
681 },
682 };
683
684 static struct clk_rcg2 pclk1_clk_src = {
685 .cmd_rcgr = 0x2020,
686 .mnd_width = 8,
687 .hid_width = 5,
688 .parent_map = mmcc_xo_dsi0pll_dsi1pll_map,
689 .clkr.hw.init = &(struct clk_init_data){
690 .name = "pclk1_clk_src",
691 .parent_data = mmcc_xo_dsi0pll_dsi1pll,
692 .num_parents = ARRAY_SIZE(mmcc_xo_dsi0pll_dsi1pll),
693 .ops = &clk_pixel_ops,
694 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
695 },
696 };
697
698 static const struct freq_tbl ftbl_ocmemnoc_clk_src[] = {
699 F(19200000, P_XO, 1, 0, 0),
700 F(75000000, P_GPLL0, 8, 0, 0),
701 F(100000000, P_GPLL0, 6, 0, 0),
702 F(150000000, P_GPLL0, 4, 0, 0),
703 F(228570000, P_MMPLL0, 3.5, 0, 0),
704 F(266670000, P_MMPLL0, 3, 0, 0),
705 F(320000000, P_MMPLL0, 2.5, 0, 0),
706 F(400000000, P_MMPLL0, 2, 0, 0),
707 { }
708 };
709
710 static const struct freq_tbl ftbl_ocmemnoc_clk_src_8992[] = {
711 F(19200000, P_XO, 1, 0, 0),
712 F(75000000, P_GPLL0, 8, 0, 0),
713 F(100000000, P_GPLL0, 6, 0, 0),
714 F(150000000, P_GPLL0, 4, 0, 0),
715 F(320000000, P_MMPLL0, 2.5, 0, 0),
716 F(400000000, P_MMPLL0, 2, 0, 0),
717 { }
718 };
719
720 static struct clk_rcg2 ocmemnoc_clk_src = {
721 .cmd_rcgr = 0x5090,
722 .hid_width = 5,
723 .parent_map = mmcc_xo_gpll0_mmpll0_map,
724 .freq_tbl = ftbl_ocmemnoc_clk_src,
725 .clkr.hw.init = &(struct clk_init_data){
726 .name = "ocmemnoc_clk_src",
727 .parent_data = mmcc_xo_gpll0_mmpll0,
728 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
729 .ops = &clk_rcg2_ops,
730 },
731 };
732
733 static const struct freq_tbl ftbl_cci_clk_src[] = {
734 F(19200000, P_XO, 1, 0, 0),
735 F(37500000, P_GPLL0, 16, 0, 0),
736 F(50000000, P_GPLL0, 12, 0, 0),
737 F(100000000, P_GPLL0, 6, 0, 0),
738 { }
739 };
740
741 static struct clk_rcg2 cci_clk_src = {
742 .cmd_rcgr = 0x3300,
743 .mnd_width = 8,
744 .hid_width = 5,
745 .parent_map = mmcc_xo_gpll0_map,
746 .freq_tbl = ftbl_cci_clk_src,
747 .clkr.hw.init = &(struct clk_init_data){
748 .name = "cci_clk_src",
749 .parent_data = mmcc_xo_gpll0,
750 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0),
751 .ops = &clk_rcg2_ops,
752 },
753 };
754
755 static const struct freq_tbl ftbl_mmss_gp0_1_clk_src[] = {
756 F(10000, P_XO, 16, 10, 120),
757 F(24000, P_GPLL0, 16, 1, 50),
758 F(6000000, P_GPLL0, 10, 1, 10),
759 F(12000000, P_GPLL0, 10, 1, 5),
760 F(13000000, P_GPLL0, 4, 13, 150),
761 F(24000000, P_GPLL0, 5, 1, 5),
762 { }
763 };
764
765 static struct clk_rcg2 mmss_gp0_clk_src = {
766 .cmd_rcgr = 0x3420,
767 .mnd_width = 8,
768 .hid_width = 5,
769 .parent_map = mmcc_xo_gpll0_map,
770 .freq_tbl = ftbl_mmss_gp0_1_clk_src,
771 .clkr.hw.init = &(struct clk_init_data){
772 .name = "mmss_gp0_clk_src",
773 .parent_data = mmcc_xo_gpll0,
774 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0),
775 .ops = &clk_rcg2_ops,
776 },
777 };
778
779 static struct clk_rcg2 mmss_gp1_clk_src = {
780 .cmd_rcgr = 0x3450,
781 .mnd_width = 8,
782 .hid_width = 5,
783 .parent_map = mmcc_xo_gpll0_map,
784 .freq_tbl = ftbl_mmss_gp0_1_clk_src,
785 .clkr.hw.init = &(struct clk_init_data){
786 .name = "mmss_gp1_clk_src",
787 .parent_data = mmcc_xo_gpll0,
788 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0),
789 .ops = &clk_rcg2_ops,
790 },
791 };
792
793 static struct clk_rcg2 jpeg0_clk_src = {
794 .cmd_rcgr = 0x3500,
795 .hid_width = 5,
796 .parent_map = mmcc_xo_gpll0_mmpll0_mmpll4_map,
797 .freq_tbl = ftbl_jpeg0_1_clk_src,
798 .clkr.hw.init = &(struct clk_init_data){
799 .name = "jpeg0_clk_src",
800 .parent_data = mmcc_xo_gpll0_mmpll0_mmpll4,
801 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0_mmpll4),
802 .ops = &clk_rcg2_ops,
803 },
804 };
805
806 static struct clk_rcg2 jpeg_dma_clk_src = {
807 .cmd_rcgr = 0x3560,
808 .hid_width = 5,
809 .parent_map = mmcc_xo_gpll0_mmpll0_mmpll4_map,
810 .freq_tbl = ftbl_jpeg0_1_clk_src,
811 .clkr.hw.init = &(struct clk_init_data){
812 .name = "jpeg_dma_clk_src",
813 .parent_data = mmcc_xo_gpll0_mmpll0_mmpll4,
814 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0_mmpll4),
815 .ops = &clk_rcg2_ops,
816 },
817 };
818
819 static const struct freq_tbl ftbl_mclk0_1_2_3_clk_src[] = {
820 F(4800000, P_XO, 4, 0, 0),
821 F(6000000, P_GPLL0, 10, 1, 10),
822 F(8000000, P_GPLL0, 15, 1, 5),
823 F(9600000, P_XO, 2, 0, 0),
824 F(16000000, P_MMPLL0, 10, 1, 5),
825 F(19200000, P_XO, 1, 0, 0),
826 F(24000000, P_GPLL0, 5, 1, 5),
827 F(32000000, P_MMPLL0, 5, 1, 5),
828 F(48000000, P_GPLL0, 12.5, 0, 0),
829 F(64000000, P_MMPLL0, 12.5, 0, 0),
830 { }
831 };
832
833 static const struct freq_tbl ftbl_mclk0_clk_src_8992[] = {
834 F(4800000, P_XO, 4, 0, 0),
835 F(6000000, P_MMPLL4, 10, 1, 16),
836 F(8000000, P_MMPLL4, 10, 1, 12),
837 F(9600000, P_XO, 2, 0, 0),
838 F(12000000, P_MMPLL4, 10, 1, 8),
839 F(16000000, P_MMPLL4, 10, 1, 6),
840 F(19200000, P_XO, 1, 0, 0),
841 F(24000000, P_MMPLL4, 10, 1, 4),
842 F(32000000, P_MMPLL4, 10, 1, 3),
843 F(48000000, P_MMPLL4, 10, 1, 2),
844 F(64000000, P_MMPLL4, 15, 0, 0),
845 { }
846 };
847
848 static const struct freq_tbl ftbl_mclk1_2_3_clk_src_8992[] = {
849 F(4800000, P_XO, 4, 0, 0),
850 F(6000000, P_MMPLL4, 10, 1, 16),
851 F(8000000, P_MMPLL4, 10, 1, 12),
852 F(9600000, P_XO, 2, 0, 0),
853 F(16000000, P_MMPLL4, 10, 1, 6),
854 F(19200000, P_XO, 1, 0, 0),
855 F(24000000, P_MMPLL4, 10, 1, 4),
856 F(32000000, P_MMPLL4, 10, 1, 3),
857 F(48000000, P_MMPLL4, 10, 1, 2),
858 F(64000000, P_MMPLL4, 15, 0, 0),
859 { }
860 };
861
862 static struct clk_rcg2 mclk0_clk_src = {
863 .cmd_rcgr = 0x3360,
864 .mnd_width = 8,
865 .hid_width = 5,
866 .parent_map = mmcc_xo_gpll0_mmpll0_map,
867 .freq_tbl = ftbl_mclk0_1_2_3_clk_src,
868 .clkr.hw.init = &(struct clk_init_data){
869 .name = "mclk0_clk_src",
870 .parent_data = mmcc_xo_gpll0_mmpll0,
871 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
872 .ops = &clk_rcg2_ops,
873 },
874 };
875
876 static struct clk_rcg2 mclk1_clk_src = {
877 .cmd_rcgr = 0x3390,
878 .mnd_width = 8,
879 .hid_width = 5,
880 .parent_map = mmcc_xo_gpll0_mmpll0_map,
881 .freq_tbl = ftbl_mclk0_1_2_3_clk_src,
882 .clkr.hw.init = &(struct clk_init_data){
883 .name = "mclk1_clk_src",
884 .parent_data = mmcc_xo_gpll0_mmpll0,
885 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
886 .ops = &clk_rcg2_ops,
887 },
888 };
889
890 static struct clk_rcg2 mclk2_clk_src = {
891 .cmd_rcgr = 0x33c0,
892 .mnd_width = 8,
893 .hid_width = 5,
894 .parent_map = mmcc_xo_gpll0_mmpll0_map,
895 .freq_tbl = ftbl_mclk0_1_2_3_clk_src,
896 .clkr.hw.init = &(struct clk_init_data){
897 .name = "mclk2_clk_src",
898 .parent_data = mmcc_xo_gpll0_mmpll0,
899 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
900 .ops = &clk_rcg2_ops,
901 },
902 };
903
904 static struct clk_rcg2 mclk3_clk_src = {
905 .cmd_rcgr = 0x33f0,
906 .mnd_width = 8,
907 .hid_width = 5,
908 .parent_map = mmcc_xo_gpll0_mmpll0_map,
909 .freq_tbl = ftbl_mclk0_1_2_3_clk_src,
910 .clkr.hw.init = &(struct clk_init_data){
911 .name = "mclk3_clk_src",
912 .parent_data = mmcc_xo_gpll0_mmpll0,
913 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
914 .ops = &clk_rcg2_ops,
915 },
916 };
917
918 static const struct freq_tbl ftbl_csi0_1phytimer_clk_src[] = {
919 F(50000000, P_GPLL0, 12, 0, 0),
920 F(100000000, P_GPLL0, 6, 0, 0),
921 F(200000000, P_MMPLL0, 4, 0, 0),
922 { }
923 };
924
925 static struct clk_rcg2 csi0phytimer_clk_src = {
926 .cmd_rcgr = 0x3000,
927 .hid_width = 5,
928 .parent_map = mmcc_xo_gpll0_mmpll0_map,
929 .freq_tbl = ftbl_csi0_1phytimer_clk_src,
930 .clkr.hw.init = &(struct clk_init_data){
931 .name = "csi0phytimer_clk_src",
932 .parent_data = mmcc_xo_gpll0_mmpll0,
933 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
934 .ops = &clk_rcg2_ops,
935 },
936 };
937
938 static struct clk_rcg2 csi1phytimer_clk_src = {
939 .cmd_rcgr = 0x3030,
940 .hid_width = 5,
941 .parent_map = mmcc_xo_gpll0_mmpll0_map,
942 .freq_tbl = ftbl_csi0_1phytimer_clk_src,
943 .clkr.hw.init = &(struct clk_init_data){
944 .name = "csi1phytimer_clk_src",
945 .parent_data = mmcc_xo_gpll0_mmpll0,
946 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
947 .ops = &clk_rcg2_ops,
948 },
949 };
950
951 static struct clk_rcg2 byte0_clk_src = {
952 .cmd_rcgr = 0x2120,
953 .hid_width = 5,
954 .parent_map = mmcc_xo_dsibyte_map,
955 .clkr.hw.init = &(struct clk_init_data){
956 .name = "byte0_clk_src",
957 .parent_data = mmcc_xo_dsibyte,
958 .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte),
959 .ops = &clk_byte2_ops,
960 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
961 },
962 };
963
964 static struct clk_rcg2 byte1_clk_src = {
965 .cmd_rcgr = 0x2140,
966 .hid_width = 5,
967 .parent_map = mmcc_xo_dsibyte_map,
968 .clkr.hw.init = &(struct clk_init_data){
969 .name = "byte1_clk_src",
970 .parent_data = mmcc_xo_dsibyte,
971 .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte),
972 .ops = &clk_byte2_ops,
973 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
974 },
975 };
976
977 static struct freq_tbl ftbl_mdss_esc0_1_clk[] = {
978 F(19200000, P_XO, 1, 0, 0),
979 { }
980 };
981
982 static struct clk_rcg2 esc0_clk_src = {
983 .cmd_rcgr = 0x2160,
984 .hid_width = 5,
985 .parent_map = mmcc_xo_dsibyte_map,
986 .freq_tbl = ftbl_mdss_esc0_1_clk,
987 .clkr.hw.init = &(struct clk_init_data){
988 .name = "esc0_clk_src",
989 .parent_data = mmcc_xo_dsibyte,
990 .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte),
991 .ops = &clk_rcg2_ops,
992 },
993 };
994
995 static struct clk_rcg2 esc1_clk_src = {
996 .cmd_rcgr = 0x2180,
997 .hid_width = 5,
998 .parent_map = mmcc_xo_dsibyte_map,
999 .freq_tbl = ftbl_mdss_esc0_1_clk,
1000 .clkr.hw.init = &(struct clk_init_data){
1001 .name = "esc1_clk_src",
1002 .parent_data = mmcc_xo_dsibyte,
1003 .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte),
1004 .ops = &clk_rcg2_ops,
1005 },
1006 };
1007
1008 static struct freq_tbl extpclk_freq_tbl[] = {
1009 { .src = P_HDMIPLL },
1010 { }
1011 };
1012
1013 static struct clk_rcg2 extpclk_clk_src = {
1014 .cmd_rcgr = 0x2060,
1015 .hid_width = 5,
1016 .parent_map = mmss_xo_hdmi_map,
1017 .freq_tbl = extpclk_freq_tbl,
1018 .clkr.hw.init = &(struct clk_init_data){
1019 .name = "extpclk_clk_src",
1020 .parent_data = mmss_xo_hdmi,
1021 .num_parents = ARRAY_SIZE(mmss_xo_hdmi),
1022 .ops = &clk_rcg2_ops,
1023 .flags = CLK_SET_RATE_PARENT,
1024 },
1025 };
1026
1027 static struct freq_tbl ftbl_hdmi_clk_src[] = {
1028 F(19200000, P_XO, 1, 0, 0),
1029 { }
1030 };
1031
1032 static struct clk_rcg2 hdmi_clk_src = {
1033 .cmd_rcgr = 0x2100,
1034 .hid_width = 5,
1035 .parent_map = mmcc_xo_gpll0_map,
1036 .freq_tbl = ftbl_hdmi_clk_src,
1037 .clkr.hw.init = &(struct clk_init_data){
1038 .name = "hdmi_clk_src",
1039 .parent_data = mmcc_xo_gpll0,
1040 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0),
1041 .ops = &clk_rcg2_ops,
1042 },
1043 };
1044
1045 static struct freq_tbl ftbl_mdss_vsync_clk[] = {
1046 F(19200000, P_XO, 1, 0, 0),
1047 { }
1048 };
1049
1050 static struct clk_rcg2 vsync_clk_src = {
1051 .cmd_rcgr = 0x2080,
1052 .hid_width = 5,
1053 .parent_map = mmcc_xo_gpll0_map,
1054 .freq_tbl = ftbl_mdss_vsync_clk,
1055 .clkr.hw.init = &(struct clk_init_data){
1056 .name = "vsync_clk_src",
1057 .parent_data = mmcc_xo_gpll0,
1058 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0),
1059 .ops = &clk_rcg2_ops,
1060 },
1061 };
1062
1063 static const struct freq_tbl ftbl_rbbmtimer_clk_src[] = {
1064 F(19200000, P_XO, 1, 0, 0),
1065 { }
1066 };
1067
1068 static struct clk_rcg2 rbbmtimer_clk_src = {
1069 .cmd_rcgr = 0x4090,
1070 .hid_width = 5,
1071 .parent_map = mmcc_xo_gpll0_map,
1072 .freq_tbl = ftbl_rbbmtimer_clk_src,
1073 .clkr.hw.init = &(struct clk_init_data){
1074 .name = "rbbmtimer_clk_src",
1075 .parent_data = mmcc_xo_gpll0,
1076 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0),
1077 .ops = &clk_rcg2_ops,
1078 },
1079 };
1080
1081 static struct clk_branch camss_ahb_clk = {
1082 .halt_reg = 0x348c,
1083 .clkr = {
1084 .enable_reg = 0x348c,
1085 .enable_mask = BIT(0),
1086 .hw.init = &(struct clk_init_data){
1087 .name = "camss_ahb_clk",
1088 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1089 .num_parents = 1,
1090 .flags = CLK_SET_RATE_PARENT,
1091 .ops = &clk_branch2_ops,
1092 },
1093 },
1094 };
1095
1096 static struct clk_branch camss_cci_cci_ahb_clk = {
1097 .halt_reg = 0x3348,
1098 .clkr = {
1099 .enable_reg = 0x3348,
1100 .enable_mask = BIT(0),
1101 .hw.init = &(struct clk_init_data){
1102 .name = "camss_cci_cci_ahb_clk",
1103 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1104 .num_parents = 1,
1105 .flags = CLK_SET_RATE_PARENT,
1106 .ops = &clk_branch2_ops,
1107 },
1108 },
1109 };
1110
1111 static struct clk_branch camss_cci_cci_clk = {
1112 .halt_reg = 0x3344,
1113 .clkr = {
1114 .enable_reg = 0x3344,
1115 .enable_mask = BIT(0),
1116 .hw.init = &(struct clk_init_data){
1117 .name = "camss_cci_cci_clk",
1118 .parent_hws = (const struct clk_hw *[]){ &cci_clk_src.clkr.hw },
1119 .num_parents = 1,
1120 .ops = &clk_branch2_ops,
1121 },
1122 },
1123 };
1124
1125 static struct clk_branch camss_vfe_cpp_ahb_clk = {
1126 .halt_reg = 0x36b4,
1127 .clkr = {
1128 .enable_reg = 0x36b4,
1129 .enable_mask = BIT(0),
1130 .hw.init = &(struct clk_init_data){
1131 .name = "camss_vfe_cpp_ahb_clk",
1132 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1133 .num_parents = 1,
1134 .flags = CLK_SET_RATE_PARENT,
1135 .ops = &clk_branch2_ops,
1136 },
1137 },
1138 };
1139
1140 static struct clk_branch camss_vfe_cpp_axi_clk = {
1141 .halt_reg = 0x36c4,
1142 .clkr = {
1143 .enable_reg = 0x36c4,
1144 .enable_mask = BIT(0),
1145 .hw.init = &(struct clk_init_data){
1146 .name = "camss_vfe_cpp_axi_clk",
1147 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
1148 .num_parents = 1,
1149 .ops = &clk_branch2_ops,
1150 },
1151 },
1152 };
1153
1154 static struct clk_branch camss_vfe_cpp_clk = {
1155 .halt_reg = 0x36b0,
1156 .clkr = {
1157 .enable_reg = 0x36b0,
1158 .enable_mask = BIT(0),
1159 .hw.init = &(struct clk_init_data){
1160 .name = "camss_vfe_cpp_clk",
1161 .parent_hws = (const struct clk_hw *[]){ &cpp_clk_src.clkr.hw },
1162 .num_parents = 1,
1163 .ops = &clk_branch2_ops,
1164 },
1165 },
1166 };
1167
1168 static struct clk_branch camss_csi0_ahb_clk = {
1169 .halt_reg = 0x30bc,
1170 .clkr = {
1171 .enable_reg = 0x30bc,
1172 .enable_mask = BIT(0),
1173 .hw.init = &(struct clk_init_data){
1174 .name = "camss_csi0_ahb_clk",
1175 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1176 .num_parents = 1,
1177 .flags = CLK_SET_RATE_PARENT,
1178 .ops = &clk_branch2_ops,
1179 },
1180 },
1181 };
1182
1183 static struct clk_branch camss_csi0_clk = {
1184 .halt_reg = 0x30b4,
1185 .clkr = {
1186 .enable_reg = 0x30b4,
1187 .enable_mask = BIT(0),
1188 .hw.init = &(struct clk_init_data){
1189 .name = "camss_csi0_clk",
1190 .parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
1191 .num_parents = 1,
1192 .ops = &clk_branch2_ops,
1193 },
1194 },
1195 };
1196
1197 static struct clk_branch camss_csi0phy_clk = {
1198 .halt_reg = 0x30c4,
1199 .clkr = {
1200 .enable_reg = 0x30c4,
1201 .enable_mask = BIT(0),
1202 .hw.init = &(struct clk_init_data){
1203 .name = "camss_csi0phy_clk",
1204 .parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
1205 .num_parents = 1,
1206 .ops = &clk_branch2_ops,
1207 },
1208 },
1209 };
1210
1211 static struct clk_branch camss_csi0pix_clk = {
1212 .halt_reg = 0x30e4,
1213 .clkr = {
1214 .enable_reg = 0x30e4,
1215 .enable_mask = BIT(0),
1216 .hw.init = &(struct clk_init_data){
1217 .name = "camss_csi0pix_clk",
1218 .parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
1219 .num_parents = 1,
1220 .ops = &clk_branch2_ops,
1221 },
1222 },
1223 };
1224
1225 static struct clk_branch camss_csi0rdi_clk = {
1226 .halt_reg = 0x30d4,
1227 .clkr = {
1228 .enable_reg = 0x30d4,
1229 .enable_mask = BIT(0),
1230 .hw.init = &(struct clk_init_data){
1231 .name = "camss_csi0rdi_clk",
1232 .parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
1233 .num_parents = 1,
1234 .ops = &clk_branch2_ops,
1235 },
1236 },
1237 };
1238
1239 static struct clk_branch camss_csi1_ahb_clk = {
1240 .halt_reg = 0x3128,
1241 .clkr = {
1242 .enable_reg = 0x3128,
1243 .enable_mask = BIT(0),
1244 .hw.init = &(struct clk_init_data){
1245 .name = "camss_csi1_ahb_clk",
1246 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1247 .num_parents = 1,
1248 .flags = CLK_SET_RATE_PARENT,
1249 .ops = &clk_branch2_ops,
1250 },
1251 },
1252 };
1253
1254 static struct clk_branch camss_csi1_clk = {
1255 .halt_reg = 0x3124,
1256 .clkr = {
1257 .enable_reg = 0x3124,
1258 .enable_mask = BIT(0),
1259 .hw.init = &(struct clk_init_data){
1260 .name = "camss_csi1_clk",
1261 .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1262 .num_parents = 1,
1263 .ops = &clk_branch2_ops,
1264 },
1265 },
1266 };
1267
1268 static struct clk_branch camss_csi1phy_clk = {
1269 .halt_reg = 0x3134,
1270 .clkr = {
1271 .enable_reg = 0x3134,
1272 .enable_mask = BIT(0),
1273 .hw.init = &(struct clk_init_data){
1274 .name = "camss_csi1phy_clk",
1275 .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1276 .num_parents = 1,
1277 .ops = &clk_branch2_ops,
1278 },
1279 },
1280 };
1281
1282 static struct clk_branch camss_csi1pix_clk = {
1283 .halt_reg = 0x3154,
1284 .clkr = {
1285 .enable_reg = 0x3154,
1286 .enable_mask = BIT(0),
1287 .hw.init = &(struct clk_init_data){
1288 .name = "camss_csi1pix_clk",
1289 .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1290 .num_parents = 1,
1291 .ops = &clk_branch2_ops,
1292 },
1293 },
1294 };
1295
1296 static struct clk_branch camss_csi1rdi_clk = {
1297 .halt_reg = 0x3144,
1298 .clkr = {
1299 .enable_reg = 0x3144,
1300 .enable_mask = BIT(0),
1301 .hw.init = &(struct clk_init_data){
1302 .name = "camss_csi1rdi_clk",
1303 .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1304 .num_parents = 1,
1305 .ops = &clk_branch2_ops,
1306 },
1307 },
1308 };
1309
1310 static struct clk_branch camss_csi2_ahb_clk = {
1311 .halt_reg = 0x3188,
1312 .clkr = {
1313 .enable_reg = 0x3188,
1314 .enable_mask = BIT(0),
1315 .hw.init = &(struct clk_init_data){
1316 .name = "camss_csi2_ahb_clk",
1317 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1318 .num_parents = 1,
1319 .flags = CLK_SET_RATE_PARENT,
1320 .ops = &clk_branch2_ops,
1321 },
1322 },
1323 };
1324
1325 static struct clk_branch camss_csi2_clk = {
1326 .halt_reg = 0x3184,
1327 .clkr = {
1328 .enable_reg = 0x3184,
1329 .enable_mask = BIT(0),
1330 .hw.init = &(struct clk_init_data){
1331 .name = "camss_csi2_clk",
1332 .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1333 .num_parents = 1,
1334 .ops = &clk_branch2_ops,
1335 },
1336 },
1337 };
1338
1339 static struct clk_branch camss_csi2phy_clk = {
1340 .halt_reg = 0x3194,
1341 .clkr = {
1342 .enable_reg = 0x3194,
1343 .enable_mask = BIT(0),
1344 .hw.init = &(struct clk_init_data){
1345 .name = "camss_csi2phy_clk",
1346 .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1347 .num_parents = 1,
1348 .ops = &clk_branch2_ops,
1349 },
1350 },
1351 };
1352
1353 static struct clk_branch camss_csi2pix_clk = {
1354 .halt_reg = 0x31b4,
1355 .clkr = {
1356 .enable_reg = 0x31b4,
1357 .enable_mask = BIT(0),
1358 .hw.init = &(struct clk_init_data){
1359 .name = "camss_csi2pix_clk",
1360 .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1361 .num_parents = 1,
1362 .ops = &clk_branch2_ops,
1363 },
1364 },
1365 };
1366
1367 static struct clk_branch camss_csi2rdi_clk = {
1368 .halt_reg = 0x31a4,
1369 .clkr = {
1370 .enable_reg = 0x31a4,
1371 .enable_mask = BIT(0),
1372 .hw.init = &(struct clk_init_data){
1373 .name = "camss_csi2rdi_clk",
1374 .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1375 .num_parents = 1,
1376 .ops = &clk_branch2_ops,
1377 },
1378 },
1379 };
1380
1381 static struct clk_branch camss_csi3_ahb_clk = {
1382 .halt_reg = 0x31e8,
1383 .clkr = {
1384 .enable_reg = 0x31e8,
1385 .enable_mask = BIT(0),
1386 .hw.init = &(struct clk_init_data){
1387 .name = "camss_csi3_ahb_clk",
1388 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1389 .num_parents = 1,
1390 .flags = CLK_SET_RATE_PARENT,
1391 .ops = &clk_branch2_ops,
1392 },
1393 },
1394 };
1395
1396 static struct clk_branch camss_csi3_clk = {
1397 .halt_reg = 0x31e4,
1398 .clkr = {
1399 .enable_reg = 0x31e4,
1400 .enable_mask = BIT(0),
1401 .hw.init = &(struct clk_init_data){
1402 .name = "camss_csi3_clk",
1403 .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1404 .num_parents = 1,
1405 .ops = &clk_branch2_ops,
1406 },
1407 },
1408 };
1409
1410 static struct clk_branch camss_csi3phy_clk = {
1411 .halt_reg = 0x31f4,
1412 .clkr = {
1413 .enable_reg = 0x31f4,
1414 .enable_mask = BIT(0),
1415 .hw.init = &(struct clk_init_data){
1416 .name = "camss_csi3phy_clk",
1417 .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1418 .num_parents = 1,
1419 .ops = &clk_branch2_ops,
1420 },
1421 },
1422 };
1423
1424 static struct clk_branch camss_csi3pix_clk = {
1425 .halt_reg = 0x3214,
1426 .clkr = {
1427 .enable_reg = 0x3214,
1428 .enable_mask = BIT(0),
1429 .hw.init = &(struct clk_init_data){
1430 .name = "camss_csi3pix_clk",
1431 .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1432 .num_parents = 1,
1433 .ops = &clk_branch2_ops,
1434 },
1435 },
1436 };
1437
1438 static struct clk_branch camss_csi3rdi_clk = {
1439 .halt_reg = 0x3204,
1440 .clkr = {
1441 .enable_reg = 0x3204,
1442 .enable_mask = BIT(0),
1443 .hw.init = &(struct clk_init_data){
1444 .name = "camss_csi3rdi_clk",
1445 .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1446 .num_parents = 1,
1447 .ops = &clk_branch2_ops,
1448 },
1449 },
1450 };
1451
1452 static struct clk_branch camss_csi_vfe0_clk = {
1453 .halt_reg = 0x3704,
1454 .clkr = {
1455 .enable_reg = 0x3704,
1456 .enable_mask = BIT(0),
1457 .hw.init = &(struct clk_init_data){
1458 .name = "camss_csi_vfe0_clk",
1459 .parent_hws = (const struct clk_hw *[]){ &vfe0_clk_src.clkr.hw },
1460 .num_parents = 1,
1461 .ops = &clk_branch2_ops,
1462 },
1463 },
1464 };
1465
1466 static struct clk_branch camss_csi_vfe1_clk = {
1467 .halt_reg = 0x3714,
1468 .clkr = {
1469 .enable_reg = 0x3714,
1470 .enable_mask = BIT(0),
1471 .hw.init = &(struct clk_init_data){
1472 .name = "camss_csi_vfe1_clk",
1473 .parent_hws = (const struct clk_hw *[]){ &vfe1_clk_src.clkr.hw },
1474 .num_parents = 1,
1475 .ops = &clk_branch2_ops,
1476 },
1477 },
1478 };
1479
1480 static struct clk_branch camss_gp0_clk = {
1481 .halt_reg = 0x3444,
1482 .clkr = {
1483 .enable_reg = 0x3444,
1484 .enable_mask = BIT(0),
1485 .hw.init = &(struct clk_init_data){
1486 .name = "camss_gp0_clk",
1487 .parent_hws = (const struct clk_hw *[]){ &mmss_gp0_clk_src.clkr.hw },
1488 .num_parents = 1,
1489 .ops = &clk_branch2_ops,
1490 },
1491 },
1492 };
1493
1494 static struct clk_branch camss_gp1_clk = {
1495 .halt_reg = 0x3474,
1496 .clkr = {
1497 .enable_reg = 0x3474,
1498 .enable_mask = BIT(0),
1499 .hw.init = &(struct clk_init_data){
1500 .name = "camss_gp1_clk",
1501 .parent_hws = (const struct clk_hw *[]){ &mmss_gp1_clk_src.clkr.hw },
1502 .num_parents = 1,
1503 .ops = &clk_branch2_ops,
1504 },
1505 },
1506 };
1507
1508 static struct clk_branch camss_ispif_ahb_clk = {
1509 .halt_reg = 0x3224,
1510 .clkr = {
1511 .enable_reg = 0x3224,
1512 .enable_mask = BIT(0),
1513 .hw.init = &(struct clk_init_data){
1514 .name = "camss_ispif_ahb_clk",
1515 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1516 .num_parents = 1,
1517 .flags = CLK_SET_RATE_PARENT,
1518 .ops = &clk_branch2_ops,
1519 },
1520 },
1521 };
1522
1523 static struct clk_branch camss_jpeg_dma_clk = {
1524 .halt_reg = 0x35c0,
1525 .clkr = {
1526 .enable_reg = 0x35c0,
1527 .enable_mask = BIT(0),
1528 .hw.init = &(struct clk_init_data){
1529 .name = "camss_jpeg_dma_clk",
1530 .parent_hws = (const struct clk_hw *[]){ &jpeg_dma_clk_src.clkr.hw },
1531 .num_parents = 1,
1532 .ops = &clk_branch2_ops,
1533 },
1534 },
1535 };
1536
1537 static struct clk_branch camss_jpeg_jpeg0_clk = {
1538 .halt_reg = 0x35a8,
1539 .clkr = {
1540 .enable_reg = 0x35a8,
1541 .enable_mask = BIT(0),
1542 .hw.init = &(struct clk_init_data){
1543 .name = "camss_jpeg_jpeg0_clk",
1544 .parent_hws = (const struct clk_hw *[]){ &jpeg0_clk_src.clkr.hw },
1545 .num_parents = 1,
1546 .ops = &clk_branch2_ops,
1547 },
1548 },
1549 };
1550
1551 static struct clk_branch camss_jpeg_jpeg1_clk = {
1552 .halt_reg = 0x35ac,
1553 .clkr = {
1554 .enable_reg = 0x35ac,
1555 .enable_mask = BIT(0),
1556 .hw.init = &(struct clk_init_data){
1557 .name = "camss_jpeg_jpeg1_clk",
1558 .parent_hws = (const struct clk_hw *[]){ &jpeg1_clk_src.clkr.hw },
1559 .num_parents = 1,
1560 .ops = &clk_branch2_ops,
1561 },
1562 },
1563 };
1564
1565 static struct clk_branch camss_jpeg_jpeg2_clk = {
1566 .halt_reg = 0x35b0,
1567 .clkr = {
1568 .enable_reg = 0x35b0,
1569 .enable_mask = BIT(0),
1570 .hw.init = &(struct clk_init_data){
1571 .name = "camss_jpeg_jpeg2_clk",
1572 .parent_hws = (const struct clk_hw *[]){ &jpeg2_clk_src.clkr.hw },
1573 .num_parents = 1,
1574 .ops = &clk_branch2_ops,
1575 },
1576 },
1577 };
1578
1579 static struct clk_branch camss_jpeg_jpeg_ahb_clk = {
1580 .halt_reg = 0x35b4,
1581 .clkr = {
1582 .enable_reg = 0x35b4,
1583 .enable_mask = BIT(0),
1584 .hw.init = &(struct clk_init_data){
1585 .name = "camss_jpeg_jpeg_ahb_clk",
1586 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1587 .num_parents = 1,
1588 .flags = CLK_SET_RATE_PARENT,
1589 .ops = &clk_branch2_ops,
1590 },
1591 },
1592 };
1593
1594 static struct clk_branch camss_jpeg_jpeg_axi_clk = {
1595 .halt_reg = 0x35b8,
1596 .clkr = {
1597 .enable_reg = 0x35b8,
1598 .enable_mask = BIT(0),
1599 .hw.init = &(struct clk_init_data){
1600 .name = "camss_jpeg_jpeg_axi_clk",
1601 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
1602 .num_parents = 1,
1603 .ops = &clk_branch2_ops,
1604 },
1605 },
1606 };
1607
1608 static struct clk_branch camss_mclk0_clk = {
1609 .halt_reg = 0x3384,
1610 .clkr = {
1611 .enable_reg = 0x3384,
1612 .enable_mask = BIT(0),
1613 .hw.init = &(struct clk_init_data){
1614 .name = "camss_mclk0_clk",
1615 .parent_hws = (const struct clk_hw *[]){ &mclk0_clk_src.clkr.hw },
1616 .num_parents = 1,
1617 .ops = &clk_branch2_ops,
1618 },
1619 },
1620 };
1621
1622 static struct clk_branch camss_mclk1_clk = {
1623 .halt_reg = 0x33b4,
1624 .clkr = {
1625 .enable_reg = 0x33b4,
1626 .enable_mask = BIT(0),
1627 .hw.init = &(struct clk_init_data){
1628 .name = "camss_mclk1_clk",
1629 .parent_hws = (const struct clk_hw *[]){ &mclk1_clk_src.clkr.hw },
1630 .num_parents = 1,
1631 .ops = &clk_branch2_ops,
1632 },
1633 },
1634 };
1635
1636 static struct clk_branch camss_mclk2_clk = {
1637 .halt_reg = 0x33e4,
1638 .clkr = {
1639 .enable_reg = 0x33e4,
1640 .enable_mask = BIT(0),
1641 .hw.init = &(struct clk_init_data){
1642 .name = "camss_mclk2_clk",
1643 .parent_hws = (const struct clk_hw *[]){ &mclk2_clk_src.clkr.hw },
1644 .num_parents = 1,
1645 .ops = &clk_branch2_ops,
1646 },
1647 },
1648 };
1649
1650 static struct clk_branch camss_mclk3_clk = {
1651 .halt_reg = 0x3414,
1652 .clkr = {
1653 .enable_reg = 0x3414,
1654 .enable_mask = BIT(0),
1655 .hw.init = &(struct clk_init_data){
1656 .name = "camss_mclk3_clk",
1657 .parent_hws = (const struct clk_hw *[]){ &mclk3_clk_src.clkr.hw },
1658 .num_parents = 1,
1659 .ops = &clk_branch2_ops,
1660 },
1661 },
1662 };
1663
1664 static struct clk_branch camss_micro_ahb_clk = {
1665 .halt_reg = 0x3494,
1666 .clkr = {
1667 .enable_reg = 0x3494,
1668 .enable_mask = BIT(0),
1669 .hw.init = &(struct clk_init_data){
1670 .name = "camss_micro_ahb_clk",
1671 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1672 .num_parents = 1,
1673 .flags = CLK_SET_RATE_PARENT,
1674 .ops = &clk_branch2_ops,
1675 },
1676 },
1677 };
1678
1679 static struct clk_branch camss_phy0_csi0phytimer_clk = {
1680 .halt_reg = 0x3024,
1681 .clkr = {
1682 .enable_reg = 0x3024,
1683 .enable_mask = BIT(0),
1684 .hw.init = &(struct clk_init_data){
1685 .name = "camss_phy0_csi0phytimer_clk",
1686 .parent_hws = (const struct clk_hw *[]){ &csi0phytimer_clk_src.clkr.hw },
1687 .num_parents = 1,
1688 .ops = &clk_branch2_ops,
1689 },
1690 },
1691 };
1692
1693 static struct clk_branch camss_phy1_csi1phytimer_clk = {
1694 .halt_reg = 0x3054,
1695 .clkr = {
1696 .enable_reg = 0x3054,
1697 .enable_mask = BIT(0),
1698 .hw.init = &(struct clk_init_data){
1699 .name = "camss_phy1_csi1phytimer_clk",
1700 .parent_hws = (const struct clk_hw *[]){ &csi1phytimer_clk_src.clkr.hw },
1701 .num_parents = 1,
1702 .ops = &clk_branch2_ops,
1703 },
1704 },
1705 };
1706
1707 static struct clk_branch camss_phy2_csi2phytimer_clk = {
1708 .halt_reg = 0x3084,
1709 .clkr = {
1710 .enable_reg = 0x3084,
1711 .enable_mask = BIT(0),
1712 .hw.init = &(struct clk_init_data){
1713 .name = "camss_phy2_csi2phytimer_clk",
1714 .parent_hws = (const struct clk_hw *[]){ &csi2phytimer_clk_src.clkr.hw },
1715 .num_parents = 1,
1716 .ops = &clk_branch2_ops,
1717 },
1718 },
1719 };
1720
1721 static struct clk_branch camss_top_ahb_clk = {
1722 .halt_reg = 0x3484,
1723 .clkr = {
1724 .enable_reg = 0x3484,
1725 .enable_mask = BIT(0),
1726 .hw.init = &(struct clk_init_data){
1727 .name = "camss_top_ahb_clk",
1728 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1729 .num_parents = 1,
1730 .flags = CLK_SET_RATE_PARENT,
1731 .ops = &clk_branch2_ops,
1732 },
1733 },
1734 };
1735
1736 static struct clk_branch camss_vfe_vfe0_clk = {
1737 .halt_reg = 0x36a8,
1738 .clkr = {
1739 .enable_reg = 0x36a8,
1740 .enable_mask = BIT(0),
1741 .hw.init = &(struct clk_init_data){
1742 .name = "camss_vfe_vfe0_clk",
1743 .parent_hws = (const struct clk_hw *[]){ &vfe0_clk_src.clkr.hw },
1744 .num_parents = 1,
1745 .ops = &clk_branch2_ops,
1746 },
1747 },
1748 };
1749
1750 static struct clk_branch camss_vfe_vfe1_clk = {
1751 .halt_reg = 0x36ac,
1752 .clkr = {
1753 .enable_reg = 0x36ac,
1754 .enable_mask = BIT(0),
1755 .hw.init = &(struct clk_init_data){
1756 .name = "camss_vfe_vfe1_clk",
1757 .parent_hws = (const struct clk_hw *[]){ &vfe1_clk_src.clkr.hw },
1758 .num_parents = 1,
1759 .ops = &clk_branch2_ops,
1760 },
1761 },
1762 };
1763
1764 static struct clk_branch camss_vfe_vfe_ahb_clk = {
1765 .halt_reg = 0x36b8,
1766 .clkr = {
1767 .enable_reg = 0x36b8,
1768 .enable_mask = BIT(0),
1769 .hw.init = &(struct clk_init_data){
1770 .name = "camss_vfe_vfe_ahb_clk",
1771 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1772 .num_parents = 1,
1773 .flags = CLK_SET_RATE_PARENT,
1774 .ops = &clk_branch2_ops,
1775 },
1776 },
1777 };
1778
1779 static struct clk_branch camss_vfe_vfe_axi_clk = {
1780 .halt_reg = 0x36bc,
1781 .clkr = {
1782 .enable_reg = 0x36bc,
1783 .enable_mask = BIT(0),
1784 .hw.init = &(struct clk_init_data){
1785 .name = "camss_vfe_vfe_axi_clk",
1786 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
1787 .num_parents = 1,
1788 .ops = &clk_branch2_ops,
1789 },
1790 },
1791 };
1792
1793 static struct clk_branch fd_ahb_clk = {
1794 .halt_reg = 0x3b74,
1795 .clkr = {
1796 .enable_reg = 0x3b74,
1797 .enable_mask = BIT(0),
1798 .hw.init = &(struct clk_init_data){
1799 .name = "fd_ahb_clk",
1800 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1801 .num_parents = 1,
1802 .ops = &clk_branch2_ops,
1803 },
1804 },
1805 };
1806
1807 static struct clk_branch fd_axi_clk = {
1808 .halt_reg = 0x3b70,
1809 .clkr = {
1810 .enable_reg = 0x3b70,
1811 .enable_mask = BIT(0),
1812 .hw.init = &(struct clk_init_data){
1813 .name = "fd_axi_clk",
1814 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
1815 .num_parents = 1,
1816 .ops = &clk_branch2_ops,
1817 },
1818 },
1819 };
1820
1821 static struct clk_branch fd_core_clk = {
1822 .halt_reg = 0x3b68,
1823 .clkr = {
1824 .enable_reg = 0x3b68,
1825 .enable_mask = BIT(0),
1826 .hw.init = &(struct clk_init_data){
1827 .name = "fd_core_clk",
1828 .parent_hws = (const struct clk_hw *[]){ &fd_core_clk_src.clkr.hw },
1829 .num_parents = 1,
1830 .ops = &clk_branch2_ops,
1831 },
1832 },
1833 };
1834
1835 static struct clk_branch fd_core_uar_clk = {
1836 .halt_reg = 0x3b6c,
1837 .clkr = {
1838 .enable_reg = 0x3b6c,
1839 .enable_mask = BIT(0),
1840 .hw.init = &(struct clk_init_data){
1841 .name = "fd_core_uar_clk",
1842 .parent_hws = (const struct clk_hw *[]){ &fd_core_clk_src.clkr.hw },
1843 .num_parents = 1,
1844 .ops = &clk_branch2_ops,
1845 },
1846 },
1847 };
1848
1849 static struct clk_branch mdss_ahb_clk = {
1850 .halt_reg = 0x2308,
1851 .halt_check = BRANCH_HALT,
1852 .clkr = {
1853 .enable_reg = 0x2308,
1854 .enable_mask = BIT(0),
1855 .hw.init = &(struct clk_init_data){
1856 .name = "mdss_ahb_clk",
1857 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1858 .num_parents = 1,
1859 .flags = CLK_SET_RATE_PARENT,
1860 .ops = &clk_branch2_ops,
1861 },
1862 },
1863 };
1864
1865 static struct clk_branch mdss_axi_clk = {
1866 .halt_reg = 0x2310,
1867 .clkr = {
1868 .enable_reg = 0x2310,
1869 .enable_mask = BIT(0),
1870 .hw.init = &(struct clk_init_data){
1871 .name = "mdss_axi_clk",
1872 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
1873 .num_parents = 1,
1874 .flags = CLK_SET_RATE_PARENT,
1875 .ops = &clk_branch2_ops,
1876 },
1877 },
1878 };
1879
1880 static struct clk_branch mdss_byte0_clk = {
1881 .halt_reg = 0x233c,
1882 .clkr = {
1883 .enable_reg = 0x233c,
1884 .enable_mask = BIT(0),
1885 .hw.init = &(struct clk_init_data){
1886 .name = "mdss_byte0_clk",
1887 .parent_hws = (const struct clk_hw *[]){ &byte0_clk_src.clkr.hw },
1888 .num_parents = 1,
1889 .flags = CLK_SET_RATE_PARENT,
1890 .ops = &clk_branch2_ops,
1891 },
1892 },
1893 };
1894
1895 static struct clk_branch mdss_byte1_clk = {
1896 .halt_reg = 0x2340,
1897 .clkr = {
1898 .enable_reg = 0x2340,
1899 .enable_mask = BIT(0),
1900 .hw.init = &(struct clk_init_data){
1901 .name = "mdss_byte1_clk",
1902 .parent_hws = (const struct clk_hw *[]){ &byte1_clk_src.clkr.hw },
1903 .num_parents = 1,
1904 .flags = CLK_SET_RATE_PARENT,
1905 .ops = &clk_branch2_ops,
1906 },
1907 },
1908 };
1909
1910 static struct clk_branch mdss_esc0_clk = {
1911 .halt_reg = 0x2344,
1912 .clkr = {
1913 .enable_reg = 0x2344,
1914 .enable_mask = BIT(0),
1915 .hw.init = &(struct clk_init_data){
1916 .name = "mdss_esc0_clk",
1917 .parent_hws = (const struct clk_hw *[]){ &esc0_clk_src.clkr.hw },
1918 .num_parents = 1,
1919 .flags = CLK_SET_RATE_PARENT,
1920 .ops = &clk_branch2_ops,
1921 },
1922 },
1923 };
1924
1925 static struct clk_branch mdss_esc1_clk = {
1926 .halt_reg = 0x2348,
1927 .clkr = {
1928 .enable_reg = 0x2348,
1929 .enable_mask = BIT(0),
1930 .hw.init = &(struct clk_init_data){
1931 .name = "mdss_esc1_clk",
1932 .parent_hws = (const struct clk_hw *[]){ &esc1_clk_src.clkr.hw },
1933 .num_parents = 1,
1934 .flags = CLK_SET_RATE_PARENT,
1935 .ops = &clk_branch2_ops,
1936 },
1937 },
1938 };
1939
1940 static struct clk_branch mdss_extpclk_clk = {
1941 .halt_reg = 0x2324,
1942 .clkr = {
1943 .enable_reg = 0x2324,
1944 .enable_mask = BIT(0),
1945 .hw.init = &(struct clk_init_data){
1946 .name = "mdss_extpclk_clk",
1947 .parent_hws = (const struct clk_hw *[]){ &extpclk_clk_src.clkr.hw },
1948 .num_parents = 1,
1949 .flags = CLK_SET_RATE_PARENT,
1950 .ops = &clk_branch2_ops,
1951 },
1952 },
1953 };
1954
1955 static struct clk_branch mdss_hdmi_ahb_clk = {
1956 .halt_reg = 0x230c,
1957 .clkr = {
1958 .enable_reg = 0x230c,
1959 .enable_mask = BIT(0),
1960 .hw.init = &(struct clk_init_data){
1961 .name = "mdss_hdmi_ahb_clk",
1962 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1963 .num_parents = 1,
1964 .flags = CLK_SET_RATE_PARENT,
1965 .ops = &clk_branch2_ops,
1966 },
1967 },
1968 };
1969
1970 static struct clk_branch mdss_hdmi_clk = {
1971 .halt_reg = 0x2338,
1972 .clkr = {
1973 .enable_reg = 0x2338,
1974 .enable_mask = BIT(0),
1975 .hw.init = &(struct clk_init_data){
1976 .name = "mdss_hdmi_clk",
1977 .parent_hws = (const struct clk_hw *[]){ &hdmi_clk_src.clkr.hw },
1978 .num_parents = 1,
1979 .flags = CLK_SET_RATE_PARENT,
1980 .ops = &clk_branch2_ops,
1981 },
1982 },
1983 };
1984
1985 static struct clk_branch mdss_mdp_clk = {
1986 .halt_reg = 0x231c,
1987 .clkr = {
1988 .enable_reg = 0x231c,
1989 .enable_mask = BIT(0),
1990 .hw.init = &(struct clk_init_data){
1991 .name = "mdss_mdp_clk",
1992 .parent_hws = (const struct clk_hw *[]){ &mdp_clk_src.clkr.hw },
1993 .num_parents = 1,
1994 .flags = CLK_SET_RATE_PARENT,
1995 .ops = &clk_branch2_ops,
1996 },
1997 },
1998 };
1999
2000 static struct clk_branch mdss_pclk0_clk = {
2001 .halt_reg = 0x2314,
2002 .clkr = {
2003 .enable_reg = 0x2314,
2004 .enable_mask = BIT(0),
2005 .hw.init = &(struct clk_init_data){
2006 .name = "mdss_pclk0_clk",
2007 .parent_hws = (const struct clk_hw *[]){ &pclk0_clk_src.clkr.hw },
2008 .num_parents = 1,
2009 .flags = CLK_SET_RATE_PARENT,
2010 .ops = &clk_branch2_ops,
2011 },
2012 },
2013 };
2014
2015 static struct clk_branch mdss_pclk1_clk = {
2016 .halt_reg = 0x2318,
2017 .clkr = {
2018 .enable_reg = 0x2318,
2019 .enable_mask = BIT(0),
2020 .hw.init = &(struct clk_init_data){
2021 .name = "mdss_pclk1_clk",
2022 .parent_hws = (const struct clk_hw *[]){ &pclk1_clk_src.clkr.hw },
2023 .num_parents = 1,
2024 .flags = CLK_SET_RATE_PARENT,
2025 .ops = &clk_branch2_ops,
2026 },
2027 },
2028 };
2029
2030 static struct clk_branch mdss_vsync_clk = {
2031 .halt_reg = 0x2328,
2032 .clkr = {
2033 .enable_reg = 0x2328,
2034 .enable_mask = BIT(0),
2035 .hw.init = &(struct clk_init_data){
2036 .name = "mdss_vsync_clk",
2037 .parent_hws = (const struct clk_hw *[]){ &vsync_clk_src.clkr.hw },
2038 .num_parents = 1,
2039 .flags = CLK_SET_RATE_PARENT,
2040 .ops = &clk_branch2_ops,
2041 },
2042 },
2043 };
2044
2045 static struct clk_branch mmss_misc_ahb_clk = {
2046 .halt_reg = 0x502c,
2047 .clkr = {
2048 .enable_reg = 0x502c,
2049 .enable_mask = BIT(0),
2050 .hw.init = &(struct clk_init_data){
2051 .name = "mmss_misc_ahb_clk",
2052 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2053 .num_parents = 1,
2054 .flags = CLK_SET_RATE_PARENT,
2055 .ops = &clk_branch2_ops,
2056 },
2057 },
2058 };
2059
2060 static struct clk_branch mmss_mmssnoc_axi_clk = {
2061 .halt_reg = 0x506c,
2062 .clkr = {
2063 .enable_reg = 0x506c,
2064 .enable_mask = BIT(0),
2065 .hw.init = &(struct clk_init_data){
2066 .name = "mmss_mmssnoc_axi_clk",
2067 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
2068 .num_parents = 1,
2069 /* Gating this clock will wreck havoc among MMSS! */
2070 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
2071 .ops = &clk_branch2_ops,
2072 },
2073 },
2074 };
2075
2076 static struct clk_branch mmss_s0_axi_clk = {
2077 .halt_reg = 0x5064,
2078 .clkr = {
2079 .enable_reg = 0x5064,
2080 .enable_mask = BIT(0),
2081 .hw.init = &(struct clk_init_data){
2082 .name = "mmss_s0_axi_clk",
2083 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw, },
2084 .num_parents = 1,
2085 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2086 .ops = &clk_branch2_ops,
2087 },
2088 },
2089 };
2090
2091 static struct clk_branch ocmemcx_ocmemnoc_clk = {
2092 .halt_reg = 0x4058,
2093 .clkr = {
2094 .enable_reg = 0x4058,
2095 .enable_mask = BIT(0),
2096 .hw.init = &(struct clk_init_data){
2097 .name = "ocmemcx_ocmemnoc_clk",
2098 .parent_hws = (const struct clk_hw *[]){ &ocmemnoc_clk_src.clkr.hw },
2099 .num_parents = 1,
2100 .flags = CLK_SET_RATE_PARENT,
2101 .ops = &clk_branch2_ops,
2102 },
2103 },
2104 };
2105
2106 static struct clk_branch oxili_gfx3d_clk = {
2107 .halt_reg = 0x4028,
2108 .clkr = {
2109 .enable_reg = 0x4028,
2110 .enable_mask = BIT(0),
2111 .hw.init = &(struct clk_init_data){
2112 .name = "oxili_gfx3d_clk",
2113 .parent_data = &(const struct clk_parent_data){
2114 .fw_name = "oxili_gfx3d_clk_src",
2115 .name = "oxili_gfx3d_clk_src"
2116 },
2117 .num_parents = 1,
2118 .flags = CLK_SET_RATE_PARENT,
2119 .ops = &clk_branch2_ops,
2120 },
2121 },
2122 };
2123
2124 static struct clk_branch oxili_rbbmtimer_clk = {
2125 .halt_reg = 0x40b0,
2126 .clkr = {
2127 .enable_reg = 0x40b0,
2128 .enable_mask = BIT(0),
2129 .hw.init = &(struct clk_init_data){
2130 .name = "oxili_rbbmtimer_clk",
2131 .parent_hws = (const struct clk_hw *[]){ &rbbmtimer_clk_src.clkr.hw },
2132 .num_parents = 1,
2133 .flags = CLK_SET_RATE_PARENT,
2134 .ops = &clk_branch2_ops,
2135 },
2136 },
2137 };
2138
2139 static struct clk_branch oxilicx_ahb_clk = {
2140 .halt_reg = 0x403c,
2141 .clkr = {
2142 .enable_reg = 0x403c,
2143 .enable_mask = BIT(0),
2144 .hw.init = &(struct clk_init_data){
2145 .name = "oxilicx_ahb_clk",
2146 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2147 .num_parents = 1,
2148 .flags = CLK_SET_RATE_PARENT,
2149 .ops = &clk_branch2_ops,
2150 },
2151 },
2152 };
2153
2154 static struct clk_branch venus0_ahb_clk = {
2155 .halt_reg = 0x1030,
2156 .clkr = {
2157 .enable_reg = 0x1030,
2158 .enable_mask = BIT(0),
2159 .hw.init = &(struct clk_init_data){
2160 .name = "venus0_ahb_clk",
2161 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2162 .num_parents = 1,
2163 .flags = CLK_SET_RATE_PARENT,
2164 .ops = &clk_branch2_ops,
2165 },
2166 },
2167 };
2168
2169 static struct clk_branch venus0_axi_clk = {
2170 .halt_reg = 0x1034,
2171 .clkr = {
2172 .enable_reg = 0x1034,
2173 .enable_mask = BIT(0),
2174 .hw.init = &(struct clk_init_data){
2175 .name = "venus0_axi_clk",
2176 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
2177 .num_parents = 1,
2178 .ops = &clk_branch2_ops,
2179 },
2180 },
2181 };
2182
2183 static struct clk_branch venus0_ocmemnoc_clk = {
2184 .halt_reg = 0x1038,
2185 .clkr = {
2186 .enable_reg = 0x1038,
2187 .enable_mask = BIT(0),
2188 .hw.init = &(struct clk_init_data){
2189 .name = "venus0_ocmemnoc_clk",
2190 .parent_hws = (const struct clk_hw *[]){ &ocmemnoc_clk_src.clkr.hw },
2191 .num_parents = 1,
2192 .flags = CLK_SET_RATE_PARENT,
2193 .ops = &clk_branch2_ops,
2194 },
2195 },
2196 };
2197
2198 static struct clk_branch venus0_vcodec0_clk = {
2199 .halt_reg = 0x1028,
2200 .clkr = {
2201 .enable_reg = 0x1028,
2202 .enable_mask = BIT(0),
2203 .hw.init = &(struct clk_init_data){
2204 .name = "venus0_vcodec0_clk",
2205 .parent_hws = (const struct clk_hw *[]){ &vcodec0_clk_src.clkr.hw },
2206 .num_parents = 1,
2207 .flags = CLK_SET_RATE_PARENT,
2208 .ops = &clk_branch2_ops,
2209 },
2210 },
2211 };
2212
2213 static struct clk_branch venus0_core0_vcodec_clk = {
2214 .halt_reg = 0x1048,
2215 .clkr = {
2216 .enable_reg = 0x1048,
2217 .enable_mask = BIT(0),
2218 .hw.init = &(struct clk_init_data){
2219 .name = "venus0_core0_vcodec_clk",
2220 .parent_hws = (const struct clk_hw *[]){ &vcodec0_clk_src.clkr.hw },
2221 .num_parents = 1,
2222 .flags = CLK_SET_RATE_PARENT,
2223 .ops = &clk_branch2_ops,
2224 },
2225 },
2226 };
2227
2228 static struct clk_branch venus0_core1_vcodec_clk = {
2229 .halt_reg = 0x104c,
2230 .clkr = {
2231 .enable_reg = 0x104c,
2232 .enable_mask = BIT(0),
2233 .hw.init = &(struct clk_init_data){
2234 .name = "venus0_core1_vcodec_clk",
2235 .parent_hws = (const struct clk_hw *[]){ &vcodec0_clk_src.clkr.hw },
2236 .num_parents = 1,
2237 .flags = CLK_SET_RATE_PARENT,
2238 .ops = &clk_branch2_ops,
2239 },
2240 },
2241 };
2242
2243 static struct clk_branch venus0_core2_vcodec_clk = {
2244 .halt_reg = 0x1054,
2245 .clkr = {
2246 .enable_reg = 0x1054,
2247 .enable_mask = BIT(0),
2248 .hw.init = &(struct clk_init_data){
2249 .name = "venus0_core2_vcodec_clk",
2250 .parent_hws = (const struct clk_hw *[]){ &vcodec0_clk_src.clkr.hw },
2251 .num_parents = 1,
2252 .flags = CLK_SET_RATE_PARENT,
2253 .ops = &clk_branch2_ops,
2254 },
2255 },
2256 };
2257
2258 static struct gdsc venus_gdsc = {
2259 .gdscr = 0x1024,
2260 .cxcs = (unsigned int []){ 0x1038, 0x1034, 0x1048 },
2261 .cxc_count = 3,
2262 .pd = {
2263 .name = "venus_gdsc",
2264 },
2265 .pwrsts = PWRSTS_OFF_ON,
2266 };
2267
2268 static struct gdsc venus_core0_gdsc = {
2269 .gdscr = 0x1040,
2270 .cxcs = (unsigned int []){ 0x1048 },
2271 .cxc_count = 1,
2272 .pd = {
2273 .name = "venus_core0_gdsc",
2274 },
2275 .pwrsts = PWRSTS_OFF_ON,
2276 .flags = HW_CTRL,
2277 };
2278
2279 static struct gdsc venus_core1_gdsc = {
2280 .gdscr = 0x1044,
2281 .cxcs = (unsigned int []){ 0x104c },
2282 .cxc_count = 1,
2283 .pd = {
2284 .name = "venus_core1_gdsc",
2285 },
2286 .pwrsts = PWRSTS_OFF_ON,
2287 .flags = HW_CTRL,
2288 };
2289
2290 static struct gdsc venus_core2_gdsc = {
2291 .gdscr = 0x1050,
2292 .cxcs = (unsigned int []){ 0x1054 },
2293 .cxc_count = 1,
2294 .pd = {
2295 .name = "venus_core2_gdsc",
2296 },
2297 .pwrsts = PWRSTS_OFF_ON,
2298 .flags = HW_CTRL,
2299 };
2300
2301 static struct gdsc mdss_gdsc = {
2302 .gdscr = 0x2304,
2303 .cxcs = (unsigned int []){ 0x2310, 0x231c },
2304 .cxc_count = 2,
2305 .pd = {
2306 .name = "mdss_gdsc",
2307 },
2308 .pwrsts = PWRSTS_OFF_ON,
2309 };
2310
2311 static struct gdsc camss_top_gdsc = {
2312 .gdscr = 0x34a0,
2313 .cxcs = (unsigned int []){ 0x3704, 0x3714, 0x3494 },
2314 .cxc_count = 3,
2315 .pd = {
2316 .name = "camss_top_gdsc",
2317 },
2318 .pwrsts = PWRSTS_OFF_ON,
2319 };
2320
2321 static struct gdsc jpeg_gdsc = {
2322 .gdscr = 0x35a4,
2323 .cxcs = (unsigned int []){ 0x35a8 },
2324 .cxc_count = 1,
2325 .pd = {
2326 .name = "jpeg_gdsc",
2327 },
2328 .parent = &camss_top_gdsc.pd,
2329 .pwrsts = PWRSTS_OFF_ON,
2330 };
2331
2332 static struct gdsc vfe_gdsc = {
2333 .gdscr = 0x36a4,
2334 .cxcs = (unsigned int []){ 0x36bc },
2335 .cxc_count = 1,
2336 .pd = {
2337 .name = "vfe_gdsc",
2338 },
2339 .parent = &camss_top_gdsc.pd,
2340 .pwrsts = PWRSTS_OFF_ON,
2341 };
2342
2343 static struct gdsc cpp_gdsc = {
2344 .gdscr = 0x36d4,
2345 .cxcs = (unsigned int []){ 0x36c4, 0x36b0 },
2346 .cxc_count = 2,
2347 .pd = {
2348 .name = "cpp_gdsc",
2349 },
2350 .parent = &camss_top_gdsc.pd,
2351 .pwrsts = PWRSTS_OFF_ON,
2352 };
2353
2354 static struct gdsc fd_gdsc = {
2355 .gdscr = 0x3b64,
2356 .cxcs = (unsigned int []){ 0x3b70, 0x3b68 },
2357 .pd = {
2358 .name = "fd_gdsc",
2359 },
2360 .pwrsts = PWRSTS_OFF_ON,
2361 };
2362
2363 static struct gdsc oxili_cx_gdsc = {
2364 .gdscr = 0x4034,
2365 .pd = {
2366 .name = "oxili_cx_gdsc",
2367 },
2368 .pwrsts = PWRSTS_OFF_ON,
2369 .flags = VOTABLE,
2370 };
2371
2372 static struct gdsc oxili_gx_gdsc = {
2373 .gdscr = 0x4024,
2374 .cxcs = (unsigned int []){ 0x4028 },
2375 .cxc_count = 1,
2376 .pd = {
2377 .name = "oxili_gx_gdsc",
2378 },
2379 .pwrsts = PWRSTS_OFF_ON,
2380 .parent = &oxili_cx_gdsc.pd,
2381 .flags = CLAMP_IO,
2382 .supply = "VDD_GFX",
2383 };
2384
2385 static struct clk_regmap *mmcc_msm8994_clocks[] = {
2386 [MMPLL0_EARLY] = &mmpll0_early.clkr,
2387 [MMPLL0_PLL] = &mmpll0.clkr,
2388 [MMPLL1_EARLY] = &mmpll1_early.clkr,
2389 [MMPLL1_PLL] = &mmpll1.clkr,
2390 [MMPLL3_EARLY] = &mmpll3_early.clkr,
2391 [MMPLL3_PLL] = &mmpll3.clkr,
2392 [MMPLL4_EARLY] = &mmpll4_early.clkr,
2393 [MMPLL4_PLL] = &mmpll4.clkr,
2394 [MMPLL5_EARLY] = &mmpll5_early.clkr,
2395 [MMPLL5_PLL] = &mmpll5.clkr,
2396 [AHB_CLK_SRC] = &ahb_clk_src.clkr,
2397 [AXI_CLK_SRC] = &axi_clk_src.clkr,
2398 [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
2399 [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
2400 [CSI2_CLK_SRC] = &csi2_clk_src.clkr,
2401 [CSI3_CLK_SRC] = &csi3_clk_src.clkr,
2402 [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
2403 [VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
2404 [CPP_CLK_SRC] = &cpp_clk_src.clkr,
2405 [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
2406 [JPEG1_CLK_SRC] = &jpeg1_clk_src.clkr,
2407 [JPEG2_CLK_SRC] = &jpeg2_clk_src.clkr,
2408 [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr,
2409 [FD_CORE_CLK_SRC] = &fd_core_clk_src.clkr,
2410 [MDP_CLK_SRC] = &mdp_clk_src.clkr,
2411 [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
2412 [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
2413 [OCMEMNOC_CLK_SRC] = &ocmemnoc_clk_src.clkr,
2414 [CCI_CLK_SRC] = &cci_clk_src.clkr,
2415 [MMSS_GP0_CLK_SRC] = &mmss_gp0_clk_src.clkr,
2416 [MMSS_GP1_CLK_SRC] = &mmss_gp1_clk_src.clkr,
2417 [JPEG_DMA_CLK_SRC] = &jpeg_dma_clk_src.clkr,
2418 [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
2419 [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
2420 [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
2421 [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr,
2422 [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
2423 [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
2424 [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
2425 [BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
2426 [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
2427 [ESC1_CLK_SRC] = &esc1_clk_src.clkr,
2428 [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
2429 [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr,
2430 [EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr,
2431 [HDMI_CLK_SRC] = &hdmi_clk_src.clkr,
2432 [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
2433 [RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr,
2434 [CAMSS_AHB_CLK] = &camss_ahb_clk.clkr,
2435 [CAMSS_CCI_CCI_AHB_CLK] = &camss_cci_cci_ahb_clk.clkr,
2436 [CAMSS_CCI_CCI_CLK] = &camss_cci_cci_clk.clkr,
2437 [CAMSS_VFE_CPP_AHB_CLK] = &camss_vfe_cpp_ahb_clk.clkr,
2438 [CAMSS_VFE_CPP_AXI_CLK] = &camss_vfe_cpp_axi_clk.clkr,
2439 [CAMSS_VFE_CPP_CLK] = &camss_vfe_cpp_clk.clkr,
2440 [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
2441 [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
2442 [CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr,
2443 [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
2444 [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
2445 [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
2446 [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
2447 [CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr,
2448 [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
2449 [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
2450 [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr,
2451 [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr,
2452 [CAMSS_CSI2PHY_CLK] = &camss_csi2phy_clk.clkr,
2453 [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr,
2454 [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr,
2455 [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr,
2456 [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr,
2457 [CAMSS_CSI3PHY_CLK] = &camss_csi3phy_clk.clkr,
2458 [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr,
2459 [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr,
2460 [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
2461 [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr,
2462 [CAMSS_GP0_CLK] = &camss_gp0_clk.clkr,
2463 [CAMSS_GP1_CLK] = &camss_gp1_clk.clkr,
2464 [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
2465 [CAMSS_JPEG_DMA_CLK] = &camss_jpeg_dma_clk.clkr,
2466 [CAMSS_JPEG_JPEG0_CLK] = &camss_jpeg_jpeg0_clk.clkr,
2467 [CAMSS_JPEG_JPEG1_CLK] = &camss_jpeg_jpeg1_clk.clkr,
2468 [CAMSS_JPEG_JPEG2_CLK] = &camss_jpeg_jpeg2_clk.clkr,
2469 [CAMSS_JPEG_JPEG_AHB_CLK] = &camss_jpeg_jpeg_ahb_clk.clkr,
2470 [CAMSS_JPEG_JPEG_AXI_CLK] = &camss_jpeg_jpeg_axi_clk.clkr,
2471 [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
2472 [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
2473 [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr,
2474 [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr,
2475 [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
2476 [CAMSS_PHY0_CSI0PHYTIMER_CLK] = &camss_phy0_csi0phytimer_clk.clkr,
2477 [CAMSS_PHY1_CSI1PHYTIMER_CLK] = &camss_phy1_csi1phytimer_clk.clkr,
2478 [CAMSS_PHY2_CSI2PHYTIMER_CLK] = &camss_phy2_csi2phytimer_clk.clkr,
2479 [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
2480 [CAMSS_VFE_VFE0_CLK] = &camss_vfe_vfe0_clk.clkr,
2481 [CAMSS_VFE_VFE1_CLK] = &camss_vfe_vfe1_clk.clkr,
2482 [CAMSS_VFE_VFE_AHB_CLK] = &camss_vfe_vfe_ahb_clk.clkr,
2483 [CAMSS_VFE_VFE_AXI_CLK] = &camss_vfe_vfe_axi_clk.clkr,
2484 [FD_AHB_CLK] = &fd_ahb_clk.clkr,
2485 [FD_AXI_CLK] = &fd_axi_clk.clkr,
2486 [FD_CORE_CLK] = &fd_core_clk.clkr,
2487 [FD_CORE_UAR_CLK] = &fd_core_uar_clk.clkr,
2488 [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
2489 [MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
2490 [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
2491 [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr,
2492 [MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr,
2493 [MDSS_HDMI_AHB_CLK] = &mdss_hdmi_ahb_clk.clkr,
2494 [MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr,
2495 [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
2496 [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
2497 [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr,
2498 [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
2499 [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr,
2500 [MMSS_MMSSNOC_AXI_CLK] = &mmss_mmssnoc_axi_clk.clkr,
2501 [MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr,
2502 [OCMEMCX_OCMEMNOC_CLK] = &ocmemcx_ocmemnoc_clk.clkr,
2503 [OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr,
2504 [OXILI_RBBMTIMER_CLK] = &oxili_rbbmtimer_clk.clkr,
2505 [OXILICX_AHB_CLK] = &oxilicx_ahb_clk.clkr,
2506 [VENUS0_AHB_CLK] = &venus0_ahb_clk.clkr,
2507 [VENUS0_AXI_CLK] = &venus0_axi_clk.clkr,
2508 [VENUS0_OCMEMNOC_CLK] = &venus0_ocmemnoc_clk.clkr,
2509 [VENUS0_VCODEC0_CLK] = &venus0_vcodec0_clk.clkr,
2510 [VENUS0_CORE0_VCODEC_CLK] = &venus0_core0_vcodec_clk.clkr,
2511 [VENUS0_CORE1_VCODEC_CLK] = &venus0_core1_vcodec_clk.clkr,
2512 [VENUS0_CORE2_VCODEC_CLK] = &venus0_core2_vcodec_clk.clkr,
2513 };
2514
2515 static struct gdsc *mmcc_msm8994_gdscs[] = {
2516 [VENUS_GDSC] = &venus_gdsc,
2517 [VENUS_CORE0_GDSC] = &venus_core0_gdsc,
2518 [VENUS_CORE1_GDSC] = &venus_core1_gdsc,
2519 [VENUS_CORE2_GDSC] = &venus_core2_gdsc,
2520 [CAMSS_TOP_GDSC] = &camss_top_gdsc,
2521 [MDSS_GDSC] = &mdss_gdsc,
2522 [JPEG_GDSC] = &jpeg_gdsc,
2523 [VFE_GDSC] = &vfe_gdsc,
2524 [CPP_GDSC] = &cpp_gdsc,
2525 [OXILI_GX_GDSC] = &oxili_gx_gdsc,
2526 [OXILI_CX_GDSC] = &oxili_cx_gdsc,
2527 [FD_GDSC] = &fd_gdsc,
2528 };
2529
2530 static const struct qcom_reset_map mmcc_msm8994_resets[] = {
2531 [CAMSS_MICRO_BCR] = { 0x3490 },
2532 };
2533
2534 static const struct regmap_config mmcc_msm8994_regmap_config = {
2535 .reg_bits = 32,
2536 .reg_stride = 4,
2537 .val_bits = 32,
2538 .max_register = 0x5200,
2539 .fast_io = true,
2540 };
2541
2542 static const struct qcom_cc_desc mmcc_msm8994_desc = {
2543 .config = &mmcc_msm8994_regmap_config,
2544 .clks = mmcc_msm8994_clocks,
2545 .num_clks = ARRAY_SIZE(mmcc_msm8994_clocks),
2546 .resets = mmcc_msm8994_resets,
2547 .num_resets = ARRAY_SIZE(mmcc_msm8994_resets),
2548 .gdscs = mmcc_msm8994_gdscs,
2549 .num_gdscs = ARRAY_SIZE(mmcc_msm8994_gdscs),
2550 };
2551
2552 static const struct of_device_id mmcc_msm8994_match_table[] = {
2553 { .compatible = "qcom,mmcc-msm8992" },
2554 { .compatible = "qcom,mmcc-msm8994" }, /* V2 and V2.1 */
2555 { }
2556 };
2557 MODULE_DEVICE_TABLE(of, mmcc_msm8994_match_table);
2558
mmcc_msm8994_probe(struct platform_device * pdev)2559 static int mmcc_msm8994_probe(struct platform_device *pdev)
2560 {
2561 struct regmap *regmap;
2562
2563 if (of_device_is_compatible(pdev->dev.of_node, "qcom,mmcc-msm8992")) {
2564 /* MSM8992 features less clocks and some have different freq tables */
2565 mmcc_msm8994_desc.clks[CAMSS_JPEG_JPEG1_CLK] = NULL;
2566 mmcc_msm8994_desc.clks[CAMSS_JPEG_JPEG2_CLK] = NULL;
2567 mmcc_msm8994_desc.clks[FD_CORE_CLK_SRC] = NULL;
2568 mmcc_msm8994_desc.clks[FD_CORE_CLK] = NULL;
2569 mmcc_msm8994_desc.clks[FD_CORE_UAR_CLK] = NULL;
2570 mmcc_msm8994_desc.clks[FD_AXI_CLK] = NULL;
2571 mmcc_msm8994_desc.clks[FD_AHB_CLK] = NULL;
2572 mmcc_msm8994_desc.clks[JPEG1_CLK_SRC] = NULL;
2573 mmcc_msm8994_desc.clks[JPEG2_CLK_SRC] = NULL;
2574 mmcc_msm8994_desc.clks[VENUS0_CORE2_VCODEC_CLK] = NULL;
2575
2576 mmcc_msm8994_desc.gdscs[FD_GDSC] = NULL;
2577 mmcc_msm8994_desc.gdscs[VENUS_CORE2_GDSC] = NULL;
2578
2579 axi_clk_src.freq_tbl = ftbl_axi_clk_src_8992;
2580 cpp_clk_src.freq_tbl = ftbl_cpp_clk_src_8992;
2581 csi0_clk_src.freq_tbl = ftbl_csi0_1_2_3_clk_src_8992;
2582 csi1_clk_src.freq_tbl = ftbl_csi0_1_2_3_clk_src_8992;
2583 csi2_clk_src.freq_tbl = ftbl_csi0_1_2_3_clk_src_8992;
2584 csi3_clk_src.freq_tbl = ftbl_csi0_1_2_3_clk_src_8992;
2585 mclk0_clk_src.freq_tbl = ftbl_mclk0_clk_src_8992;
2586 mclk1_clk_src.freq_tbl = ftbl_mclk1_2_3_clk_src_8992;
2587 mclk2_clk_src.freq_tbl = ftbl_mclk1_2_3_clk_src_8992;
2588 mclk3_clk_src.freq_tbl = ftbl_mclk1_2_3_clk_src_8992;
2589 mdp_clk_src.freq_tbl = ftbl_mdp_clk_src_8992;
2590 ocmemnoc_clk_src.freq_tbl = ftbl_ocmemnoc_clk_src_8992;
2591 vcodec0_clk_src.freq_tbl = ftbl_vcodec0_clk_src_8992;
2592 vfe0_clk_src.freq_tbl = ftbl_vfe0_1_clk_src_8992;
2593 vfe1_clk_src.freq_tbl = ftbl_vfe0_1_clk_src_8992;
2594 }
2595
2596 regmap = qcom_cc_map(pdev, &mmcc_msm8994_desc);
2597 if (IS_ERR(regmap))
2598 return PTR_ERR(regmap);
2599
2600 clk_alpha_pll_configure(&mmpll0_early, regmap, &mmpll_p_config);
2601 clk_alpha_pll_configure(&mmpll1_early, regmap, &mmpll_p_config);
2602 clk_alpha_pll_configure(&mmpll3_early, regmap, &mmpll_p_config);
2603 clk_alpha_pll_configure(&mmpll5_early, regmap, &mmpll_p_config);
2604
2605 return qcom_cc_really_probe(pdev, &mmcc_msm8994_desc, regmap);
2606 }
2607
2608 static struct platform_driver mmcc_msm8994_driver = {
2609 .probe = mmcc_msm8994_probe,
2610 .driver = {
2611 .name = "mmcc-msm8994",
2612 .of_match_table = mmcc_msm8994_match_table,
2613 },
2614 };
2615 module_platform_driver(mmcc_msm8994_driver);
2616
2617 MODULE_DESCRIPTION("QCOM MMCC MSM8994 Driver");
2618 MODULE_LICENSE("GPL v2");
2619 MODULE_ALIAS("platform:mmcc-msm8994");
2620