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/openbmc/linux/drivers/phy/marvell/
H A Dphy-mvebu-a3700-utmi.c9 * Marvell A3700 UTMI PHY driver
21 /* Armada 3700 UTMI PHY registers */
62 * - The UTMI PHY wired to the USB3/USB2 controller (otg)
63 * - The UTMI PHY wired to the USB2 controller (host only)
88 struct mvebu_a3700_utmi *utmi = phy_get_drvdata(phy); in mvebu_a3700_utmi_phy_power_on() local
90 int usb32 = utmi->caps->usb32; in mvebu_a3700_utmi_phy_power_on()
98 reg = readl(utmi->regs + USB2_PHY_PLL_CTRL_REG0); in mvebu_a3700_utmi_phy_power_on()
102 writel(reg, utmi->regs + USB2_PHY_PLL_CTRL_REG0); in mvebu_a3700_utmi_phy_power_on()
105 regmap_update_bits(utmi->usb_misc, USB2_PHY_CTRL(usb32), in mvebu_a3700_utmi_phy_power_on()
111 reg = readl(utmi->regs + USB2_PHY_OTG_CTRL); in mvebu_a3700_utmi_phy_power_on()
[all …]
H A Dphy-mvebu-cp110-utmi.c8 * Marvell CP110 UTMI PHY driver
24 /* CP110 UTMI register macro definetions */
167 struct mvebu_cp110_utmi *utmi = port->priv; in mvebu_cp110_utmi_phy_power_off() local
170 /* Power down UTMI PHY port */ in mvebu_cp110_utmi_phy_power_off()
171 regmap_clear_bits(utmi->syscon, SYSCON_UTMI_CFG_REG(port->id), in mvebu_cp110_utmi_phy_power_off()
175 int test = regmap_test_bits(utmi->syscon, in mvebu_cp110_utmi_phy_power_off()
178 /* skip PLL shutdown if there are active UTMI PHY ports */ in mvebu_cp110_utmi_phy_power_off()
183 /* PLL Power down if all UTMI PHYs are down */ in mvebu_cp110_utmi_phy_power_off()
184 regmap_clear_bits(utmi->syscon, SYSCON_USB_CFG_REG, USB_CFG_PLL_MASK); in mvebu_cp110_utmi_phy_power_off()
192 struct mvebu_cp110_utmi *utmi = port->priv; in mvebu_cp110_utmi_phy_power_on() local
[all …]
H A DKconfig40 tristate "Marvell A3700 UTMI driver"
46 Enable this to support Marvell A3700 UTMI PHY driver.
71 tristate "Marvell CP110 UTMI driver"
76 Enable this to support Marvell CP110 UTMI PHY driver.
H A DMakefile8 obj-$(CONFIG_PHY_MVEBU_A3700_UTMI) += phy-mvebu-a3700-utmi.o
11 obj-$(CONFIG_PHY_MVEBU_CP110_UTMI) += phy-mvebu-cp110-utmi.o
/openbmc/linux/drivers/clk/at91/
H A Dclk-utmi.c43 struct clk_utmi *utmi = to_clk_utmi(hw); in clk_utmi_prepare() local
52 * the utmi clock. in clk_utmi_prepare()
79 if (utmi->regmap_sfr) { in clk_utmi_prepare()
80 regmap_update_bits(utmi->regmap_sfr, AT91_SFR_UTMICKTRIM, in clk_utmi_prepare()
87 regmap_update_bits(utmi->regmap_pmc, AT91_CKGR_UCKR, uckr, uckr); in clk_utmi_prepare()
89 while (!clk_utmi_ready(utmi->regmap_pmc)) in clk_utmi_prepare()
97 struct clk_utmi *utmi = to_clk_utmi(hw); in clk_utmi_is_prepared() local
99 return clk_utmi_ready(utmi->regmap_pmc); in clk_utmi_is_prepared()
104 struct clk_utmi *utmi = to_clk_utmi(hw); in clk_utmi_unprepare() local
106 regmap_update_bits(utmi->regmap_pmc, AT91_CKGR_UCKR, in clk_utmi_unprepare()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dmarvell,armada-cp110-utmi-phy.yaml5 $id: http://devicetree.org/schemas/phy/marvell,armada-cp110-utmi-phy.yaml#
8 title: Marvell Armada CP110/CP115 UTMI PHY
15 Each of two exiting UTMI PHYs could be connected to either USB host or USB device
17 The USB device controller can only be connected to a single UTMI PHY port
19 UTMI PHY0 --------/
23 UTMI PHY1 --------\
28 const: marvell,cp110-utmi-phy
50 Each UTMI PHY port must be represented as a sub-node.
77 cp0_utmi: utmi@580000 {
78 compatible = "marvell,cp110-utmi-phy";
[all …]
H A Dnvidia,tegra20-usb-phy.yaml50 - description: UTMI pads control registers clock
55 - description: UTMI timeout clock
56 - description: UTMI pads control registers clock
72 - const: utmi-pads
78 - const: utmi-pads
90 - description: UTMI pads reset
98 - const: utmi-pads
105 enum: [utmi, ulpi, hsic]
128 nvidia,has-utmi-pad-registers:
130 Indicates whether this controller contains the UTMI pad control
[all …]
H A Dmarvell,armada-3700-utmi-phy.yaml5 $id: http://devicetree.org/schemas/phy/marvell,armada-3700-utmi-phy.yaml#
8 title: Marvell Armada UTMI/UTMI+ PHY
17 a slightly different UTMI PHY.
22 - marvell,a3700-utmi-host-phy
23 - marvell,a3700-utmi-otg-phy
48 compatible = "marvell,a3700-utmi-host-phy";
H A Dphy-stm32-usbphyc.yaml11 The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI
12 switch. It controls PHY configuration and status, and the UTMI+ switch that
24 |_ UTMI switch_______| OTG controller
212 The value is used to select UTMI switch output.
/openbmc/linux/Documentation/devicetree/bindings/mfd/
H A Domap-usb-host.txt43 * "refclk_60m_int" - 60MHz internal reference clock for UTMI clock mux
44 * "refclk_60m_ext_p1" - 60MHz external ref. clock for Port 1's UTMI clock mux.
45 * "refclk_60m_ext_p2" - 60MHz external ref. clock for Port 2's UTMI clock mux
46 * "utmi_p1_gfclk" - Port 1 UTMI clock mux.
47 * "utmi_p2_gfclk" - Port 2 UTMI clock mux.
48 * "usb_host_hs_utmi_p1_clk" - Port 1 UTMI clock gate.
49 * "usb_host_hs_utmi_p2_clk" - Port 2 UTMI clock gate.
50 * "usb_host_hs_utmi_p3_clk" - Port 3 UTMI clock gate.
/openbmc/u-boot/drivers/clk/at91/
H A DKconfig9 PLLA, UTMI PLL. Clocks can also be a source clock of other
16 bool "Support UTMI PLL Clock"
23 This option is used to enable the AT91 UTMI PLL clock
25 output of 480 MHz UTMI PLL, The souce clock of the UTMI
35 the device tree, configure the USBS bit (PLLA or UTMI PLL)
H A Dclk-utmi.c39 * the utmi clock. in utmi_clk_enable()
101 /* UTMI clk rate is fixed. */ in utmi_clk_get_rate()
130 { .compatible = "atmel,at91sam9x5-clk-utmi" },
135 .name = "at91sam9x5-utmi-clk",
/openbmc/linux/Documentation/devicetree/bindings/usb/
H A Dusb.yaml36 UTMI+ PHY with an 8- or 16-bit interface if UTMI+ is selected, UTMI+ low
42 enum: [utmi, utmi_wide, ulpi, serial, hsic]
H A Datmel-usb.txt37 - clocks: Should reference the peripheral and the UTMI clocks
40 "usb_clk" for the UTMI clock
44 "utmi", or "hsic".
50 clocks = <&utmi>, <&uhphs_clk>;
122 clocks = <&utmi>, <&udphs_clk>;
H A Domap-usb.txt13 specifying ULPI and UTMI respectively.
55 - utmi-mode : controls the source of UTMI/PIPE status for VBUS and OTG ID.
77 utmi-mode = <2>;
H A Dhisilicon,histb-xhci.txt13 "utmi": for utmi clock
40 clock-names = "bus", "utmi", "pipe", "suspend";
/openbmc/u-boot/drivers/usb/host/
H A Dutmi-armada100.c16 #include <asm/arch/utmi-armada100.h>
60 * Initialize USB host controller's UTMI Physical interface
70 /* Turn on 26Mhz ref clock for UTMI PLL */ in utmi_init()
77 /* Initialize UTMI transceiver */ in utmi_init()
H A Dehci-tegra.c72 unsigned utmi:1; /* 1 if port has external tranceiver, else 0 */ member
296 if (config->utmi) in usbf_reset_controller()
334 * controller can only talk to a UTMI PHY, so the PHY selection is in init_phy_mux()
343 /* set up the UTMI USB controller with the parameters provided */
553 /* Select UTMI parallel interface */ in init_utmi_usb_controller()
716 config->utmi = phy && 0 == strcmp("utmi", phy); in fdt_decode_usb()
728 …debug("legacy_mode=%d, utmi=%d, ulpi=%d, periph_id=%d, vbus=%d, phy_reset=%d, dr_mode=%d, reg=%p\n… in fdt_decode_usb()
729 config->has_legacy_mode, config->utmi, config->ulpi, in fdt_decode_usb()
758 if (!config->utmi) { in usb_common_init()
759 printf("tegrausb: Device mode only supported with UTMI PHY\n"); in usb_common_init()
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Darmada-cp110-master.dtsi251 cpm_utmi0: utmi@580000 {
252 compatible = "marvell,mvebu-utmi-2.6.0";
253 reg = <0x580000 0x1000>, /* utmi-unit */
255 <0x440440 0x4>; /* utmi-cfg */
256 utmi-port = <UTMI_PHY_TO_USB3_HOST0>;
260 cpm_utmi1: utmi@581000 {
261 compatible = "marvell,mvebu-utmi-2.6.0";
262 reg = <0x581000 0x1000>, /* utmi-unit */
264 <0x440444 0x4>; /* utmi-cfg */
265 utmi-port = <UTMI_PHY_TO_USB3_HOST1>;
H A Dtegra30.dtsi802 phy_type = "utmi";
814 phy_type = "utmi";
818 clock-names = "reg", "pll_u", "utmi-pads";
820 reset-names = "usb", "utmi-pads";
832 nvidia,has-utmi-pad-registers;
840 phy_type = "utmi";
851 phy_type = "utmi";
855 clock-names = "reg", "pll_u", "utmi-pads";
857 reset-names = "usb", "utmi-pads";
876 phy_type = "utmi";
[all …]
/openbmc/u-boot/doc/device-tree-bindings/phy/
H A Dphy-stm32-usbphyc.txt3 The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI
4 switch. It controls PHY configuration and status, and the UTMI+ switch that
16 |_ UTMI switch_______| OTG controller
/openbmc/u-boot/drivers/phy/marvell/
H A Dcomphy_cp110.c1636 debug("stage: UTMI %d - Power down transceiver (power down Phy), Power down PLL, and SuspendDM\n", in comphy_utmi_power_down()
1638 /* Power down UTMI PHY */ in comphy_utmi_power_down()
1643 * If UTMI connected to USB Device, configure mux prior to PHY init in comphy_utmi_power_down()
1647 debug("stage: UTMI %d - Enable Device mode and configure UTMI mux\n", in comphy_utmi_power_down()
1649 /* USB3 Device UTMI enable */ in comphy_utmi_power_down()
1652 /* USB3 Device UTMI MUX */ in comphy_utmi_power_down()
1661 /* Enable Test UTMI select */ in comphy_utmi_power_down()
1666 /* Wait for UTMI power down */ in comphy_utmi_power_down()
1681 debug("stage: Configure UTMI PHY %d registers\n", utmi_index); in comphy_utmi_phy_config()
1742 debug("stage: UTMI %d - Power up transceiver(Power up Phy), and exit SuspendDM\n", in comphy_utmi_power_up()
[all …]
/openbmc/linux/drivers/media/usb/dvb-usb-v2/
H A Drtl28xxu.h197 #define USB_VDRCTRL 0x2F10 /* UTMI vendor signal control */
198 #define USB_VSTAIN 0x2F14 /* UTMI vendor signal status in */
199 #define USB_VLOADM 0x2F18 /* UTMI load vendor signal status in */
200 #define USB_VSTAOUT 0x2F1C /* UTMI vendor signal status out */
201 #define USB_UTMI_TST 0x2F80 /* UTMI test */
202 #define USB_UTMI_STATUS 0x2F84 /* UTMI status */
/openbmc/u-boot/drivers/usb/ulpi/
H A DKconfig9 UTMI (USB PHY) via ULPI interface.
29 ULPI is wrapper on UTMI+ core that is used as
/openbmc/u-boot/doc/
H A DREADME.fsl-hwconfig38 Select USB phy type: 'utmi' OR 'ulpi'
46 usb1:dr_mode=host,phy_type=utmi;usb2:dr_mode=host'

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