| /openbmc/linux/Documentation/devicetree/bindings/soc/aspeed/ |
| H A D | uart-routing.yaml | 17 the built-in UARTS and physical serial I/O ports.
20 This can be used to enable Host <-> BMC communication via UARTs, e.g. to
24 which owns the system configuration policy, to configure how UARTs and
|
| /openbmc/qemu/docs/system/ |
| H A D | target-m68k.rst | 13 - Three Two on-chip UARTs.
21 - Two on-chip UARTs.
|
| /openbmc/qemu/hw/mips/ |
| H A D | loongson3_bootp.c | 71 s->uarts[0].iotype = cpu_to_le32(2); in init_system_loongson()
72 s->uarts[0].int_offset = cpu_to_le32(2); in init_system_loongson()
73 s->uarts[0].uartclk = cpu_to_le32(25000000); /* Random value */ in init_system_loongson()
74 s->uarts[0].uart_base = cpu_to_le64(virt_memmap[VIRT_UART].base); in init_system_loongson()
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| /openbmc/linux/Documentation/translations/zh_CN/arch/loongarch/ |
| H A D | irq-chip-model.rst | 27 CPU串口（UARTs）中断发送到LIOINTC，而其他所有设备的中断则分别发送到所连接的PCH-PIC/
36 | LIOINTC | <-- | UARTs |
63 CPU串口（UARTs）中断发送到LIOINTC，而其他所有设备的中断则分别发送到所连接的PCH-PIC/
72 | EIOINTC | | LIOINTC | <-- | UARTs |
|
| /openbmc/qemu/docs/system/arm/ |
| H A D | stellaris.rst | 11 - Timers, UARTs, ADC and |I2C| interface.
23 - Timers, UARTs, ADC, |I2C| and SSI interfaces.
|
| H A D | collie.rst | 15 * UARTs
|
| H A D | integratorcp.rst | 8 - Two PL011 UARTs
|
| H A D | musicpal.rst | 11 - Up to 2 16550 UARTs
|
| H A D | kzm.rst | 10 - UARTs
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| /openbmc/u-boot/board/toradex/apalis_imx6/ |
| H A D | Kconfig | 46 The UARTs must be used in DCE mode, RTS/CTS are swapped and
50 otherwise the UARTs are configuered in DTE mode.
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| /openbmc/linux/drivers/net/wireless/broadcom/brcm80211/include/ |
| H A D | chipcommon.h | 156 /* UARTs */
233 #define CC_CAP_UARTS_MASK 0x00000003 /* Number of UARTs */
235 #define CC_CAP_UCLKSEL 0x00000018 /* UARTs clock select */
236 /* UARTs are driven by internal divided clock */
238 #define CC_CAP_UARTGPIO 0x00000020 /* UARTs own GPIOs 15:12 */
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| /openbmc/u-boot/arch/arm/mach-rockchip/ |
| H A D | Kconfig | 73 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
93 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
115 I2S, UARTs, SPI, I2C and PWMs.
147 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
|
| /openbmc/qemu/docs/specs/ |
| H A D | pci-serial.rst | 6 wrappers around one or more 16550 UARTs.
34 IO bar, with two or four 16550 UARTs mapped after each other.
|
| /openbmc/linux/Documentation/arch/ia64/ |
| H A D | serial.rst | 23 - If there was no HCDP, we assumed there were UARTs at the
106 - Multiple UARTs selected as EFI console devices. EFI and
155 several UARTs. One of the UARTs is often used as a console; the
|
| /openbmc/linux/Documentation/arch/loongarch/ |
| H A D | irq-chip-model.rst | 23 to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices
33 | LIOINTC | <-- | UARTs |
60 to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices
70 | EIOINTC | | LIOINTC | <-- | UARTs |
|
| /openbmc/u-boot/arch/x86/cpu/baytrail/ |
| H A D | cpu.c | 30 * Configure the BayTrail UART clock for the internal HS UARTs in hsuart_clock_set()
42 * Configure the internal clock of both SIO HS-UARTs, if they are enabled
52 /* Loop over the 2 HS-UARTs */ in arch_cpu_init_dm()
|
| /openbmc/u-boot/drivers/serial/ |
| H A D | serial_pl01x.c | 11 /* Simple U-Boot driver for the PrimeCell PL010/PL011 UARTs */
199 * Integrator AP has two UARTs, we use the first one, at 38400-8-N-1
200 * Integrator CP has two UARTs, use the first one, at 38400-8-N-1
201 * Versatile PB has four UARTs.
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| /openbmc/u-boot/arch/arm/mach-tegra/ |
| H A D | board.c | 27 /* UARTs which we can enable */
169 * Set up the specified uarts
171 * @param uarts_ids Mask containing UARTs to init (UARTx)
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| /openbmc/linux/drivers/tty/serial/8250/ |
| H A D | Kconfig | 181 This enables support for FPGA based UARTs found on many MEN
183 and 16z125 UARTs.
387 erratum for Freescale 16550 UARTs in the 8250 driver. It also
395 driver for the Altera 16550 UART. One or more Altera 16550 UARTs
500 its UARTs, say Y to this option. If unsure, say N.
538 I/O UARTs that are not covered by the more generic SERIAL_8250_PCI
|
| /openbmc/linux/drivers/tty/serial/ |
| H A D | Kconfig | 136 This enables the driver for the on-chip UARTs of the Atmel
169 Say Y here if you wish to have the internal AT91 UARTs
172 64). This is necessary if you also want other UARTs, such as
173 external 8250/16C550 compatible UARTs.
206 This enables the driver for the on-chip UARTs of the Amlogic
226 This enables the driver for the on-chip UARTs of the Cirrus
244 Support for the on-chip UARTs on the Samsung
280 Support for the on-chip UARTs on the NVIDIA Tegra series SOCs
675 Those are UARTs completely different from the Standard UARTs on the
749 UARTs.
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| /openbmc/phosphor-mrw-tools/docs/ |
| H A D | mrw-xml-requirements.md | 81 ### UARTS subsection
83 UARTs are enabled by connecting the appropriate UART master units in the BMC
|
| /openbmc/obmc-console/ |
| H A D | README.md | 41 … +->+ @obmc-console.host0 +<-+ <--+ /dev/ttyVUART0 | UARTs
58 In some hardware designs, multiple UARTS may be available behind a Mux. Please
|
| /openbmc/u-boot/board/freescale/ls1021atwr/ |
| H A D | README | 55 - Ten UARTs comprised of two 16550 compliant DUARTs, and six low power
56 UARTs
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| /openbmc/linux/arch/parisc/include/asm/ |
| H A D | serial.h | 6 * This is used for 16550-compatible UARTs
|
| /openbmc/u-boot/board/freescale/ls1021aqds/ |
| H A D | README | 55 - Ten UARTs comprised of two 16550 compliant DUARTs, and six low power
56 UARTs
|