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/openbmc/linux/drivers/scsi/qla4xxx/
H A Dql4_dbg.c83 (uint8_t) offsetof(struct isp_reg, u2.isp4010.ext_hw_conf), in qla4xxx_dump_registers()
84 readw(&ha->reg->u2.isp4010.ext_hw_conf)); in qla4xxx_dump_registers()
86 (uint8_t) offsetof(struct isp_reg, u2.isp4010.port_ctrl), in qla4xxx_dump_registers()
87 readw(&ha->reg->u2.isp4010.port_ctrl)); in qla4xxx_dump_registers()
89 (uint8_t) offsetof(struct isp_reg, u2.isp4010.port_status), in qla4xxx_dump_registers()
90 readw(&ha->reg->u2.isp4010.port_status)); in qla4xxx_dump_registers()
92 (uint8_t) offsetof(struct isp_reg, u2.isp4010.req_q_out), in qla4xxx_dump_registers()
93 readw(&ha->reg->u2.isp4010.req_q_out)); in qla4xxx_dump_registers()
95 (uint8_t) offsetof(struct isp_reg, u2.isp4010.gp_out), in qla4xxx_dump_registers()
96 readw(&ha->reg->u2.isp4010.gp_out)); in qla4xxx_dump_registers()
[all …]
H A Dql4_def.h943 &ha->reg->u2.isp4010.ext_hw_conf : in isp_ext_hw_conf()
944 &ha->reg->u2.isp4022.p0.ext_hw_conf); in isp_ext_hw_conf()
950 &ha->reg->u2.isp4010.port_status : in isp_port_status()
951 &ha->reg->u2.isp4022.p0.port_status); in isp_port_status()
957 &ha->reg->u2.isp4010.port_ctrl : in isp_port_ctrl()
958 &ha->reg->u2.isp4022.p0.port_ctrl); in isp_port_ctrl()
964 &ha->reg->u2.isp4010.port_err_status : in isp_port_error_status()
965 &ha->reg->u2.isp4022.p0.port_err_status); in isp_port_error_status()
971 &ha->reg->u2.isp4010.gp_out : in isp_gp_out()
972 &ha->reg->u2.isp4022.p0.gp_out); in isp_gp_out()
/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dmediatek,tphy.yaml24 u2 port0 0x0800 U2PHY_COM
29 u2 port1 0x1000 U2PHY_COM
34 u2 port2 0x1800 U2PHY_COM
39 u2 port0 0x0000 MISC
48 u2 port1 0x1000 MISC
57 u2 port2 0x2000 MISC
60 SPLLC shared by u3 ports and FMREG shared by u2 ports on V1 are put back
61 into each port; a new bank MISC for u2 ports and CHIP for u3 ports are
171 - description: internal R efuse for U2 PHY or U3/PCIe PHY
176 Available only for U2 PHY or U3/PCIe PHY of version 2/3, these
[all …]
H A Dmediatek,xsphy.yaml20 u2 port0 0x0000 MISC
23 u2 port1 0x1000 MISC
26 u2 port2 0x2000 MISC
57 if only U2 ports provided, shouldn't use the property.
113 The value of slew rate calibrate (U2 phy)
120 The selection of VRT reference voltage (U2 phy)
127 The selection of HS_TX TERM reference voltage (U2 phy)
134 The selection of Internal Resistor (U2/U3 phy)
/openbmc/bmcweb/redfish-core/include/generated/enums/
H A Dpcie_slots.hpp20 U2, enumerator
33 {SlotTypes::U2, "U2"},
H A Dpcie_device.hpp38 U2, enumerator
92 {SlotType::U2, "U2"},
H A Ddrive.hpp80 U2, enumerator
177 {FormFactor::U2, "U2"},
/openbmc/linux/lib/crypto/mpi/
H A Dmpi-inv.c33 MPI u, v, u1, u2 = NULL, u3, v1, v2 = NULL, v3, t1, t2 = NULL, t3; in mpi_invm() local
54 u2 = mpi_alloc_set_ui(0); in mpi_invm()
102 mpi_set(u2, t2); in mpi_invm()
116 mpi_sub(t2, u2, v2); in mpi_invm()
131 mpi_free(u2); in mpi_invm()
/openbmc/linux/include/linux/
H A Duuid.h46 static inline bool guid_equal(const guid_t *u1, const guid_t *u2) in guid_equal() argument
48 return memcmp(u1, u2, sizeof(guid_t)) == 0; in guid_equal()
71 static inline bool uuid_equal(const uuid_t *u1, const uuid_t *u2) in uuid_equal() argument
73 return memcmp(u1, u2, sizeof(uuid_t)) == 0; in uuid_equal()
/openbmc/linux/fs/smb/server/mgmt/
H A Duser_config.c71 bool ksmbd_compare_user(struct ksmbd_user *u1, struct ksmbd_user *u2) in ksmbd_compare_user() argument
73 if (strcmp(u1->name, u2->name)) in ksmbd_compare_user()
75 if (memcmp(u1->passkey, u2->passkey, u1->passkey_sz)) in ksmbd_compare_user()
/openbmc/qemu/target/ppc/
H A Dfpu_helper.c1123 CPU_FloatU u1, u2; in efsadd() local
1126 u2.l = op2; in efsadd()
1127 u1.f = float32_add(u1.f, u2.f, &env->vec_status); in efsadd()
1133 CPU_FloatU u1, u2; in efssub() local
1136 u2.l = op2; in efssub()
1137 u1.f = float32_sub(u1.f, u2.f, &env->vec_status); in efssub()
1143 CPU_FloatU u1, u2; in efsmul() local
1146 u2.l = op2; in efsmul()
1147 u1.f = float32_mul(u1.f, u2.f, &env->vec_status); in efsmul()
1153 CPU_FloatU u1, u2; in efsdiv() local
[all …]
/openbmc/linux/crypto/
H A Decdsa.c87 u64 u2[ECC_MAX_DIGITS]; in _ecdsa_verify() local
105 /* u2 = (r * s1) mod n */ in _ecdsa_verify()
106 vli_mod_mult_slow(u2, r, s1, curve->n, ndigits); in _ecdsa_verify()
107 /* res = u1*G + u2 * pub_key */ in _ecdsa_verify()
108 ecc_point_mult_shamir(&res, u1, &curve->g, u2, &ctx->pub_key, curve); in _ecdsa_verify()
/openbmc/linux/drivers/usb/mtu3/
H A Dmtu3_host.c156 /* power on and enable all u2 ports */ in ssusb_host_enable()
192 /* power down and disable u2 ports except skipped ones */ in ssusb_host_disable()
237 /* power on all u2 ports except skipped ones */ in ssusb_host_resume()
269 /* power down u2 ports except skipped ones */ in ssusb_host_suspend()
H A Dmtu3_core.c95 /* only port0 of U2/U3 supports device mode */
182 /* Clear U2 USB common interrupts status */ in mtu3_intr_status_clear()
212 /* Enable U2 common USB interrupts */ in mtu3_intr_enable()
277 /* disable LGO_U1/U2 by default */ in mtu3_csr_init()
280 /* enable accept LGO_U1/U2 link command from host */ in mtu3_csr_init()
285 /* automatically build U2 link when U3 detect fail */ in mtu3_csr_init()
297 /* reset: u2 - data toggle, u3 - SeqN, flow control status etc */
660 /* U2/U3 detected by HW */ in mtu3_regs_init()
869 mtu->u3_capable ? "U3" : "U2"); in mtu3_hw_init()
/openbmc/u-boot/include/linux/usb/
H A Dch9.h145 #define USB_DEVICE_U2_ENABLE 49 /* dev may initiate U2 transition */
160 #define USB_DEV_STAT_U2_ENABLED 3 /* transition into U2 state */
1011 * A U2 timeout of 0x0 means the parent hub will reject any transitions to U2.
1012 * 0xff means the parent hub will accept transitions to U2, but will not
1015 * A U2 timeout of 0x1 to 0xFE also causes the hub to initiate a transition to
1016 * U2 after N*256 microseconds. Therefore a U2 timeout value of 0x1 means a U2
1034 * U1 SEL and U1 PEL, so the max exit latency is 0xFF. U2 SEL and U2 PEL each
/openbmc/qemu/target/hexagon/imported/
H A Dldst.idef25 Q6INSN(L4_##TAG##_ur, OPER"(Rt32<<#u2+#U6)", ATTRIB,DESCR,{fMUST_IMMEXT(UiV); fEA_IRs(…
109 Q6INSN(S4_##TAG##_ur, OPER"(Ru32<<#u2+#U6)="DEST, ATTRIB,DESCR,{fMUST_IMMEXT(UiV); fEA_…
220 Q6INSN(L4_##TAG##_rr, OPER"(Rs32+Rt32<<#u2)", ATTRIB,DESCR,{fEA_RRs(RsV,RtV,uiV); SEMAN…
227 Q6INSN(L4_p##TAG##t_rr, "if (Pv4) "OPER"(Rs32+Rt32<<#u2)", ATTRIB,DESCR,{fEA_RRs(RsV,RtV…
228 Q6INSN(L4_p##TAG##f_rr, "if (!Pv4) "OPER"(Rs32+Rt32<<#u2)", ATTRIB,DESCR,{fEA_RRs(RsV,RtV…
229 Q6INSN(L4_p##TAG##tnew_rr,"if (Pv4.new) "OPER"(Rs32+Rt32<<#u2)",ATTRIB,DESCR,{fEA_RRs(RsV,RtV,uiV);…
230 Q6INSN(L4_p##TAG##fnew_rr,"if (!Pv4.new) "OPER"(Rs32+Rt32<<#u2)",ATTRIB,DESCR,{fEA_RRs(RsV,RtV,uiV)…
250 Q6INSN(S4_##TAG##_rr, OPER"(Rs32+Ru32<<#u2)="DEST, ATTRIB,DESCR,{fEA_RRs(RsV,RuV,uiV); …
255 Q6INSN(S4_p##TAG##t_rr, "if (Pv4) "OPER"(Rs32+Ru32<<#u2)="DEST, ATTRIB,DESCR,{fEA_RRs(RsV,RuV,u…
256 Q6INSN(S4_p##TAG##f_rr, "if (!Pv4) "OPER"(Rs32+Ru32<<#u2)="DEST, ATTRIB,DESCR,{fEA_RRs(RsV,RuV,…
[all …]
H A Dsubinsns.idef50 Q6INSN(SA1_combine0i,"Rdd8=combine(#0,#u2)", ATTRIBS(A_SUBINSN,A_ROPS_2),"Combines", { fSETWORD(0…
51 Q6INSN(SA1_combine1i,"Rdd8=combine(#1,#u2)", ATTRIBS(A_SUBINSN,A_ROPS_2),"Combines", { fSETWORD(0…
52 Q6INSN(SA1_combine2i,"Rdd8=combine(#2,#u2)", ATTRIBS(A_SUBINSN,A_ROPS_2),"Combines", { fSETWORD(0…
53 Q6INSN(SA1_combine3i,"Rdd8=combine(#3,#u2)", ATTRIBS(A_SUBINSN,A_ROPS_2),"Combines", { fSETWORD(0…
54 Q6INSN(SA1_cmpeqi, "p0=cmp.eq(Rs16,#u2)", ATTRIBS(A_SUBINSN),"CompareImmed",{fWRITE_P0(f8BITSOF…
/openbmc/linux/arch/powerpc/include/asm/
H A Duninorth.h5 * This also includes U2 used on more recent MacRISC2/3
109 #define UNI_N_VERSION_INTREPID 0x00D2 /* Integrated U2 + K */
117 #define UNI_N_CLOCK_CNTL_ATA100 0x00000010 /* ATA-100 clock control (U2) */
/openbmc/linux/Documentation/devicetree/bindings/usb/
H A Dsnps,dwc3.yaml150 description: Set if we enable P3 OK for U2/SS Inactive quirk
210 snps,dis-u2-entry-quirk:
211 description: Set if link entering into U2 needs to be disabled
219 snps,dis-u2-freeclk-exists-quirk:
/openbmc/linux/include/uapi/linux/usb/
H A Dch9.h153 #define USB_DEVICE_U2_ENABLE 49 /* dev may initiate U2 transition */
174 #define USB_DEV_STAT_U2_ENABLED 3 /* transition into U2 state */
1230 * A U2 timeout of 0x0 means the parent hub will reject any transitions to U2.
1231 * 0xff means the parent hub will accept transitions to U2, but will not
1234 * A U2 timeout of 0x1 to 0xFE also causes the hub to initiate a transition to
1235 * U2 after N*256 microseconds. Therefore a U2 timeout value of 0x1 means a U2
1253 * U1 SEL and U1 PEL, so the max exit latency is 0xFF. U2 SEL and U2 PEL each
/openbmc/linux/Documentation/ABI/testing/
H A Dsysfs-bus-usb115 and U2 exit latencies have been set in the BOS descriptor; if
121 or not USB3 hardware LPM U1 or U2 is enabled for the device.
226 values are "0" if both u1 and u2 are NOT permitted, "u1" if only u1
227 is permitted, "u2" if only u2 is permitted, "u1_u2" if both u1 and
228 u2 are permitted.
/openbmc/linux/drivers/parisc/
H A Dccio-dma.c5 ** Program U2/Uturn in "Virtual Mode" and use the I/O MMU.
11 ** "Real Mode" operation refers to U2/Uturn chip operation.
12 ** U2/Uturn were designed to perform coherency checks w/o using
16 ** o outbound DMA is slower - U2 won't prefetch data (GSC+ XQL signal).
17 ** o Inbound DMA less efficient - U2 can't use DMA_FAST attribute.
474 ** This bit tells U2 to do R/M/W for partial cachelines. "Streaming"
480 ** According to the U2 ERS, STOP_MOST enabled pages hurt performance.
501 #define HINT_UDPATE_ENB 0x08UL /* not used/supported by U2 */
599 ** the real mode coherence index generation of U2, the PDIR entry in ccio_io_pdir_entry()
1175 /* GRANT - is this needed for U2 or not? */
[all …]
H A DKconfig24 bool "U2/Uturn I/O MMU"
29 U2/Uturn chip in "Virtual Mode" and use the I/O MMU.
/openbmc/linux/drivers/usb/cdns3/
H A Dcdns3-gadget.h177 /* U2 state entry enable (used in SS mode). */
179 /* U2 state entry disable (used in SS mode). */
185 /* U2 state entry request (used in SS mode). */
338 * U2 state enable status (used in SS mode).
339 * 0 - Entering to U2 state disabled.
340 * 1 - Entering to U2 state enabled.
364 * 1 - DMA clock turn-off in U1, U2 and U3 (SS mode) is enabled.
441 /* SS link U2 state enter interrupt enable.*/
443 /* SS link U2 state exit interrupt enable.*/
494 /* U2 link state enter detected.*/
[all …]
/openbmc/u-boot/drivers/usb/host/
H A Dxhci-rockchip.c85 if (dev_read_bool(dev, "snps,dis-u2-freeclk-exists-quirk")) in rockchip_dwc3_phy_setup()
88 if (dev_read_bool(dev, "snps,dis-u2-susphy-quirk")) in rockchip_dwc3_phy_setup()

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