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/openbmc/linux/drivers/net/ethernet/microchip/sparx5/
H A Dsparx5_mactable.c2 /* Microchip Sparx5 Switch driver
44 static int sparx5_mact_get_status(struct sparx5 *sparx5) in sparx5_mact_get_status() argument
46 return spx5_rd(sparx5, LRN_COMMON_ACCESS_CTRL); in sparx5_mact_get_status()
49 static int sparx5_mact_wait_for_completion(struct sparx5 *sparx5) in sparx5_mact_wait_for_completion() argument
54 sparx5, val, in sparx5_mact_wait_for_completion()
59 static void sparx5_mact_select(struct sparx5 *sparx5, in sparx5_mact_select() argument
76 spx5_wr(mach, sparx5, LRN_MAC_ACCESS_CFG_0); in sparx5_mact_select()
77 spx5_wr(macl, sparx5, LRN_MAC_ACCESS_CFG_1); in sparx5_mact_select()
80 int sparx5_mact_learn(struct sparx5 *sparx5, int pgid, in sparx5_mact_learn() argument
94 mutex_lock(&sparx5->lock); in sparx5_mact_learn()
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H A Dsparx5_sdlb.c2 /* Microchip Sparx5 Switch driver
23 int sparx5_sdlb_clk_hz_get(struct sparx5 *sparx5) in sparx5_sdlb_clk_hz_get() argument
28 clk_per_100ps = HSCH_SYS_CLK_PER_100PS_GET(spx5_rd(sparx5, in sparx5_sdlb_clk_hz_get()
37 static int sparx5_sdlb_pup_interval_get(struct sparx5 *sparx5, u32 max_token, in sparx5_sdlb_pup_interval_get() argument
42 clk_hz = sparx5_sdlb_clk_hz_get(sparx5); in sparx5_sdlb_pup_interval_get()
47 int sparx5_sdlb_pup_token_get(struct sparx5 *sparx5, u32 pup_interval, u64 rate) in sparx5_sdlb_pup_token_get() argument
54 clk_hz = sparx5_sdlb_clk_hz_get(sparx5); in sparx5_sdlb_pup_token_get()
59 static void sparx5_sdlb_group_disable(struct sparx5 *sparx5, u32 group) in sparx5_sdlb_group_disable() argument
62 ANA_AC_SDLB_PUP_CTRL_PUP_ENA, sparx5, in sparx5_sdlb_group_disable()
66 static void sparx5_sdlb_group_enable(struct sparx5 *sparx5, u32 group) in sparx5_sdlb_group_enable() argument
[all …]
H A Dsparx5_ptp.c2 /* Microchip Sparx5 Switch driver
6 * The Sparx5 Chip Register Model can be browsed at this location:
27 static u64 sparx5_ptp_get_1ppm(struct sparx5 *sparx5) in sparx5_ptp_get_1ppm() argument
37 switch (sparx5->coreclock) { in sparx5_ptp_get_1ppm()
55 static u64 sparx5_ptp_get_nominal_value(struct sparx5 *sparx5) in sparx5_ptp_get_nominal_value() argument
59 switch (sparx5->coreclock) { in sparx5_ptp_get_nominal_value()
81 struct sparx5 *sparx5 = port->sparx5; in sparx5_ptp_hwtstamp_set() local
89 if (test_bit(port->portno, sparx5->bridge_mask)) in sparx5_ptp_hwtstamp_set()
130 mutex_lock(&sparx5->ptp_lock); in sparx5_ptp_hwtstamp_set()
131 phc = &sparx5->phc[SPARX5_PHC_PORT]; in sparx5_ptp_hwtstamp_set()
[all …]
H A Dsparx5_psfp.c2 /* Microchip Sparx5 Switch driver
55 u32 sparx5_psfp_isdx_get_sf(struct sparx5 *sparx5, u32 isdx) in sparx5_psfp_isdx_get_sf() argument
57 return ANA_L2_TSN_CFG_TSN_SFID_GET(spx5_rd(sparx5, in sparx5_psfp_isdx_get_sf()
61 u32 sparx5_psfp_isdx_get_fm(struct sparx5 *sparx5, u32 isdx) in sparx5_psfp_isdx_get_fm() argument
63 return ANA_L2_DLB_CFG_DLB_IDX_GET(spx5_rd(sparx5, in sparx5_psfp_isdx_get_fm()
67 u32 sparx5_psfp_sf_get_sg(struct sparx5 *sparx5, u32 sfid) in sparx5_psfp_sf_get_sg() argument
69 return ANA_AC_TSN_SF_CFG_TSN_SGID_GET(spx5_rd(sparx5, in sparx5_psfp_sf_get_sg()
73 void sparx5_isdx_conf_set(struct sparx5 *sparx5, u32 isdx, u32 sfid, u32 fmid) in sparx5_isdx_conf_set() argument
76 sparx5, ANA_L2_TSN_CFG(isdx)); in sparx5_isdx_conf_set()
79 sparx5, ANA_L2_DLB_CFG(isdx)); in sparx5_isdx_conf_set()
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H A Dsparx5_main.h2 /* Microchip Sparx5 Switch driver
100 struct sparx5;
169 struct sparx5 *sparx5; member
209 struct sparx5 *sparx5; member
234 struct sparx5 { struct
303 int sparx5_register_notifier_blocks(struct sparx5 *sparx5); argument
304 void sparx5_unregister_notifier_blocks(struct sparx5 *sparx5);
312 void sparx5_xtr_flush(struct sparx5 *sparx5, u8 grp);
316 int sparx5_manual_injection_mode(struct sparx5 *sparx5);
320 int sparx5_fdma_start(struct sparx5 *sparx5);
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H A Dsparx5_vlan.c2 /* Microchip Sparx5 Switch driver
10 static int sparx5_vlant_set_mask(struct sparx5 *sparx5, u16 vid) in sparx5_vlant_set_mask() argument
15 bitmap_to_arr32(mask, sparx5->vlan_mask[vid], SPX5_PORTS); in sparx5_vlant_set_mask()
18 spx5_wr(mask[0], sparx5, ANA_L3_VLAN_MASK_CFG(vid)); in sparx5_vlant_set_mask()
19 spx5_wr(mask[1], sparx5, ANA_L3_VLAN_MASK_CFG1(vid)); in sparx5_vlant_set_mask()
20 spx5_wr(mask[2], sparx5, ANA_L3_VLAN_MASK_CFG2(vid)); in sparx5_vlant_set_mask()
25 void sparx5_vlan_init(struct sparx5 *sparx5) in sparx5_vlan_init() argument
31 sparx5, in sparx5_vlan_init()
38 sparx5, in sparx5_vlan_init()
42 void sparx5_vlan_port_setup(struct sparx5 *sparx5, int portno) in sparx5_vlan_port_setup() argument
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H A Dsparx5_main.c2 /* Microchip Sparx5 Switch driver
6 * The Sparx5 Chip Register Model can be browsed at this location:
217 static int sparx5_create_targets(struct sparx5 *sparx5) in sparx5_create_targets() argument
234 iores[idx] = platform_get_resource(sparx5->pdev, IORESOURCE_MEM, in sparx5_create_targets()
237 dev_err(sparx5->dev, "Invalid resource\n"); in sparx5_create_targets()
240 iomem[idx] = devm_ioremap(sparx5->dev, in sparx5_create_targets()
244 dev_err(sparx5->dev, "Unable to get switch registers: %s\n", in sparx5_create_targets()
253 sparx5->regs[iomap->id] = begin[iomap->range] + iomap->offset; in sparx5_create_targets()
258 static int sparx5_create_port(struct sparx5 *sparx5, in sparx5_create_port() argument
266 ndev = sparx5_create_netdev(sparx5, config->portno); in sparx5_create_port()
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H A Dsparx5_qos.c2 /* Microchip Sparx5 Switch driver
24 void sparx5_new_base_time(struct sparx5 *sparx5, const u32 cycle_time, in sparx5_new_base_time() argument
35 sparx5_ptp_gettime64(&sparx5->phc[SPARX5_PHC_PORT].info, &ts); in sparx5_new_base_time()
79 static u32 sparx5_lg_get_leak_time(struct sparx5 *sparx5, u32 layer, u32 group) in sparx5_lg_get_leak_time() argument
83 value = spx5_rd(sparx5, HSCH_HSCH_TIMER_CFG(layer, group)); in sparx5_lg_get_leak_time()
87 static void sparx5_lg_set_leak_time(struct sparx5 *sparx5, u32 layer, u32 group, in sparx5_lg_set_leak_time() argument
90 spx5_wr(HSCH_HSCH_TIMER_CFG_LEAK_TIME_SET(leak_time), sparx5, in sparx5_lg_set_leak_time()
94 static u32 sparx5_lg_get_first(struct sparx5 *sparx5, u32 layer, u32 group) in sparx5_lg_get_first() argument
98 value = spx5_rd(sparx5, HSCH_HSCH_LEAK_CFG(layer, group)); in sparx5_lg_get_first()
102 static u32 sparx5_lg_get_next(struct sparx5 *sparx5, u32 layer, u32 group, in sparx5_lg_get_next() argument
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H A Dsparx5_fdma.c2 /* Microchip Sparx5 Switch driver
6 * The Sparx5 Chip Register Model can be browsed at this location:
113 static void sparx5_fdma_rx_activate(struct sparx5 *sparx5, struct sparx5_rx *rx) in sparx5_fdma_rx_activate() argument
116 spx5_wr(((u64)rx->dma) & GENMASK(31, 0), sparx5, in sparx5_fdma_rx_activate()
118 spx5_wr(((u64)rx->dma) >> 32, sparx5, FDMA_DCB_LLP1(rx->channel_id)); in sparx5_fdma_rx_activate()
124 sparx5, FDMA_CH_CFG(rx->channel_id)); in sparx5_fdma_rx_activate()
128 sparx5, in sparx5_fdma_rx_activate()
133 sparx5, FDMA_PORT_CTRL(0)); in sparx5_fdma_rx_activate()
138 sparx5, FDMA_INTR_DB_ENA); in sparx5_fdma_rx_activate()
141 spx5_wr(BIT(rx->channel_id), sparx5, FDMA_CH_ACTIVATE); in sparx5_fdma_rx_activate()
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H A Dsparx5_vcap_impl.c2 /* Microchip Sparx5 Switch driver VCAP implementation
6 * The Sparx5 Chip Register Model can be browsed at this location:
168 static void sparx5_vcap_type_err(struct sparx5 *sparx5, in sparx5_vcap_type_err() argument
177 static void sparx5_vcap_wait_super_update(struct sparx5 *sparx5) in sparx5_vcap_wait_super_update() argument
183 false, sparx5, VCAP_SUPER_CTRL); in sparx5_vcap_wait_super_update()
187 static void sparx5_vcap_wait_es0_update(struct sparx5 *sparx5) in sparx5_vcap_wait_es0_update() argument
193 false, sparx5, VCAP_ES0_CTRL); in sparx5_vcap_wait_es0_update()
197 static void sparx5_vcap_wait_es2_update(struct sparx5 *sparx5) in sparx5_vcap_wait_es2_update() argument
203 false, sparx5, VCAP_ES2_CTRL); in sparx5_vcap_wait_es2_update()
207 static void _sparx5_vcap_range_init(struct sparx5 *sparx5, in _sparx5_vcap_range_init() argument
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H A Dsparx5_port.c2 /* Microchip Sparx5 Switch driver
78 static int sparx5_get_dev2g5_status(struct sparx5 *sparx5, in sparx5_get_dev2g5_status() argument
87 value = spx5_rd(sparx5, DEV2G5_PCS1G_STICKY(portno)); in sparx5_get_dev2g5_status()
90 spx5_wr(value, sparx5, DEV2G5_PCS1G_STICKY(portno)); in sparx5_get_dev2g5_status()
93 value = spx5_rd(sparx5, DEV2G5_PCS1G_LINK_STATUS(portno)); in sparx5_get_dev2g5_status()
105 value = spx5_rd(sparx5, DEV2G5_PCS1G_ANEG_STATUS(portno)); in sparx5_get_dev2g5_status()
113 value = spx5_rd(sparx5, DEV2G5_PCS1G_ANEG_CFG(portno)); in sparx5_get_dev2g5_status()
121 static int sparx5_get_sfi_status(struct sparx5 *sparx5, in sparx5_get_sfi_status() argument
137 inst = spx5_inst_get(sparx5, dev, tinst); in sparx5_get_sfi_status()
160 int sparx5_get_port_status(struct sparx5 *sparx5, in sparx5_get_port_status() argument
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H A Dsparx5_switchdev.c2 /* Microchip Sparx5 Switch driver
19 struct sparx5 *sparx5; member
58 struct sparx5 *sparx5 = port->sparx5; in sparx5_attr_stp_state_set() local
60 if (!test_bit(port->portno, sparx5->bridge_mask)) { in sparx5_attr_stp_state_set()
68 set_bit(port->portno, sparx5->bridge_fwd_mask); in sparx5_attr_stp_state_set()
71 set_bit(port->portno, sparx5->bridge_lrn_mask); in sparx5_attr_stp_state_set()
76 clear_bit(port->portno, sparx5->bridge_fwd_mask); in sparx5_attr_stp_state_set()
77 clear_bit(port->portno, sparx5->bridge_lrn_mask); in sparx5_attr_stp_state_set()
82 sparx5_update_fwd(sparx5); in sparx5_attr_stp_state_set()
91 sparx5_set_ageing(port->sparx5, ageing_time); in sparx5_port_attr_ageing_set()
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H A Dsparx5_packet.c2 /* Microchip Sparx5 Switch driver
23 void sparx5_xtr_flush(struct sparx5 *sparx5, u8 grp) in sparx5_xtr_flush() argument
26 spx5_wr(QS_XTR_FLUSH_FLUSH_SET(BIT(grp)), sparx5, QS_XTR_FLUSH); in sparx5_xtr_flush()
32 spx5_wr(0, sparx5, QS_XTR_FLUSH); in sparx5_xtr_flush()
59 static void sparx5_xtr_grp(struct sparx5 *sparx5, u8 grp, bool byte_swap) in sparx5_xtr_grp() argument
72 ifh[i] = spx5_rd(sparx5, QS_XTR_RD(grp)); in sparx5_xtr_grp()
79 sparx5->ports[fi.src_port] : NULL; in sparx5_xtr_grp()
81 dev_err(sparx5->dev, "Data on inactive port %d\n", fi.src_port); in sparx5_xtr_grp()
82 sparx5_xtr_flush(sparx5, grp); in sparx5_xtr_grp()
90 sparx5_xtr_flush(sparx5, grp); in sparx5_xtr_grp()
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H A Dsparx5_ethtool.c2 /* Microchip Sparx5 Switch driver
201 static void sparx5_get_queue_sys_stats(struct sparx5 *sparx5, int portno) in sparx5_get_queue_sys_stats() argument
208 portstats = &sparx5->stats[portno * sparx5->num_stats]; in sparx5_get_queue_sys_stats()
209 mutex_lock(&sparx5->queue_stats_lock); in sparx5_get_queue_sys_stats()
210 spx5_wr(XQS_STAT_CFG_STAT_VIEW_SET(portno), sparx5, XQS_STAT_CFG); in sparx5_get_queue_sys_stats()
214 sparx5_update_counter(stats, spx5_rd(sparx5, XQS_CNT(addr))); in sparx5_get_queue_sys_stats()
218 sparx5_update_counter(stats, spx5_rd(sparx5, XQS_CNT(addr))); in sparx5_get_queue_sys_stats()
222 sparx5_update_counter(stats, spx5_rd(sparx5, XQS_CNT(addr))); in sparx5_get_queue_sys_stats()
224 spx5_rd(sparx5, XQS_CNT(32))); in sparx5_get_queue_sys_stats()
226 spx5_rd(sparx5, XQS_CNT(272))); in sparx5_get_queue_sys_stats()
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H A Dsparx5_netdev.c2 /* Microchip Sparx5 Switch driver
116 err = sparx5_serdes_set(port->sparx5, port, &port->conf); in sparx5_port_open()
149 err = sparx5_serdes_set(port->sparx5, port, &port->conf); in sparx5_port_stop()
161 struct sparx5 *sparx5 = port->sparx5; in sparx5_set_rx_mode() local
163 if (!test_bit(port->portno, sparx5->bridge_mask)) in sparx5_set_rx_mode()
183 struct sparx5 *sparx5 = port->sparx5; in sparx5_set_mac_address() local
190 sparx5_mact_forget(sparx5, dev->dev_addr, port->pvid); in sparx5_set_mac_address()
193 sparx5_mact_learn(sparx5, PGID_CPU, addr->sa_data, port->pvid); in sparx5_set_mac_address()
205 struct sparx5 *sparx5 = sparx5_port->sparx5; in sparx5_get_port_parent_id() local
207 ppid->id_len = sizeof(sparx5->base_mac); in sparx5_get_port_parent_id()
[all …]
H A Dsparx5_calendar.c2 /* Microchip Sparx5 Switch driver
53 static u32 sparx5_target_bandwidth(struct sparx5 *sparx5) in sparx5_target_bandwidth() argument
55 switch (sparx5->target_ct) { in sparx5_target_bandwidth()
129 static enum sparx5_cal_bw sparx5_get_port_cal_speed(struct sparx5 *sparx5, in sparx5_get_port_cal_speed() argument
153 port = sparx5->ports[portno]; in sparx5_get_port_cal_speed()
160 int sparx5_config_auto_calendar(struct sparx5 *sparx5) in sparx5_config_auto_calendar() argument
170 max_core_bw = sparx5_clk_to_bandwidth(sparx5->coreclock); in sparx5_config_auto_calendar()
172 dev_err(sparx5->dev, "Core clock not supported"); in sparx5_config_auto_calendar()
180 spd = sparx5_get_port_cal_speed(sparx5, portno); in sparx5_config_auto_calendar()
196 if (used_port_bw > sparx5_target_bandwidth(sparx5)) { in sparx5_config_auto_calendar()
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H A Dsparx5_police.c2 /* Microchip Sparx5 Switch driver
10 static int sparx5_policer_service_conf_set(struct sparx5 *sparx5, in sparx5_policer_service_conf_set() argument
23 pup_tokens = sparx5_sdlb_pup_token_get(sparx5, g->pup_interval, rate); in sparx5_policer_service_conf_set()
25 sparx5_sdlb_pup_token_get(sparx5, g->pup_interval, g->max_rate); in sparx5_policer_service_conf_set()
29 spx5_wr(ANA_AC_SDLB_PUP_TOKENS_PUP_TOKENS_SET(pup_tokens), sparx5, in sparx5_policer_service_conf_set()
33 ANA_AC_SDLB_INH_CTRL_PUP_TOKENS_MAX, sparx5, in sparx5_policer_service_conf_set()
37 sparx5, ANA_AC_SDLB_THRES(idx, 0)); in sparx5_policer_service_conf_set()
42 int sparx5_policer_conf_set(struct sparx5 *sparx5, struct sparx5_policer *pol) in sparx5_policer_conf_set() argument
47 return sparx5_policer_service_conf_set(sparx5, pol); in sparx5_policer_conf_set()
H A Dsparx5_vcap_debugfs.c2 /* Microchip Sparx5 Switch driver VCAP debugFS implementation
76 static void sparx5_vcap_is0_port_keys(struct sparx5 *sparx5, in sparx5_vcap_is0_port_keys() argument
90 value = spx5_rd(sparx5, in sparx5_vcap_is0_port_keys()
119 static void sparx5_vcap_is2_port_keys(struct sparx5 *sparx5, in sparx5_vcap_is2_port_keys() argument
133 value = spx5_rd(sparx5, ANA_ACL_VCAP_S2_CFG(port->portno)); in sparx5_vcap_is2_port_keys()
141 value = spx5_rd(sparx5, in sparx5_vcap_is2_port_keys()
232 static void sparx5_vcap_is2_port_stickies(struct sparx5 *sparx5, in sparx5_vcap_is2_port_stickies() argument
243 value = spx5_rd(sparx5, ANA_ACL_SEC_LOOKUP_STICKY(lookup)); in sparx5_vcap_is2_port_stickies()
282 spx5_wr(value, sparx5, ANA_ACL_SEC_LOOKUP_STICKY(lookup)); in sparx5_vcap_is2_port_stickies()
287 static void sparx5_vcap_es0_port_keys(struct sparx5 *sparx5, in sparx5_vcap_es0_port_keys() argument
[all …]
H A Dsparx5_port.h2 /* Microchip Sparx5 Switch driver
73 int sparx5_port_init(struct sparx5 *sparx5,
77 int sparx5_port_config(struct sparx5 *sparx5,
81 int sparx5_port_pcs_set(struct sparx5 *sparx5,
85 int sparx5_serdes_set(struct sparx5 *sparx5,
98 int sparx5_get_port_status(struct sparx5 *sparx5,
103 int sparx5_port_fwd_urg(struct sparx5 *sparx5, u32 speed);
H A Dsparx5_tc_matchall.c20 struct sparx5 *sparx5; in sparx5_tc_matchall_replace() local
30 sparx5 = port->sparx5; in sparx5_tc_matchall_replace()
33 err = vcap_enable_lookups(sparx5->vcap_ctrl, ndev, in sparx5_tc_matchall_replace()
70 struct sparx5 *sparx5; in sparx5_tc_matchall_destroy() local
73 sparx5 = port->sparx5; in sparx5_tc_matchall_destroy()
75 err = vcap_enable_lookups(sparx5->vcap_ctrl, ndev, in sparx5_tc_matchall_destroy()
H A DMakefile3 # Makefile for the Microchip Sparx5 network device drivers.
6 obj-$(CONFIG_SPARX5_SWITCH) += sparx5-switch.o
8 sparx5-switch-y := sparx5_main.o sparx5_packet.o \
15 sparx5-switch-$(CONFIG_SPARX5_DCB) += sparx5_dcb.o
16 sparx5-switch-$(CONFIG_DEBUG_FS) += sparx5_vcap_debugfs.o
/openbmc/linux/drivers/net/ethernet/microchip/vcap/
H A Dvcap_ag_api.h28 VCAP_KFS_ARP, /* sparx5 is2 X6, sparx5 es2 X6, lan966x is2 X2 */
31 VCAP_KFS_ETAG, /* sparx5 is0 X2 */
32 VCAP_KFS_IP4_OTHER, /* sparx5 is2 X6, sparx5 es2 X6, lan966x is2 X2 */
33 VCAP_KFS_IP4_TCP_UDP, /* sparx5 is2 X6, sparx5 es2 X6, lan966x is2 X2 */
34 VCAP_KFS_IP4_VID, /* sparx5 es2 X3 */
36 VCAP_KFS_IP6_STD, /* sparx5 is2 X6, sparx5 es2 X6, lan966x is2 X2 */
38 VCAP_KFS_IP6_VID, /* sparx5 es2 X6 */
39 VCAP_KFS_IP_7TUPLE, /* sparx5 is2 X12, sparx5 es2 X12 */
40 VCAP_KFS_ISDX, /* sparx5 es0 X1 */
41 VCAP_KFS_LL_FULL, /* sparx5 is0 X6 */
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/openbmc/linux/Documentation/devicetree/bindings/arm/
H A Dmicrochip,sparx5.yaml4 $id: http://devicetree.org/schemas/arm/microchip,sparx5.yaml#
7 title: Microchip Sparx5 Boards
13 The Microchip Sparx5 SoC is a ARMv8-based used in a family of
27 - description: The Sparx5 pcb125 board is a modular board,
31 - const: microchip,sparx5-pcb125
32 - const: microchip,sparx5
34 - description: The Sparx5 pcb134 is a pizzabox form factor
38 - const: microchip,sparx5-pcb134
39 - const: microchip,sparx5
41 - description: The Sparx5 pcb135 is a pizzabox form factor
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/openbmc/linux/arch/arm64/boot/dts/microchip/
H A Dsparx5.dtsi8 #include <dt-bindings/clock/microchip,sparx5.h>
11 compatible = "microchip,sparx5";
86 compatible = "microchip,sparx5-dpll";
125 compatible = "microchip,sparx5-cpu-syscon", "syscon",
141 compatible = "microchip,sparx5-switch-reset";
177 compatible = "microchip,sparx5-spi";
196 compatible = "microchip,dw-sparx5-sdhci";
210 compatible = "microchip,sparx5-pinctrl";
303 compatible = "microchip,sparx5-sgpio";
312 compatible = "microchip,sparx5-sgpio-bank";
[all …]
/openbmc/linux/Documentation/devicetree/bindings/hwmon/
H A Dmicrochip,sparx5-temp.yaml4 $id: http://devicetree.org/schemas/hwmon/microchip,sparx5-temp.yaml#
7 title: Microchip Sparx5 Temperature Monitor
13 Microchip Sparx5 embedded temperature monitor
18 - microchip,sparx5-temp
40 compatible = "microchip,sparx5-temp";

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