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/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dti,phy-am654-serdes.yaml4 $id: http://devicetree.org/schemas/phy/ti,phy-am654-serdes.yaml#
7 title: TI AM654 SERDES
10 This binding describes the TI AM654 SERDES. AM654 SERDES can be configured
19 - ti,phy-am654-serdes
26 - const: serdes
41 include/dt-bindings/phy/phy.h) and the 2nd cell should be the serdes lane function.
43 ti,serdes-clk:
44 description: Phandle to the SYSCON entry required for configuring SERDES clock selection.
52 description: Phandle to the SYSCON entry required for configuring SERDES lane function.
56 - description: Clock output names for SERDES 0
[all …]
H A Dmscc,vsc7514-serdes.yaml4 $id: http://devicetree.org/schemas/phy/mscc,vsc7514-serdes.yaml#
7 title: Microsemi Ocelot SerDes muxing
15 space for setting up the SerDes to switch port muxing.
17 A SerDes X can be "muxed" to work with switch port Y or Z for example.
18 One specific SerDes can also be used as a PCIe interface.
20 Hence, a SerDes represents an interface, be it an Ethernet or a PCIe one.
22 There are two kinds of SerDes: SERDES1G supports 10/100Mbps in
35 - mscc,vsc7514-serdes
40 The first number defines the input port to use for a given SerDes macro.
42 dt-bindings/phy/phy-ocelot-serdes.h
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H A Dmicrochip,sparx5-serdes.yaml4 $id: http://devicetree.org/schemas/phy/microchip,sparx5-serdes.yaml#
7 title: Microchip Sparx5 Serdes controller
13 The Sparx5 SERDES interfaces share the same basic functionality, but
16 The following list lists the SERDES features:
31 The SERDES6G is a high-speed SERDES interface, which can operate at
41 The SERDES10G is a high-speed SERDES interface, which can operate at
54 The SERDES25G is a high-speed SERDES interface, which can operate at
67 pattern: "^serdes@[0-9a-f]+$"
70 const: microchip,sparx5-serdes
78 - The main serdes input port
[all …]
H A Dmicrochip,lan966x-serdes.yaml4 $id: http://devicetree.org/schemas/phy/microchip,lan966x-serdes.yaml#
7 title: Microchip Lan966x Serdes controller
16 interfaces. The Serdes controller will allow to configure these interfaces
23 interface SerDes 2.
27 pattern: "^serdes@[0-9a-f]+$"
30 const: microchip,lan966x-serdes
42 dt-bindings/phy/phy-lan966x-serdes.
53 serdes: serdes@e2004010 {
54 compatible = "microchip,lan966x-serdes";
H A Dti,phy-j721e-wiz.yaml8 title: TI J721E WIZ (SERDES Wrapper)
61 If GPIO is active, lane 0 and lane 1 of SERDES will be swapped to
118 the SERDES.
148 provided by the SERDES.
166 "^serdes@[0-9a-f]+$":
169 WIZ node should have '1' subnode for the SERDES. It could be either
170 Sierra SERDES or Torrent SERDES. Sierra SERDES should follow the
173 Torrent SERDES should follow the bindings specified in
248 serdes@5000000 {
250 reg-names = "serdes";
H A Drenesas,r8a779f0-ether-serdes.yaml4 $id: http://devicetree.org/schemas/phy/renesas,r8a779f0-ether-serdes.yaml#
7 title: Renesas Ethernet SERDES
14 const: renesas,r8a779f0-ether-serdes
29 description: Port number of SERDES.
48 compatible = "renesas,r8a779f0-ether-serdes";
/openbmc/u-boot/Documentation/devicetree/bindings/misc/
H A Dfsl,mpc83xx-serdes.txt1 MPC83xx SerDes controller devices
3 MPC83xx SoCs contain a built-in SerDes controller that determines which
4 protocols (SATA, PCI Express, SGMII, ...) are used on the system's serdes lines
8 - compatible: must be "fsl,mpc83xx-serdes"
9 - reg: must point to the serdes controller's register map
10 - proto: selects for which protocol the serdes lines are configured. One of
12 - serdes-clk: determines the frequency the serdes lines are configured for. One
18 SERDES: serdes@e3000 {
20 compatible = "fsl,mpc83xx-serdes";
22 serdes-clk = <100>;
/openbmc/linux/arch/arm64/boot/dts/microchip/
H A Dsparx5_pcb135_board.dtsi377 phys = <&serdes 13>;
384 phys = <&serdes 13>;
391 phys = <&serdes 13>;
398 phys = <&serdes 13>;
405 phys = <&serdes 14>;
412 phys = <&serdes 14>;
419 phys = <&serdes 14>;
426 phys = <&serdes 14>;
433 phys = <&serdes 15>;
440 phys = <&serdes 15>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/amd/
H A Damd-seattle-xgbe-b.dtsi40 <0 0xe1240800 0 0x00400>, /* SERDES RX/TX0 */
41 <0 0xe1250000 0 0x00060>, /* SERDES IR 1/2 */
42 <0 0xe12500f8 0 0x00004>; /* SERDES IR 2/2 */
48 amd,serdes-blwc = <1>, <1>, <0>;
49 amd,serdes-cdr-rate = <2>, <2>, <7>;
50 amd,serdes-pq-skew = <10>, <10>, <18>;
51 amd,serdes-tx-amp = <0>, <0>, <0>;
52 amd,serdes-dfe-tap-config = <3>, <3>, <3>;
53 amd,serdes-dfe-tap-enable = <0>, <0>, <7>;
66 <0 0xe1240c00 0 0x00400>, /* SERDES RX/TX1 */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Damd-xgbe.txt8 - SerDes Rx/Tx registers
9 - SerDes integration registers (1/2)
10 - SerDes integration registers (2/2)
43 - amd,serdes-blwc: Baseline wandering correction enablement
46 - amd,serdes-cdr-rate: CDR rate speed selection
47 - amd,serdes-pq-skew: PQ (data sampling) skew
48 - amd,serdes-tx-amp: TX amplitude boost
49 - amd,serdes-dfe-tap-config: DFE taps available to run
50 - amd,serdes-dfe-tap-enable: DFE taps to enable
70 amd,serdes-blwc = <1>, <1>, <0>;
[all …]
H A Dhisilicon-hns-dsaf.txt17 The second region is SerDes base register and size(optional, only used when
18 serdes-syscon in port node does not exist). It is recommended using
19 serdes-syscon rather than this address.
40 - serdes-syscon: is syscon handle for SerDes register.
81 serdes-syscon = <&serdes>;
87 serdes-syscon = <&serdes>;
/openbmc/u-boot/drivers/soc/keystone/
H A Dkeystone_serdes.c3 * TI serdes driver for keystone2.
49 /* SERDES PHY lane enable configuration value, indexed by PHY interface */
55 /* SERDES PHY PLL enable configuration value, indexed by PHY interface */
62 * Array to hold all possible serdes configurations.
139 static void ks2_serdes_cmu_comlane_enable(u32 base, struct ks2_serdes *serdes) in ks2_serdes_cmu_comlane_enable() argument
141 /* Bring SerDes out of Reset */ in ks2_serdes_cmu_comlane_enable()
143 if (serdes->intf == SERDES_PHY_PCSR) in ks2_serdes_cmu_comlane_enable()
148 if (serdes->intf == SERDES_PHY_PCSR) in ks2_serdes_cmu_comlane_enable()
154 static void ks2_serdes_pll_enable(u32 base, struct ks2_serdes *serdes) in ks2_serdes_pll_enable() argument
156 writel(serdes_cfg_pll_enable[serdes->intf], in ks2_serdes_pll_enable()
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/openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/
H A Dls1088a_serdes.c16 /* SerDes 1 */
36 /* SerDes 2 */
51 int serdes_get_number(int serdes, int cfg) in serdes_get_number() argument
57 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) in serdes_get_number()
60 ptr = serdes_cfg_tbl[serdes]; in serdes_get_number()
68 index = (serdes == FSL_SRDS_1) ? j : i; in serdes_get_number()
84 enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) in serdes_get_prtcl() argument
88 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) in serdes_get_prtcl()
91 ptr = serdes_cfg_tbl[serdes]; in serdes_get_prtcl()
101 int is_serdes_prtcl_valid(int serdes, u32 prtcl) in is_serdes_prtcl_valid() argument
[all …]
H A Dls1046a_serdes.c16 /* SerDes 1 */
40 /* SerDes 2 */
57 enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) in serdes_get_prtcl() argument
61 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) in serdes_get_prtcl()
64 ptr = serdes_cfg_tbl[serdes]; in serdes_get_prtcl()
74 int is_serdes_prtcl_valid(int serdes, u32 prtcl) in is_serdes_prtcl_valid() argument
79 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) in is_serdes_prtcl_valid()
82 ptr = serdes_cfg_tbl[serdes]; in is_serdes_prtcl_valid()
H A Dls1043a_serdes.c16 /* SerDes 1 */
44 enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) in serdes_get_prtcl() argument
48 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) in serdes_get_prtcl()
51 ptr = serdes_cfg_tbl[serdes]; in serdes_get_prtcl()
61 int is_serdes_prtcl_valid(int serdes, u32 prtcl) in is_serdes_prtcl_valid() argument
66 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) in is_serdes_prtcl_valid()
69 ptr = serdes_cfg_tbl[serdes]; in is_serdes_prtcl_valid()
H A Dls1012a_serdes.c32 enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) in serdes_get_prtcl() argument
36 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) in serdes_get_prtcl()
39 ptr = serdes_cfg_tbl[serdes]; in serdes_get_prtcl()
49 int is_serdes_prtcl_valid(int serdes, u32 prtcl) in is_serdes_prtcl_valid() argument
54 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) in is_serdes_prtcl_valid()
57 ptr = serdes_cfg_tbl[serdes]; in is_serdes_prtcl_valid()
/openbmc/u-boot/arch/arm/include/asm/ti-common/
H A Dkeystone_serdes.h3 * Texas Instruments Keystone SerDes driver
12 /* SERDES Reference clock */
21 /* SERDES Lane Baud Rate */
31 /* SERDES Lane Rate Mode */
38 /* SERDES PHY TYPE */
41 SERDES_PHY_PCSR, /* XGE SERDES */
52 int ks2_serdes_init(u32 base, struct ks2_serdes *serdes, u32 num_lanes);
/openbmc/u-boot/arch/powerpc/cpu/mpc85xx/
H A Dfsl_corenet_serdes.c19 * The work-arounds for erratum SERDES8 and SERDES-A001 are linked together.
134 /* Is serdes enabled at all? */ in is_serdes_configured()
157 * Returns the SERDES lane (0..SRDS_MAX_LANES-1) that routes to the given
158 * device. This depends on the current SERDES protocol, as defined in the RCW.
160 * Returns a negative error code if SERDES is disabled or the given device is
161 * not supported in the current SERDES protocol.
170 /* Is serdes enabled at all? */ in serdes_get_first_lane()
181 * Returns the SERDES bank (1, 2, or 3) that a given device is on for a given
182 * SERDES protocol.
185 * given SERDES protocol.
[all …]
/openbmc/u-boot/arch/arm/mach-mvebu/serdes/a38x/
H A Dhigh_speed_env_spec-38x.c40 printf("hws_serdes_seq_init: Error: Serdes initialization fail\n"); in hws_serdes_seq_init()
74 printf("%s: Device ID Error, using 4 SerDes lanes\n", in hws_serdes_get_max_lane()
121 * DESCRIPTION: Get the mapping of Serdes Selector values according to the
122 * Serdes revision number
123 * INPUT: serdes_num - Serdes number
124 * serdes_type - Serdes type
127 * Mapping of Serdes Selector values
147 * For 6810, there are 5 Serdes and Serdes Num 4 doesn't in hws_get_physical_serdes_num()
148 * exist. Instead Serdes Num 5 is connected. in hws_get_physical_serdes_num()
H A Dhigh_speed_env_spec.h20 /* Serdes revision */
21 /* Serdes revision 1.2 (for A38x-Z1) */
23 /* Serdes revision 2.1 (for A39x-Z1, A38x-A0) */
32 /* Serdes lane types */
56 /* Serdes baud rates */
69 /* Serdes modes */
89 /* Serdes ref clock options */
97 /* Serdes sequences */
/openbmc/u-boot/drivers/misc/
H A Dmpc83xx_serdes.h8 * enum srdscr0_mask - Bit masks for SRDSCR0 (SerDes Control Register 0)
33 * enum srdscr1_mask - Bit masks for SRDSCR1 (SerDes Control Register 1)
41 * enum srdscr2_mask - Bit masks for SRDSCR2 (SerDes Control Register 2)
89 * enum srdscr3_mask - Bit masks for SRDSCR3 (SerDes Control Register 3)
141 * enum srdscr4_mask - Bit masks for SRDSCR4 (SerDes Control Register 4)
193 * enum srdsrstctl_mask - Bit masks for SRDSRSTCTL (SerDes Reset Control Register)
205 * struct mpc83xx_serdes_regs - Register map of the SerDes controller
206 * @srdscr0: SerDes Control Register 0
207 * @srdscr1: SerDes Control Register 1
208 * @srdscr2: SerDes Control Register 2
[all …]
H A Dmpc83xx_serdes.c6 * base on the MPC83xx serdes initialization, which is
20 * struct mpc83xx_serdes_priv - Private structure for MPC83xx serdes
22 * @rfcks: Variable to keep the serdes reference clock selection set during
31 * setup_sata() - Configure the SerDes device to SATA mode
66 * setup_pex() - Configure the SerDes device to PCI Express mode
95 * setup_sgmii() - Configure the SerDes device to SGMII mode
126 switch (dev_read_u32_default(dev, "serdes-clk", -1)) { in mpc83xx_serdes_probe()
137 debug("%s: Could not read serdes clock value\n", dev->name); in mpc83xx_serdes_probe()
175 { .compatible = "fsl,mpc83xx-serdes" },
/openbmc/linux/arch/arm/boot/dts/microchip/
H A Dlan966x-pcb8290.dts11 #include "dt-bindings/phy/phy-lan966x-serdes.h"
120 phys = <&serdes 0 SERDES6G(1)>;
128 phys = <&serdes 1 SERDES6G(1)>;
136 phys = <&serdes 2 SERDES6G(1)>;
144 phys = <&serdes 3 SERDES6G(1)>;
152 phys = <&serdes 4 SERDES6G(2)>;
160 phys = <&serdes 5 SERDES6G(2)>;
168 phys = <&serdes 6 SERDES6G(2)>;
176 phys = <&serdes 7 SERDES6G(2)>;
180 &serdes {
/openbmc/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qmp-pcie-msm8996.c174 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
203 * @serdes: iomapped memory space for phy's serdes (i.e. PLL)
215 void __iomem *serdes; member
340 void __iomem *serdes = qphy->serdes; in qmp_pcie_msm8996_serdes_init() local
347 qmp_pcie_msm8996_configure(serdes, serdes_tbl, serdes_tbl_num); in qmp_pcie_msm8996_serdes_init()
349 qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET); in qmp_pcie_msm8996_serdes_init()
350 qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL], in qmp_pcie_msm8996_serdes_init()
353 status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS]; in qmp_pcie_msm8996_serdes_init()
369 void __iomem *serdes = qphy->serdes; in qmp_pcie_msm8996_com_init() local
400 qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL], in qmp_pcie_msm8996_com_init()
[all …]
/openbmc/linux/drivers/phy/mscc/
H A Dphy-ocelot-serdes.c3 * SerDes PHY driver for Microsemi Ocelot
19 #include <dt-bindings/phy/phy-ocelot-serdes.h>
60 static int serdes_init_s6g(struct regmap *regmap, u8 serdes, int mode) in serdes_init_s6g() argument
89 ret = serdes_update_mcb_s6g(regmap, serdes); in serdes_init_s6g()
146 ret = serdes_commit_mcb_s6g(regmap, serdes); in serdes_init_s6g()
222 ret = serdes_commit_mcb_s6g(regmap, serdes); in serdes_init_s6g()
230 ret = serdes_commit_mcb_s6g(regmap, serdes); in serdes_init_s6g()
244 ret = serdes_commit_mcb_s6g(regmap, serdes); in serdes_init_s6g()
292 static int serdes_init_s1g(struct regmap *regmap, u8 serdes) in serdes_init_s1g() argument
296 ret = serdes_update_mcb_s1g(regmap, serdes); in serdes_init_s1g()
[all …]

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