Searched full:set0 (Results 1 – 10 of 10) sorted by relevance
191 (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + SET0); in ipi_set0_regs_init()193 (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + SET0); in ipi_set0_regs_init()195 (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + SET0); in ipi_set0_regs_init()197 (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + SET0); in ipi_set0_regs_init()199 (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + SET0); in ipi_set0_regs_init()201 (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + SET0); in ipi_set0_regs_init()203 (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + SET0); in ipi_set0_regs_init()205 (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + SET0); in ipi_set0_regs_init()207 (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + SET0); in ipi_set0_regs_init()209 (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + SET0); in ipi_set0_regs_init()[all …]
23 #define SET0 0x08 macro
40 (MSI SET0) (MSI SET1) ... (MSI SET7)
441 u32 set0; member451 .set0 = 0,461 .set0 = (2 << A2W_PLLH_KA_SHIFT) | (2 << A2W_PLLH_KI_LOW_SHIFT),708 ana[0] |= data->ana->set0; in bcm2835_pll_set_rate()
358 * CPLD firmware maps SET0, SET1 and SET2
679 * [set0] | 0 | 1 | 2 | 3 | | 0 | 1 |
461 /* Pull the GPIO low to select SET0 register, while we program SET1 */ in do_scale_vcore()
1027 "can't disable set0/set1 interrupts\n"); in msa311_chip_init()
2545 "set0", "set1", "set2", "set3", in bttv_risc_decode()
4195 BNX2X_ERR("FATAL HW block attention set0 0x%x\n", in bnx2x_attn_int_deasserted0()