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Searched full:serr (Results 1 – 25 of 27) sorted by relevance

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/openbmc/ipmitool/contrib/
H A Doem_ibm_sel_map88 …s Register (LSB)","Status Register (MSB)","DevFun Number","0x00","Unknown SERR/PERR detected on PC…
89 …","Status Register (LSB)","Status Register (MSB)","DevFun Number","0x00","SERR: Address of special…
91 …","Status Register (LSB)","Status Register (MSB)","DevFun Number","0x00","SERR: Received target pa…
93 …"Status Register (LSB)","Status Register (MSB)","DevFun Number","0x00","SERR: Device signaled SERR"
95 …","Status Register (LSB)","Status Register (MSB)","DevFun Number","0x00","SERR: Signaled Target Ab…
97 …","Status Register (LSB)","Status Register (MSB)","DevFun Number","0x00","SERR: Received Master Ab…
99 …","Status Register (LSB)","Status Register (MSB)","DevFun Number","0x00","SERR: Split Completion D…
101 …","Status Register (LSB)","Status Register (MSB)","DevFun Number","0x00","SERR: Unexpected Split C…
103 …","Status Register (LSB)","Status Register (MSB)","DevFun Number","0x00","SERR: Received split com…
104 …","Status Register (LSB)","Status Register (MSB)","DevFun Number","0x00","SERR: PCI-PCI bridge sec…
[all …]
/openbmc/qemu/io/
H A Dchannel-socket.c744 struct sock_extended_err *serr; in qio_channel_socket_flush() local
746 char control[CMSG_SPACE(sizeof(*serr))]; in qio_channel_socket_flush()
785 serr = (void *) CMSG_DATA(cm); in qio_channel_socket_flush()
786 if (serr->ee_errno != SO_EE_ORIGIN_NONE) { in qio_channel_socket_flush()
787 error_setg_errno(errp, serr->ee_errno, in qio_channel_socket_flush()
791 if (serr->ee_origin != SO_EE_ORIGIN_ZEROCOPY) { in qio_channel_socket_flush()
792 error_setg_errno(errp, serr->ee_origin, in qio_channel_socket_flush()
796 if (serr->ee_data < serr->ee_info) { in qio_channel_socket_flush()
797 error_setg_errno(errp, serr->ee_origin, in qio_channel_socket_flush()
803 sioc->zero_copy_sent += serr->ee_data - serr->ee_info + 1; in qio_channel_socket_flush()
[all …]
/openbmc/openbmc/poky/scripts/lib/wic/
H A Dmisc.py70 serr = subprocess.STDOUT
74 stderr=serr, shell=shell)
75 sout, serr = process.communicate()
77 out = ''.join([out.decode('utf-8') for out in [sout, serr] if out])
/openbmc/phosphor-dbus-interfaces/yaml/xyz/openbmc_project/Chassis/Control/
H A DNMISource.interface.yaml38 Via PCI bus error(PERR & SERR).
/openbmc/phosphor-dbus-interfaces/yaml/com/intel/Control/
H A DNMISource.interface.yaml40 Via PCI SERR PERR.
/openbmc/u-boot/drivers/ata/
H A Ddwc_ahsata.c37 u32 serr; member
222 /* Wait for COMINIT bit 26 (DIAG_X) in SERR */ in ahci_host_init()
224 while (!(readl(&port_mmio->serr) | SATA_PORT_SERR_DIAG_X) in ahci_host_init()
233 * For each implemented Port, clear the P#SERR in ahci_host_init()
237 tmp = readl(&port_mmio->serr); in ahci_host_init()
238 debug("P#SERR 0x%x\n", in ahci_host_init()
240 writel(tmp, &port_mmio->serr); in ahci_host_init()
/openbmc/qemu/hw/ide/
H A Dich.c25 …* Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- Fast…
26 …* Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR…
/openbmc/u-boot/arch/m68k/include/asm/
H A Dm547x_8x.h338 #define PCI_SCR_S (0x00000100) /* SERR enable */
366 #define PCI_GSCR_SE (0x10000000) /* SERR detected */
370 #define PCI_GSCR_SEE (0x00001000) /* SERR detected interrupt enable */
H A Dm5445x.h810 #define PCI_SCR_S (0x00000100) /* SERR enable */
842 #define PCI_GSCR_SE (0x10000000) /* SERR detected */
846 #define PCI_GSCR_SEE (0x00001000) /* SERR detected interrupt enable */
/openbmc/qemu/include/hw/pci/
H A Dpci_bridge.h162 #define PCI_BRIDGE_CTL_DISCARD_SERR 0x800 /* Discard timer SERR# enable */
H A Dpci.h208 /* command register SERR bit enabled - unused since QEMU v5.0 */
/openbmc/qemu/hw/pci/
H A Dshpc.c14 /* TODO: handle SERR and wakeups */
106 /* Bits below are used for Serr/Int disable only */
H A Dpcie_aer.c214 * Bit 8 SERR# Enable in pcie_aer_msg_alldev()
/openbmc/u-boot/include/
H A Dpci.h32 #define PCI_COMMAND_SERR 0x100 /* Enable SERR */
48 #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
268 #define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
/openbmc/qemu/include/standard-headers/linux/
H A Dpci_regs.h49 #define PCI_COMMAND_SERR 0x100 /* Enable SERR */
68 #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
163 #define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
/openbmc/u-boot/arch/x86/cpu/ivybridge/
H A Dlpc.c183 reg8 |= (1 << 2); /* PCI SERR# Disable for now */ in pch_power_options()
/openbmc/u-boot/arch/x86/cpu/broadwell/
H A Dpch.c92 /* Setup NMI on errors, disable SERR */ in pch_misc_init()
/openbmc/qemu/pc-bios/dtb/
H A Dcanyonlands.dts161 /*SERR*/ 0x3 0x4
/openbmc/bmcweb/redfish-core/include/registries/
H A Dopenbmc.json528 "Description": "Indicates a Legacy PCI SERR.",
529 "Message": "Legacy PCI SERR. Bus=%1 Device=%2 Function=%3.",
H A Dopenbmc_message_registry.hpp742 "Indicates a Legacy PCI SERR.",
743 "Legacy PCI SERR. Bus=%1 Device=%2 Function=%3.",
/openbmc/qemu/hw/audio/
H A Des1370.c105 #define CTRL_SERR_DIS 0x00000001 /* 1 = disable PCI SERR signal */
/openbmc/pldm/pldmtool/
H A Dpldm_platform_cmd.cpp555 {PLDM_STATE_SET_PCI_SERR_REQUESTED, "PCI SERR Requested "},
556 {PLDM_STATE_SET_PCI_SERR_RECEIVED, "PCI SERR Received"},
/openbmc/ipmitool/include/ipmitool/
H A Dipmi_sel.h483 { 0x13, 0x05, 0xff, IPMI_EVENT_CLASS_DISCRETE, "Critical Interrupt", "PCI SERR" },
/openbmc/fb-ipmi-oem/src/
H A Dselcommands.cpp435 errLog = "PCI SERR" + tmp1.str(); in logPcieErr()
/openbmc/qemu/tests/qtest/
H A Dahci-test.c746 /* (12) SERR / SCR1: SError */ in ahci_test_port_spec()

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