| /openbmc/linux/arch/arm/boot/dts/rockchip/ |
| H A D | rk3288-veyron-sdmmc.dtsi | 3 * Google Veyron (and derivatives) fragment for sdmmc cards
10 mmc1 = &sdmmc;
19 sdmmc {
21 * We run sdmmc at max speed; bump up drive strength.
24 sdmmc_bus4: sdmmc-bus4 {
31 sdmmc_clk: sdmmc-clk {
35 sdmmc_cmd: sdmmc-cmd {
45 sdmmc_cd_disabled: sdmmc-cd-disabled {
50 sdmmc_cd_pin: sdmmc-cd-pin {
80 &sdmmc {
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| H A D | rk3288-phycore-rdk.dts | 175 sdmmc {
180 sdmmc_bus4: sdmmc-bus4 {
187 sdmmc_clk: sdmmc-clk {
191 sdmmc_cmd: sdmmc-cmd {
195 sdmmc_pwr: sdmmc-pwr {
223 &sdmmc {
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| H A D | rk3288-veyron-mighty.dts | 20 &sdmmc {
29 sdmmc {
30 sdmmc_wp_pin: sdmmc-wp-pin {
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| H A D | rk3288-evb.dtsi | 170 vcc_sd: sdmmc-regulator {
224 &sdmmc {
339 sdmmc {
344 sdmmc_bus4: sdmmc-bus4 {
351 sdmmc_clk: sdmmc-clk {
355 sdmmc_cmd: sdmmc-cmd {
359 sdmmc_pwr: sdmmc-pwr {
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| H A D | rk3288-firefly-reload.dts | 110 vcc_sd: sdmmc-regulator {
241 &sdmmc {
346 sdmmc {
351 sdmmc_bus4: sdmmc-bus4 {
358 sdmmc_clk: sdmmc-clk {
362 sdmmc_cmd: sdmmc-cmd {
366 sdmmc_pwr: sdmmc-pwr {
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| H A D | rk3288-miqi.dts | 61 vcc_sd: sdmmc-regulator {
341 sdmmc {
346 sdmmc_bus4: sdmmc-bus4 {
353 sdmmc_clk: sdmmc-clk {
357 sdmmc_cmd: sdmmc-cmd {
361 sdmmc_pwr: sdmmc-pwr {
378 &sdmmc {
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| H A D | rk3288-veyron-pinky.dts | 107 sdmmc {
108 sdmmc_wp_pin: sdmmc-wp-pin {
127 &sdmmc {
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| H A D | rk3288-tinker.dtsi | 97 vcc_sd: sdmmc-regulator {
407 sdmmc {
408 sdmmc_bus4: sdmmc-bus4 {
415 sdmmc_clk: sdmmc-clk {
419 sdmmc_cmd: sdmmc-cmd {
423 sdmmc_pwr: sdmmc-pwr {
455 &sdmmc {
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| H A D | rk3288-firefly.dtsi | 91 vcc_sd: sdmmc-regulator {
440 sdmmc {
445 sdmmc_bus4: sdmmc-bus4 {
452 sdmmc_clk: sdmmc-clk {
456 sdmmc_cmd: sdmmc-cmd {
460 sdmmc_pwr: sdmmc-pwr {
498 &sdmmc {
|
| /openbmc/u-boot/drivers/mmc/ |
| H A D | stm32_sdmmc2.c | 39 /* SDMMC REGISTERS OFFSET */
40 #define SDMMC_POWER 0x00 /* SDMMC power control */
41 #define SDMMC_CLKCR 0x04 /* SDMMC clock control */
42 #define SDMMC_ARG 0x08 /* SDMMC argument */
43 #define SDMMC_CMD 0x0C /* SDMMC command */
44 #define SDMMC_RESP1 0x14 /* SDMMC response 1 */
45 #define SDMMC_RESP2 0x18 /* SDMMC response 2 */
46 #define SDMMC_RESP3 0x1C /* SDMMC response 3 */
47 #define SDMMC_RESP4 0x20 /* SDMMC response 4 */
48 #define SDMMC_DTIMER 0x24 /* SDMMC data timer */
[all …]
|
| /openbmc/linux/Documentation/devicetree/bindings/mmc/ |
| H A D | nvidia,tegra20-sdhci.yaml | 228 - const: sdmmc-3v3
230 - const: sdmmc-1v8
232 - const: sdmmc-3v3-drv
234 - const: sdmmc-1v8-drv
237 - const: sdmmc-3v3-drv
239 - const: sdmmc-1v8-drv
242 - const: sdmmc-1v8-drv
257 - const: sdmmc-3v3
259 - const: sdmmc-1v8
296 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",
[all …]
|
| H A D | synopsys-dw-mshc.yaml | 43 - description: register offset that controls the SDMMC clock phase
47 that contains the SDMMC clock-phase control register. The first value is
49 SDMMC clock phase register, and the 3rd value is the bit shift for the
|
| /openbmc/linux/arch/arm64/boot/dts/rockchip/ |
| H A D | rk3368-orion-r68-meta.dts | 15 mmc0 = &sdmmc;
272 sdmmc {
273 sdmmc_clk: sdmmc-clk {
277 sdmmc_cmd: sdmmc-cmd {
281 sdmmc_cd: sdmmc-cd {
285 sdmmc_bus1: sdmmc-bus1 {
289 sdmmc_bus4: sdmmc-bus4 {
309 &sdmmc {
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| H A D | rk3368-lion-haikou.dts | 14 mmc1 = &sdmmc;
71 &sdmmc {
131 sdmmc {
132 sdmmc_cd_pin: sdmmc-cd-pin {
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| H A D | rk3399-gru.dtsi | 14 mmc0 = &sdmmc;
474 sdmmc-supply = <&ppvar_sd_card_io>; /* SDMMC0_VDD; 4b */
537 &sdmmc {
546 * configured as SDMMC and not JTAG.
773 sdmmc {
775 * We run sdmmc at max speed; bump up drive strength.
778 sdmmc_bus4: sdmmc-bus4 {
786 sdmmc_clk: sdmmc-clk {
791 sdmmc_cmd: sdmmc-cmd {
805 sdmmc_cd: sdmmc-cd {
[all …]
|
| H A D | rk3399-rock960.dtsi | 15 mmc1 = &sdmmc;
392 sdmmc-supply = <&vcc_sd>; /* sdmmc_gpio4b_ms */
431 sdmmc {
432 sdmmc_bus1: sdmmc-bus1 {
437 sdmmc_bus4: sdmmc-bus4 {
445 sdmmc_clk: sdmmc-clk {
450 sdmmc_cmd: sdmmc-cmd {
549 &sdmmc {
|
| /openbmc/linux/drivers/pinctrl/ |
| H A D | pinctrl-lpc18xx.c | 163 [FUNC_SDMMC] = "sdmmc",
245 LPC_P(1,3, GPIO, CTOUT, SGPIO, EMC, USB0, SSP1, R, SDMMC, 0, ND);
246 LPC_P(1,4, GPIO, CTOUT, SGPIO, EMC, USB0, SSP1, R, SDMMC, 0, ND);
247 LPC_P(1,5, GPIO, CTOUT, R, EMC, USB0, SSP1, SGPIO, SDMMC, 0, ND);
248 LPC_P(1,6, GPIO, CTIN, R, EMC, R, R, SGPIO, SDMMC, 0, ND);
250 LPC_P(1,8, GPIO, UART1, CTOUT, EMC, R, R, R, SDMMC, 0, ND);
251 LPC_P(1,9, GPIO, UART1, CTOUT, EMC, R, R, R, SDMMC, 0, ND);
252 LPC_P(1,10, GPIO, UART1, CTOUT, EMC, R, R, R, SDMMC, 0, ND);
253 LPC_P(1,11, GPIO, UART1, CTOUT, EMC, R, R, R, SDMMC, 0, ND);
254 LPC_P(1,12, GPIO, UART1, R, EMC, TIMER0, R, SGPIO, SDMMC, 0, ND);
[all …]
|
| /openbmc/u-boot/arch/arm/dts/ |
| H A D | rk3288-miqi.dtsi | 71 vcc_sd: sdmmc-regulator {
330 sdmmc {
335 sdmmc_bus4: sdmmc-bus4 {
342 sdmmc_clk: sdmmc-clk {
346 sdmmc_cmd: sdmmc-cmd {
350 sdmmc_pwr: sdmmc-pwr {
367 &sdmmc {
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| H A D | rk3288-phycore-rdk.dts | 205 sdmmc {
210 sdmmc_bus4: sdmmc-bus4 {
217 sdmmc_clk: sdmmc-clk {
221 sdmmc_cmd: sdmmc-cmd {
225 sdmmc_pwr: sdmmc-pwr {
253 &sdmmc {
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| H A D | rk3399-rock960.dtsi | 350 sdmmc-supply = <&vcc_sd>; /* sdmmc_gpio4b_ms */
373 sdmmc {
374 sdmmc_bus1: sdmmc-bus1 {
379 sdmmc_bus4: sdmmc-bus4 {
387 sdmmc_clk: sdmmc-clk {
392 sdmmc_cmd: sdmmc-cmd {
432 &sdmmc {
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| H A D | rk3288-rock2-square.dts | 86 vcc_sd: sdmmc-regulator {
98 &sdmmc {
161 sdmmc {
162 sdmmc_pwr: sdmmc-pwr {
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| H A D | rk3288-tinker.dtsi | 100 vcc_sd: sdmmc-regulator {
129 &sdmmc {
497 sdmmc {
502 sdmmc_bus4: sdmmc-bus4 {
509 sdmmc_clk: sdmmc-clk {
513 sdmmc_cmd: sdmmc-cmd {
517 sdmmc_pwr: sdmmc-pwr {
|
| H A D | rk3288-fennec.dtsi | 81 &sdmmc {
348 sdmmc {
349 sdmmc_bus4: sdmmc-bus4 {
356 sdmmc_clk: sdmmc-clk {
360 sdmmc_cmd: sdmmc-cmd {
364 sdmmc_pwr: sdmmc-pwr {
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| H A D | rk3288-veyron.dtsi | 288 &sdmmc {
629 /* Add this for sdmmc pins to SD card */
765 sdmmc {
767 * We run sdmmc at max speed; bump up drive strength.
770 sdmmc_bus4: sdmmc-bus4 {
777 sdmmc_clk: sdmmc-clk {
781 sdmmc_cmd: sdmmc-cmd {
791 sdmmc_cd_disabled: sdmmc-cd-disabled {
796 sdmmc_cd_gpio: sdmmc-cd-gpio {
834 &sdmmc {
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| /openbmc/linux/Documentation/devicetree/bindings/edac/ |
| H A D | socfpga-eccmgr.txt | 125 SDMMC FIFO ECC
127 - compatible : Should be "altr,socfpga-sdmmc-ecc"
224 sdmmc-ecc@ff8c2c00 {
225 compatible = "altr,socfpga-sdmmc-ecc";
296 SDMMC FIFO ECC
298 - compatible : Should be "altr,socfpga-s10-sdmmc-ecc"
376 sdmmc-ecc@ff8c8c00 {
377 compatible = "altr,socfpga-s10-sdmmc-ecc";
|