Lines Matching full:sdmmc
39 /* SDMMC REGISTERS OFFSET */
40 #define SDMMC_POWER 0x00 /* SDMMC power control */
41 #define SDMMC_CLKCR 0x04 /* SDMMC clock control */
42 #define SDMMC_ARG 0x08 /* SDMMC argument */
43 #define SDMMC_CMD 0x0C /* SDMMC command */
44 #define SDMMC_RESP1 0x14 /* SDMMC response 1 */
45 #define SDMMC_RESP2 0x18 /* SDMMC response 2 */
46 #define SDMMC_RESP3 0x1C /* SDMMC response 3 */
47 #define SDMMC_RESP4 0x20 /* SDMMC response 4 */
48 #define SDMMC_DTIMER 0x24 /* SDMMC data timer */
49 #define SDMMC_DLEN 0x28 /* SDMMC data length */
50 #define SDMMC_DCTRL 0x2C /* SDMMC data control */
51 #define SDMMC_DCOUNT 0x30 /* SDMMC data counter */
52 #define SDMMC_STA 0x34 /* SDMMC status */
53 #define SDMMC_ICR 0x38 /* SDMMC interrupt clear */
54 #define SDMMC_MASK 0x3C /* SDMMC mask */
55 #define SDMMC_IDMACTRL 0x50 /* SDMMC DMA control */
56 #define SDMMC_IDMABASE0 0x58 /* SDMMC DMA buffer 0 base address */
200 /* Configure the SDMMC DPSM (Data Path State Machine) */ in stm32_sdmmc2_start_data()
212 /* Set the SDMMC Data TimeOut value */ in stm32_sdmmc2_start_data()
215 /* Set the SDMMC DataLength value */ in stm32_sdmmc2_start_data()
218 /* Write to SDMMC DCTRL */ in stm32_sdmmc2_start_data()
257 /* Set SDMMC argument value */ in stm32_sdmmc2_start_cmd()
260 /* Set SDMMC command parameters */ in stm32_sdmmc2_start_cmd()
447 * Reset the SDMMC with the RCC.SDMMCxRST register bit.
448 * This will reset the SDMMC to the reset state and the CPSM and DPSM
449 * to the Idle state. SDMMC is disabled, Signals Hiz.
458 /* init the needed SDMMC register after reset */ in stm32_sdmmc2_reset()
463 * Set the SDMMC in power-cycle state.
480 * set the SDMMC state Power-on: the card is clocked
481 * manage the SDMMC state control:
508 /* After the 1ms delay set the SDMMC to power-on */ in stm32_sdmmc2_pwron()
513 /* during the first 74 SDMMC_CK cycles the SDMMC is still disabled. */ in stm32_sdmmc2_pwron()
634 /* SDMMC init */ in stm32_sdmmc2_probe()