| /openbmc/u-boot/drivers/clk/rockchip/ |
| H A D | clk_rk3368.c | 365 * The entries are numbered relative to their offset from SCLK_SPI0.
384 case SCLK_SPI0 ... SCLK_SPI2: in rk3368_spi_get_clk()
385 spiclk = &spi_clkregs[clk_id - SCLK_SPI0]; in rk3368_spi_get_clk()
409 case SCLK_SPI0 ... SCLK_SPI2: in rk3368_spi_set_clk()
410 spiclk = &spi_clkregs[clk_id - SCLK_SPI0]; in rk3368_spi_set_clk()
465 case SCLK_SPI0 ... SCLK_SPI2: in rk3368_clk_get_rate()
491 case SCLK_SPI0 ... SCLK_SPI2: in rk3368_clk_set_rate()
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| H A D | clk_rk3188.c | 330 case SCLK_SPI0: in rockchip_spi_get_clk()
352 case SCLK_SPI0: in rockchip_spi_set_clk()
477 case SCLK_SPI0: in rk3188_clk_get_rate()
519 case SCLK_SPI0: in rk3188_clk_set_rate()
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| H A D | clk_rk3399.c | 606 * The entries are numbered relative to their offset from SCLK_SPI0.
635 case SCLK_SPI0 ... SCLK_SPI5: in rk3399_spi_get_clk()
636 spiclk = &spi_clkregs[clk_id - SCLK_SPI0]; in rk3399_spi_get_clk()
661 spiclk = &spi_clkregs[clk_id - SCLK_SPI0]; in rk3399_spi_set_clk()
911 case SCLK_SPI0...SCLK_SPI5: in rk3399_clk_get_rate()
983 case SCLK_SPI0...SCLK_SPI5: in rk3399_clk_set_rate()
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| H A D | clk_rk3288.c | 661 case SCLK_SPI0: in rockchip_spi_get_clk()
693 case SCLK_SPI0: in rockchip_spi_set_clk()
761 case SCLK_SPI0: in rk3288_clk_get_rate()
811 case SCLK_SPI0: in rk3288_clk_set_rate()
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| /openbmc/linux/Documentation/devicetree/bindings/spi/ |
| H A D | spi-rockchip.yaml | 106 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
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| /openbmc/linux/include/dt-bindings/clock/ |
| H A D | samsung,s3c64xx-clock.h | 102 #define SCLK_SPI0 90 macro
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| H A D | exynos7-clk.h | 109 #define SCLK_SPI0 17 macro
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| H A D | s5pv210.h | 193 #define SCLK_SPI0 171 macro
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| H A D | rk3188-cru-common.h | 25 #define SCLK_SPI0 69 macro
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| H A D | rk3228-cru.h | 18 #define SCLK_SPI0 65 macro
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| H A D | rk3128-cru.h | 20 #define SCLK_SPI0 65 macro
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| H A D | rv1108-cru.h | 17 #define SCLK_SPI0 65 macro
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| H A D | px30-cru.h | 38 #define SCLK_SPI0 36 macro
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| H A D | rk3368-cru.h | 21 #define SCLK_SPI0 65 macro
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| H A D | rk3308-cru.h | 31 #define SCLK_SPI0 27 macro
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| H A D | rk3288-cru.h | 20 #define SCLK_SPI0 65 macro
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| /openbmc/u-boot/include/dt-bindings/clock/ |
| H A D | exynos7420-clk.h | 112 #define SCLK_SPI0 17 macro
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| H A D | rk3228-cru.h | 17 #define SCLK_SPI0 65 macro
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| H A D | rk3188-cru-common.h | 25 #define SCLK_SPI0 69 macro
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| H A D | rv1108-cru.h | 17 #define SCLK_SPI0 65 macro
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| H A D | rk3368-cru.h | 30 #define SCLK_SPI0 65 macro
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| H A D | rk3288-cru.h | 17 #define SCLK_SPI0 65 macro
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| /openbmc/linux/drivers/clk/samsung/ |
| H A D | clk-s3c64xx.c | 256 GATE_SCLK(SCLK_SPI0, "sclk_spi0", "dout_spi0", SCLK_GATE, 20),
357 ALIAS(SCLK_SPI0, "s3c6410-spi.0", "spi_busclk2"),
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| H A D | clk-exynos7.c | 352 GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_sclk_spi0",
708 PNAME(mout_sclk_spi0_user_p) = { "fin_pll", "sclk_spi0" };
784 GATE(SCLK_SPI0, "sclk_spi0_user", "mout_sclk_spi0_user",
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| /openbmc/linux/Documentation/devicetree/bindings/clock/ |
| H A D | samsung,exynos7-clock.yaml | 155 - const: sclk_spi0
|