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/openbmc/openbmc/meta-openembedded/meta-filesystems/recipes-utils/btrfsmaintenance/files/
H A D0001-change-sysconfig-path-to-etc-default.patch15 btrfsmaintenance-refresh.path | 4 ++--
16 btrfsmaintenance-refresh.service | 2 +-
19 diff --git a/btrfsmaintenance-refresh.path b/btrfsmaintenance-refresh.path
21 --- a/btrfsmaintenance-refresh.path
22 +++ b/btrfsmaintenance-refresh.path
34 diff --git a/btrfsmaintenance-refresh.service b/btrfsmaintenance-refresh.service
36 --- a/btrfsmaintenance-refresh.service
37 +++ b/btrfsmaintenance-refresh.service
44 ExecStart=/usr/share/btrfsmaintenance/btrfsmaintenance-refresh-cron.sh systemd-timer
H A D0002-add-WantedBy-directive-to-btrfsmaintenance-refresh.s.patch4 Subject: [PATCH] add WantedBy directive to btrfsmaintenance-refresh.service
15 btrfsmaintenance-refresh.service | 4 ++++
18 diff --git a/btrfsmaintenance-refresh.service b/btrfsmaintenance-refresh.service
20 --- a/btrfsmaintenance-refresh.service
21 +++ b/btrfsmaintenance-refresh.service
25 ExecStart=/usr/share/btrfsmaintenance/btrfsmaintenance-refresh-cron.sh systemd-timer
26 +ExecStart=systemctl disable btrfsmaintenance-refresh.service
/openbmc/u-boot/arch/arm/cpu/arm926ejs/lpc32xx/
H A Ddram.c31 /* Select maximum EMC Dynamic Memory Refresh Time */ in ddr_init()
32 writel(0x7FF, &emc->refresh); in ddr_init()
51 /* Dynamic refresh */ in ddr_init()
52 writel((((ck / dram->refresh) >> 4) & 0x7FF), &emc->refresh); in ddr_init()
59 /* Fast dynamic refresh for at least a few SDRAM ck cycles */ in ddr_init()
60 writel((((128) >> 4) & 0x7FF), &emc->refresh); in ddr_init()
62 /* set correct dynamic refresh timing */ in ddr_init()
63 writel((((ck / dram->refresh) >> 4) & 0x7FF), &emc->refresh); in ddr_init()
/openbmc/linux/arch/arm/mach-lpc32xx/
H A Dsuspend.S63 @ Setup self-refresh with support for manual exit of
64 @ self-refresh mode
70 @ Wait for self-refresh acknowledge, clocks to the DRAM device
71 @ will automatically stop on start of self-refresh
76 bne 3b @ Branch until self-refresh mode starts
113 @ Re-enter run mode with self-refresh flag cleared, but no DRAM
114 @ update yet. DRAM is still in self-refresh
122 @ Clear self-refresh mode
129 @ Wait for EMC to clear self-refresh mode
133 bne 5b @ Branch until self-refresh has exited
H A Dpm.c38 * DRAM refresh
39 * DRAM clocking and refresh are slightly different for systems with DDR
44 * and exit DRAM self-refresh modes must not be executed in DRAM. A small
51 * Places DRAMs in self-refresh mode
126 * Setup SDRAM self-refresh clock to automatically disable o in lpc32xx_pm_init()
127 * start of self-refresh. This only needs to be done once. in lpc32xx_pm_init()
/openbmc/linux/drivers/cpufreq/
H A Dsa1110-cpufreq.c40 u_short refresh; /* refresh time for array (us) */ member
57 .refresh = 64000,
66 .refresh = 64000,
75 .refresh = 64000,
83 .refresh = 64000,
92 .refresh = 64000,
101 .refresh = 64000,
110 .refresh = 64000,
196 * Set the SDRAM refresh rate.
205 * Update the refresh period. We do this such that we always refresh
[all …]
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Drockchip,rk3399-dmc.yaml69 Configure the SR_IDLE value. Defines the self-refresh idle period in
70 which memories are placed into self-refresh mode if bus is idle for
79 Defines the memory self-refresh and controller clock gating idle period.
80 Memories are placed into self-refresh mode and memory controller clock
89 Defines the self-refresh power down idle period in which memories are
90 placed into self-refresh power down mode if bus is idle for
100 self-refresh mode. The controller, pi, PHY and DRAM clock will be gated
293 Configure the SR_IDLE value in nanoseconds. Defines the self-refresh idle
294 period in which memories are placed into self-refresh mode if bus is idle
300 Defines the memory self-refresh and controller clock gating idle period in nanoseconds.
[all …]
/openbmc/linux/include/soc/at91/
H A Dsama7-ddr.h55 #define UDDRC_STAT_SELFREF_TYPE_DIS (0x0 << 4) /* SDRAM is not in Self-refresh */
56 #define UDDRC_STAT_SELFREF_TYPE_PHY (0x1 << 4) /* SDRAM is in Self-refresh, which was caused by PH…
57 …FREF_TYPE_SW (0x2 << 4) /* SDRAM is in Self-refresh, which was not caused solely under Automatic S…
58 …T_SELFREF_TYPE_AUTO (0x3 << 4) /* SDRAM is in Self-refresh, which was caused by Automatic Self-ref…
59 #define UDDRC_STAT_SELFREF_TYPE_MSK (0x3 << 4) /* Self-refresh type mask */
63 #define UDDRC_STAT_OPMODE_SELF_REFRESH (0x3 << 0) /* Self-refresh */
67 #define UDDRC_PWRCTL_SELFREF_EN (1 << 0) /* Automatic self-refresh */
68 #define UDDRC_PWRCTL_SELFREF_SW (1 << 5) /* Software self-refresh */
H A Dat91sam9_sdramc.h26 #define AT91_SDRAMC_TR 0x04 /* SDRAM Controller Refresh Timer Register */
27 #define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Counter */
54 #define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */
62 #define AT91_SDRAMC_PASR (7 << 4) /* Partial Array Self Refresh */
63 #define AT91_SDRAMC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */
74 #define AT91_SDRAMC_RES (1 << 0) /* Refresh Error Status */
/openbmc/webui-vue/src/layouts/
H A DAppLayout.vue7 @refresh="refresh"
47 this.$root.$on('refresh-application', () => this.refresh());
51 this.refresh();
56 refresh() {
65 // a component re-rendering and 'refresh' the view
/openbmc/linux/drivers/video/fbdev/core/
H A Dfbcvt.c38 u32 refresh; member
230 cvt->xres, cvt->yres, cvt->refresh); in fb_cvt_print_name()
262 mode->refresh = cvt->f_refresh; in fb_cvt_convert_to_mode()
281 * @mode: pointer to fb_videomode; xres, yres, refresh and vmode must be
288 * @mode is filled with computed values. If interlaced, the refresh field
311 cvt.refresh = mode->refresh; in fb_find_mode_cvt()
312 cvt.f_refresh = cvt.refresh; in fb_find_mode_cvt()
315 if (!cvt.xres || !cvt.yres || !cvt.refresh) { in fb_find_mode_cvt()
320 if (!(cvt.refresh == 50 || cvt.refresh == 60 || cvt.refresh == 70 || in fb_find_mode_cvt()
321 cvt.refresh == 85)) { in fb_find_mode_cvt()
[all …]
/openbmc/u-boot/board/freescale/m5249evb/
H A Dm5249evb.c45 * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=39 in dram_init()
51 * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=02 in dram_init()
57 * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=22 (562 bus clock cycles) in dram_init()
67 /* RE=0 (keep auto-refresh disabled while setting up registers) */ in dram_init()
78 /** Refresh Sequence **/ in dram_init()
79 mbar_writeLong(MCFSIM_DACR0, 0x0000b324); /* Enable the refresh bit, DACR0[RE] (bit 15) */ in dram_init()
80 udelay(0x7d0); /* Allow gobs of refresh cycles */ in dram_init()
/openbmc/linux/drivers/gpu/drm/
H A Ddrm_self_refresh_helper.c27 * framework to implement panel self refresh (SR) support. Drivers are
32 * (meaning it knows how to initiate self refresh on the panel).
140 * update the average entry/exit self refresh times on self refresh transitions.
142 * entering self refresh mode after activity.
179 * incompatible with self refresh exit and changes them. This is a bit
181 * another. However in order to keep self refresh entirely hidden from
184 * At the end, we queue up the self refresh entry work so we can enter PSR after
227 * drm_self_refresh_helper_init - Initializes self refresh helpers for a crtc
228 * @crtc: the crtc which supports self refresh supported displays
265 * drm_self_refresh_helper_cleanup - Cleans up self refresh helpers for a crtc
/openbmc/linux/tools/perf/pmu-events/arch/arm64/freescale/yitian710/sys/
H A Dali_drw.json171 "BriefDescription": "Rank0 enters self-refresh(SRE).",
178 "BriefDescription": "Rank1 enters self-refresh(SRE).",
185 "BriefDescription": "Rank2 enters self-refresh(SRE).",
192 "BriefDescription": "Rank3 enters self-refresh(SRE).",
227 "BriefDescription": "A cycle that Rank0 stays in self-refresh mode.",
234 "BriefDescription": "A cycle that Rank1 stays in self-refresh mode.",
241 "BriefDescription": "A cycle that Rank2 stays in self-refresh mode.",
248 "BriefDescription": "A cycle that Rank3 stays in self-refresh mode.",
255 "BriefDescription": "An auto-refresh(REF) command to DRAM.",
262 "BriefDescription": "A critical auto-refresh(REF) command to DRAM.",
[all …]
/openbmc/linux/arch/arm/mach-pxa/
H A Dsleep.S55 @ prepare SDRAM refresh settings
59 @ enable SDRAM self-refresh mode
96 @ prepare SDRAM refresh settings
100 @ enable SDRAM self-refresh mode
108 @ as possible to eliminate messing about with the refresh clock
160 @ external accesses after SDRAM is put in self-refresh mode
161 @ (see Errata 38 ...hangs when entering self-refresh mode)
166 @ put SDRAM into self-refresh
/openbmc/openbmc/meta-openembedded/meta-filesystems/recipes-utils/btrfsmaintenance/
H A Dbtrfsmaintenance_0.5.bb14 file://0002-add-WantedBy-directive-to-btrfsmaintenance-refresh.s.patch \
29 install -Dm0644 ${S}/btrfsmaintenance-refresh.path \
30 ${D}${systemd_system_unitdir}/btrfsmaintenance-refresh.path
56 btrfsmaintenance-refresh.service \
57 btrfsmaintenance-refresh.path \
/openbmc/linux/arch/arm/mach-socfpga/
H A Dself-refresh.S44 * return value: lower 16 bits: loop count going into self refresh
45 * upper 16 bits: loop count exiting self refresh
53 /* Enable self refresh: set sdr.ctrlgrp.lowpwreq.selfrshreq = 1 */
89 /* Disable self-refresh: set sdr.ctrlgrp.lowpwreq.selfrshreq = 0 */
109 * Shift loop count for exiting self refresh into upper 16 bits.
110 * Leave loop count for requesting self refresh in lower 16 bits.
/openbmc/u-boot/arch/arm/include/asm/arch-lpc32xx/
H A Demc.h18 u32 refresh; /* Configures dyn memory refresh operation */ member
23 u32 t_srex; /* Self-refresh exit time */
27 u32 t_rfc; /* Auto-refresh period */
28 u32 t_xsr; /* Exit self-refresh to active command time */
94 u32 refresh; member
/openbmc/qemu/authz/
H A Dlistfile.c135 if (!fauthz->refresh) { in qauthz_list_file_complete()
197 fauthz->refresh = value; in qauthz_list_file_prop_set_refresh()
207 return fauthz->refresh; in qauthz_list_file_prop_get_refresh()
233 object_class_property_add_bool(oc, "refresh", in qauthz_list_file_class_init()
248 authz->refresh = true; in qauthz_list_file_init()
255 bool refresh, in qauthz_list_file_new() argument
263 "refresh", refresh ? "yes" : "no", in qauthz_list_file_new()
/openbmc/u-boot/doc/device-tree-bindings/clock/
H A Drockchip,rk3288-dmc.txt23 …ck frequency high than sr-enable-freq,this driver should enable the automatic self refresh function
25 …refresh-cnt: Self Refresh idle period. Memories are placed into Self-Refresh mode if the NIF is id…
139 rockchip,auto-self-refresh-cnt = <0>;
/openbmc/linux/arch/sh/boards/mach-kfr2r09/
H A Dsdram.S3 * KFR2R09 sdram self/auto-refresh setup code
15 /* code to enter and leave self-refresh. must be self-contained.
21 /* DBSC: put memory in self-refresh mode */
37 /* DBSC: put memory in auto-refresh mode */
55 /* DBSC: re-initialize and put in auto-refresh */
/openbmc/qemu/include/authz/
H A Dlistfile.h52 * "refresh": true
57 * If 'refresh' is 'yes', inotify is used to monitor for changes
76 * filename=/etc/qemu/myvm-vnc.acl,refresh=on
84 bool refresh; member
94 bool refresh,
/openbmc/openbmc/meta-openembedded/meta-networking/recipes-support/tnftp/tnftp/
H A D0001-Add-casts-to-appease-conversions-between-wchar_t-and.patch6 Upstream-Status: Backport [http://cvsweb.netbsd.org/bsdweb.cgi/src/lib/libedit/refresh.c.diff?r1=1.…
10 libedit/refresh.c | 16 +++++++++-------
13 diff --git a/libedit/refresh.c b/libedit/refresh.c
15 --- a/libedit/refresh.c
16 +++ b/libedit/refresh.c
/openbmc/linux/drivers/cpuidle/
H A Dcpuidle-zynq.c9 * The cpu idle uses wait-for-interrupt and RAM self refresh in order
12 * #2 wait-for-interrupt and RAM self refresh
28 /* Add code for DDR self refresh start */ in zynq_enter_idle()
44 .desc = "WFI and RAM Self Refresh",
/openbmc/u-boot/arch/arm/mach-at91/include/mach/
H A Dat91sam9_sdramc.h55 #define AT91_SDRAMC_TR (ATMEL_BASE_SDRAMC + 0x04) /* SDRAM Controller Refresh Timer Register */
56 #define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Counter */
88 #define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */
97 #define AT91_SDRAMC_PASR (7 << 4) /* Partial Array Self Refresh */
98 #define AT91_SDRAMC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */
109 #define AT91_SDRAMC_RES (1 << 0) /* Refresh Error Status */

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