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/openbmc/qemu/hw/core/
H A Dloader.c149 /* Can only load an image into RAM or ROM */ in load_image_mr()
925 typedef struct Rom Rom; typedef
927 struct Rom { struct
949 QTAILQ_ENTRY(Rom) next; argument
953 static QTAILQ_HEAD(, Rom) roms = QTAILQ_HEAD_INITIALIZER(roms);
956 * rom->data can be heap-allocated or memory-mapped (e.g. when added with
959 static void rom_free_data(Rom *rom) in rom_free_data() argument
961 if (rom->mapped_file) { in rom_free_data()
962 g_mapped_file_unref(rom->mapped_file); in rom_free_data()
963 rom->mapped_file = NULL; in rom_free_data()
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/openbmc/qemu/roms/
H A DMakefile7 pxe-rom-e1000 efi-rom-e1000 : VID := 8086
8 pxe-rom-e1000 efi-rom-e1000 : DID := 100e
9 pxe-rom-e1000e efi-rom-e1000e : VID := 8086
10 pxe-rom-e1000e efi-rom-e1000e : DID := 10d3
11 pxe-rom-eepro100 efi-rom-eepro100 : VID := 8086
12 pxe-rom-eepro100 efi-rom-eepro100 : DID := 1209
13 pxe-rom-ne2k_pci efi-rom-ne2k_pci : VID := 1050
14 pxe-rom-ne2k_pci efi-rom-ne2k_pci : DID := 0940
15 pxe-rom-pcnet efi-rom-pcnet : VID := 1022
16 pxe-rom-pcnet efi-rom-pcnet : DID := 2000
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/openbmc/qemu/pc-bios/
H A Dmeson.build35 'qboot.rom',
50 'pxe-e1000.rom',
51 'pxe-eepro100.rom',
52 'pxe-ne2k_pci.rom',
53 'pxe-pcnet.rom',
54 'pxe-rtl8139.rom',
55 'pxe-virtio.rom',
56 'efi-e1000.rom',
57 'efi-eepro100.rom',
58 'efi-ne2k_pci.rom',
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H A DREADME24 Sources available at http://ipxe.org. Vendor:Device ID -> ROM mapping:
26 8086:100e -> pxe-e1000.rom
27 8086:1209 -> pxe-eepro100.rom
28 1050:0940 -> pxe-ne2k_pci.rom
29 1022:2000 -> pxe-pcnet.rom
30 10ec:8139 -> pxe-rtl8139.rom
31 1af4:1000 -> pxe-virtio.rom
86 - npcm{7xx,8xx}_bootrom.bin is a simplified, free (Apache 2.0) boot ROM for
92 - ast27x0_bootrom.bin is a simplified, free (Apache 2.0) boot ROM for
/openbmc/qemu/hw/xen/
H A Dxen_pt_load_rom.c12 * Scan the assigned devices for the devices that have an option ROM, and then
13 * load the corresponding ROM data to RAM. If an error occurs while loading an
14 * option ROM, we just ignore that option ROM and continue with the next one.
28 /* If loading ROM from file, pci handles it */ in pci_assign_dev_load_option_rom()
34 "/sys/bus/pci/devices/%04x:%02x:%02x.%01x/rom", in pci_assign_dev_load_option_rom()
37 /* Write "1" to the ROM file to enable it */ in pci_assign_dev_load_option_rom()
58 error_report("ROM BAR \"%s\" (%ld bytes) is too large for ROM size %u", in pci_assign_dev_load_option_rom()
66 snprintf(name, sizeof(name), "%s.rom", object_get_typename(owner)); in pci_assign_dev_load_option_rom()
67 memory_region_init_ram(&dev->rom, owner, name, dev->romsize, &error_abort); in pci_assign_dev_load_option_rom()
68 ptr = memory_region_get_ram_ptr(&dev->rom); in pci_assign_dev_load_option_rom()
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/openbmc/u-boot/board/synopsys/iot_devkit/
H A Du-boot.lds10 ROM : ORIGIN = ROM_BASE, LENGTH = ROM_SIZE
26 } > ROM
34 } > ROM
39 } > ROM
48 } > ROM
56 * copied from ROM to RAM in board_early_init_f().
63 } > RAM AT > ROM
/openbmc/u-boot/arch/xtensa/cpu/
H A Du-boot.lds17 * U-Boot resets from SYSROM and unpacks itself from a ROM store to RAM.
19 * above it for the ROM store into which the rest of U-Boot is packed.
20 * The ROM store also needs to be above any other vectors that are in ROM.
21 * If a core has its vectors near the top of ROM, this must be edited.
23 * Note that to run C code out of ROM, the processor would have to support
28 * other means (serial ROM, for example) or are initialized early (requiring
91 * On many Xtensa boards a region of RAM may be mapped to the ROM address
105 "U-Boot ROM image is too large. Check optimization level.")
/openbmc/qemu/backends/
H A Dhostmem-file.c36 OnOffAuto rom; member
60 switch (fb->rom) { in file_backend_memory_alloc()
62 /* Traditionally, opening the file readonly always resulted in ROM. */ in file_backend_memory_alloc()
63 fb->rom = fb->readonly ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF; in file_backend_memory_alloc()
67 error_setg(errp, "property 'rom' = 'on' is not supported with" in file_backend_memory_alloc()
74 error_setg(errp, "property 'rom' = 'off' is incompatible with" in file_backend_memory_alloc()
87 ram_flags |= fb->rom == ON_OFF_AUTO_ON ? RAM_READONLY : 0; in file_backend_memory_alloc()
238 OnOffAuto rom = fb->rom; in file_memory_backend_get_rom() local
240 visit_type_OnOffAuto(v, name, &rom, errp); in file_memory_backend_get_rom()
256 visit_type_OnOffAuto(v, name, &fb->rom, errp); in file_memory_backend_set_rom()
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/openbmc/u-boot/arch/arm/mach-k3/
H A DKconfig20 specify the total size of SPL as ROM can use some part
21 of this RAM. Once ROM gives control to SPL then this
28 Describes the maximum size of the image that ROM can download
47 Address at which ROM stores the value which determines if SPL
/openbmc/u-boot/doc/
H A DREADME.sh7753evb12 - SPI ROM 8MB
35 You can write MAC address to SPI ROM.
57 Update SPI ROM:
64 3. Erase SPI ROM.
66 4. Write u-boot image to SPI ROM.
H A DREADME.sh7752evb12 - SPI ROM 8MB
35 You can write MAC address to SPI ROM.
57 Update SPI ROM:
64 3. Erase SPI ROM.
66 4. Write u-boot image to SPI ROM.
H A DREADME.x8662 Building a ROM version of U-Boot (hereafter referred to as u-boot.rom) is a
64 shipped in the U-Boot source tree. Due to this reason, the u-boot.rom build is
66 on by enabling the ROM build either via an environment variable
74 Both tell the Makefile to build u-boot.rom as a target.
85 * video ROM - sets up the display
99 As for the video ROM, you can get it here [3] and rename it to vga.bin.
102 Now you can build U-Boot and obtain u-boot.rom:
117 * vga.bin - video ROM, which sets up the display
151 pci8086,0406.rom 0x7004c0 optionrom 65536
167 cbfstool samus.bin extract -n pci8086,0406.rom -f vga.bin
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H A DREADME.ag101p22 If you want to boot this system from SPI ROM and bypass e-bios (the
23 other boot loader on ROM). You should undefine CONFIG_SKIP_LOWLEVEL_INIT
33 Burn u-boot to SPI ROM:
/openbmc/u-boot/drivers/pci/
H A Dpci_rom.c92 /* Enable expansion ROM address decoding. */ in pci_rom_probe()
96 debug("Option ROM address %x\n", rom_address); in pci_rom_probe()
99 debug("PCI expansion ROM, signature %#04x, INIT size %#04x, data ptr %#04x\n", in pci_rom_probe()
104 printf("Incorrect expansion ROM header signature %04x\n", in pci_rom_probe()
107 /* Disable expansion ROM address decoding */ in pci_rom_probe()
117 debug("PCI ROM image, vendor ID %04x, device ID %04x,\n", in pci_rom_probe()
129 debug("PCI ROM image, Class Code %06x, Code Type %02x\n", in pci_rom_probe()
133 debug("Class Code mismatch ROM %06x, dev %06x\n", in pci_rom_probe()
142 * pci_rom_load() - Load a ROM image and return a pointer to it
144 * @rom_header: Pointer to ROM image
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/openbmc/qemu/hw/i386/
H A Dvapic.c64 MemoryRegion rom; member
298 /* bail out if ROM init code was not executed (missing ROM?) */ in update_rom_mapping()
303 /* find out virtual address of the ROM */ in update_rom_mapping()
319 /* fixup addresses in ROM if needed */ in update_rom_mapping()
545 uint8_t *rom; in patch_hypercalls() local
547 rom = g_malloc(s->rom_size); in patch_hypercalls()
548 cpu_physical_memory_read(rom_paddr, rom, s->rom_size); in patch_hypercalls()
562 if (memcmp(rom + pos, pattern, 7) == 0 && in patch_hypercalls()
563 (rom[pos + 7] == alternates[0] || rom[pos + 7] == alternates[1])) { in patch_hypercalls()
573 g_free(rom); in patch_hypercalls()
[all …]
/openbmc/u-boot/board/renesas/sh7757lcr/
H A DREADME.sh7757lcr12 - SPI ROM 8MB
43 You can write MAC address to SPI ROM.
67 Update SPI ROM:
74 3. Erase SPI ROM.
76 4. Write u-boot image to SPI ROM.
/openbmc/u-boot/arch/arm/include/asm/arch-mx7/
H A Dmx7_plugin.S21 * Check if we are in USB serial download mode and immediately return to ROM
40 * The following is to fill in those arguments for this ROM function
65 /* To return to ROM from plugin, we need to fill in these argument.
67 * Need to construct the paramters for this function before return to ROM:
81 /* return back to ROM code */
/openbmc/qemu/scripts/
H A Dsignrom.py4 # Option ROM signing utility
24 sys.exit("%s: option ROM does not begin with magic 55 aa" % sys.argv[1])
32 sys.stderr.write('error: ROM is too large (%d > %d)\n' % (len(data), size))
41 sys.stderr.write('WARNING: ROM includes nonzero checksum\n')
/openbmc/qemu/include/hw/arm/
H A Dallwinner-a10.h53 * Emulate Boot ROM firmware setup functionality.
55 * A real Allwinner A10 SoC contains a Boot ROM
57 * the SoC is powered on. The Boot ROM is responsible
63 * This function emulates the Boot ROM by copying 32 KiB
/openbmc/u-boot/arch/arm/mach-omap2/omap5/
H A Dsec_entry_cpu1.S27 /* DRA7xx ROM code function "startup_BootSlave". This function is where CPU1
68 bx r4 @ Jump back to ROM
74 * Makes a secure ROM/PPA call on CPU Core #1 on supported platforms.
75 * Assumes that CPU #1 is waiting in ROM code and not yet woken up or used by
93 str r5, [r4] @ Tell ROM to exit while loop
/openbmc/u-boot/arch/arm/cpu/arm926ejs/mx27/
H A Drelocate.S16 * in ROM. Therefore, vectors cannot be changed at all.
18 * However, these ROM-based vectors actually just perform indirect
22 * Offset Exception Use by ROM code
28 * 0x00000014 (reserved in ARMv5) vector to ROM reset: 0xc0000000
/openbmc/u-boot/cmd/
H A Dcbfs.c20 printf("usage: cbfsls [end of rom]>\n"); in do_cbfs_init()
26 puts("\n** Invalid end of ROM **\n"); in do_cbfs_init()
41 "[end of rom]\n"
42 " - Initialize the cbfs driver. The optional 'end of rom'\n"
43 " parameter specifies where the end of the ROM is that the\n"
131 type_name = "option rom"; in do_cbfs_ls()
215 printf("ROM size: %#x\n", header->rom_size); in do_cbfs_fsinfo()
/openbmc/qemu/docs/system/ppc/
H A Damigang.rst33 The ROM image is in the last 512kB which can be extracted with the
86 The Pegasos II board has an Open Firmware compliant ROM based on
88 the ROM binary cannot be included in QEMU. An updater was available
91 The ROM image can be extracted from it with the following command:
95 $ tail -c +85581 up050404 | head -c 524288 > pegasos2.rom
106 $ qemu-system-ppc -machine pegasos2 -bios pegasos2.rom \
113 firmware ROM using the QEMU built-in minimal Virtual Open Firmware
135 modifications to support booting AmigaOS 4. The firmware ROM is
/openbmc/u-boot/arch/arm/mach-uniphier/
H A Dmmc-boot-mode.c16 * work around a bug in the Boot ROM of LD4, Pro4, and sLD8: in spl_boot_mode()
18 * The boot ROM in these SoCs breaks the PARTITION_CONFIG [179] of in spl_boot_mode()
20 * Boot ROM should issue the SWITCH command (CMD6) with Set Bits for in spl_boot_mode()
/openbmc/u-boot/arch/nds32/cpu/n1213/ag101/
H A Dlowlevel_init.S95 * BANK0: FLASH/ROM (SW5, J16), BANK1: OnBoard SDRAM.
206 * Copy ROM code to SDRAM base for memory remap layout.
216 * The reason is because the ROM/FLASH circuit on PCB board.
218 * ROM/FLASH is used to boot.
220 * When SW5 = "0101", MA17 = LO, the ROM is connected to BANK0,
222 * When SW5 = "1010", MA17 = HI, the ROM is disabled (still at BANK0),
251 * - before remap: flash/rom 0x00000000, sdram: 0x10000000-0x4fffffff
252 * - after remap: flash/rom 0x80000000, sdram: 0x00000000
277 * extend rom base from 256MB to 2GB

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