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Searched full:r8a7795_clk_s0d4 (Results 1 – 7 of 7) sorted by relevance

/openbmc/linux/include/dt-bindings/clock/
H A Dr8a7795-cpg-mssr.h20 #define R8A7795_CLK_S0D4 9 macro
/openbmc/u-boot/include/dt-bindings/clock/
H A Dr8a7795-cpg-mssr.h24 #define R8A7795_CLK_S0D4 9 macro
/openbmc/linux/drivers/clk/renesas/
H A Dr8a7795-cpg-mssr.c90 DEF_FIXED("s0d4", R8A7795_CLK_S0D4, CLK_S0, 4, 1),
224 DEF_MOD("lvds", 727, R8A7795_CLK_S0D4),
256 DEF_MOD("adg", 922, R8A7795_CLK_S0D4),
/openbmc/linux/Documentation/devicetree/bindings/display/bridge/
H A Drenesas,dw-hdmi.yaml89 clocks = <&cpg CPG_CORE R8A7795_CLK_S0D4>, <&cpg CPG_MOD 729>;
/openbmc/u-boot/drivers/clk/renesas/
H A Dr8a7795-cpg-mssr.c82 DEF_FIXED("s0d4", R8A7795_CLK_S0D4, CLK_S0, 4, 1),
202 DEF_MOD("lvds", 727, R8A7795_CLK_S0D4),
/openbmc/u-boot/arch/arm/dts/
H A Dr8a7795.dtsi12 #define CPG_AUDIO_CLK_I R8A7795_CLK_S0D4
1819 <&cpg CPG_CORE R8A7795_CLK_S0D4>;
/openbmc/linux/arch/arm64/boot/dts/renesas/
H A Dr8a77951.dtsi12 #define CPG_AUDIO_CLK_I R8A7795_CLK_S0D4
2035 <&cpg CPG_CORE R8A7795_CLK_S0D4>;