1*4157c472SMarek Vasut /*
2*4157c472SMarek Vasut  * Copyright (C) 2015 Renesas Electronics Corp.
3*4157c472SMarek Vasut  *
4*4157c472SMarek Vasut  * This program is free software; you can redistribute it and/or modify
5*4157c472SMarek Vasut  * it under the terms of the GNU General Public License as published by
6*4157c472SMarek Vasut  * the Free Software Foundation; either version 2 of the License, or
7*4157c472SMarek Vasut  * (at your option) any later version.
8*4157c472SMarek Vasut  */
9*4157c472SMarek Vasut #ifndef __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__
10*4157c472SMarek Vasut #define __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__
11*4157c472SMarek Vasut 
12*4157c472SMarek Vasut #include <dt-bindings/clock/renesas-cpg-mssr.h>
13*4157c472SMarek Vasut 
14*4157c472SMarek Vasut /* r8a7795 CPG Core Clocks */
15*4157c472SMarek Vasut #define R8A7795_CLK_Z			0
16*4157c472SMarek Vasut #define R8A7795_CLK_Z2			1
17*4157c472SMarek Vasut #define R8A7795_CLK_ZR			2
18*4157c472SMarek Vasut #define R8A7795_CLK_ZG			3
19*4157c472SMarek Vasut #define R8A7795_CLK_ZTR			4
20*4157c472SMarek Vasut #define R8A7795_CLK_ZTRD2		5
21*4157c472SMarek Vasut #define R8A7795_CLK_ZT			6
22*4157c472SMarek Vasut #define R8A7795_CLK_ZX			7
23*4157c472SMarek Vasut #define R8A7795_CLK_S0D1		8
24*4157c472SMarek Vasut #define R8A7795_CLK_S0D4		9
25*4157c472SMarek Vasut #define R8A7795_CLK_S1D1		10
26*4157c472SMarek Vasut #define R8A7795_CLK_S1D2		11
27*4157c472SMarek Vasut #define R8A7795_CLK_S1D4		12
28*4157c472SMarek Vasut #define R8A7795_CLK_S2D1		13
29*4157c472SMarek Vasut #define R8A7795_CLK_S2D2		14
30*4157c472SMarek Vasut #define R8A7795_CLK_S2D4		15
31*4157c472SMarek Vasut #define R8A7795_CLK_S3D1		16
32*4157c472SMarek Vasut #define R8A7795_CLK_S3D2		17
33*4157c472SMarek Vasut #define R8A7795_CLK_S3D4		18
34*4157c472SMarek Vasut #define R8A7795_CLK_LB			19
35*4157c472SMarek Vasut #define R8A7795_CLK_CL			20
36*4157c472SMarek Vasut #define R8A7795_CLK_ZB3			21
37*4157c472SMarek Vasut #define R8A7795_CLK_ZB3D2		22
38*4157c472SMarek Vasut #define R8A7795_CLK_CR			23
39*4157c472SMarek Vasut #define R8A7795_CLK_CRD2		24
40*4157c472SMarek Vasut #define R8A7795_CLK_SD0H		25
41*4157c472SMarek Vasut #define R8A7795_CLK_SD0			26
42*4157c472SMarek Vasut #define R8A7795_CLK_SD1H		27
43*4157c472SMarek Vasut #define R8A7795_CLK_SD1			28
44*4157c472SMarek Vasut #define R8A7795_CLK_SD2H		29
45*4157c472SMarek Vasut #define R8A7795_CLK_SD2			30
46*4157c472SMarek Vasut #define R8A7795_CLK_SD3H		31
47*4157c472SMarek Vasut #define R8A7795_CLK_SD3			32
48*4157c472SMarek Vasut #define R8A7795_CLK_SSP2		33
49*4157c472SMarek Vasut #define R8A7795_CLK_SSP1		34
50*4157c472SMarek Vasut #define R8A7795_CLK_SSPRS		35
51*4157c472SMarek Vasut #define R8A7795_CLK_RPC			36
52*4157c472SMarek Vasut #define R8A7795_CLK_RPCD2		37
53*4157c472SMarek Vasut #define R8A7795_CLK_MSO			38
54*4157c472SMarek Vasut #define R8A7795_CLK_CANFD		39
55*4157c472SMarek Vasut #define R8A7795_CLK_HDMI		40
56*4157c472SMarek Vasut #define R8A7795_CLK_CSI0		41
57*4157c472SMarek Vasut #define R8A7795_CLK_CSIREF		42
58*4157c472SMarek Vasut #define R8A7795_CLK_CP			43
59*4157c472SMarek Vasut #define R8A7795_CLK_CPEX		44
60*4157c472SMarek Vasut #define R8A7795_CLK_R			45
61*4157c472SMarek Vasut #define R8A7795_CLK_OSC			46
62*4157c472SMarek Vasut 
63*4157c472SMarek Vasut /* r8a7795 ES2.0 CPG Core Clocks */
64*4157c472SMarek Vasut #define R8A7795_CLK_S0D2		47
65*4157c472SMarek Vasut #define R8A7795_CLK_S0D3		48
66*4157c472SMarek Vasut #define R8A7795_CLK_S0D6		49
67*4157c472SMarek Vasut #define R8A7795_CLK_S0D8		50
68*4157c472SMarek Vasut #define R8A7795_CLK_S0D12		51
69*4157c472SMarek Vasut 
70*4157c472SMarek Vasut #endif /* __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__ */
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