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/openbmc/qemu/hw/intc/
H A Dsifive_plic.c2 * SiFive PLIC (Platform Level Interrupt Controller)
6 * This provides a parameterizable interrupt controller based on SiFive's PLIC.
47 error_report("plic: invalid mode '%c'", c); in char_to_mode()
65 static void sifive_plic_set_pending(SiFivePLICState *plic, int irq, bool level) in sifive_plic_set_pending() argument
67 atomic_set_masked(&plic->pending[irq >> 5], 1 << (irq & 31), -!!level); in sifive_plic_set_pending()
70 static void sifive_plic_set_claimed(SiFivePLICState *plic, int irq, bool level) in sifive_plic_set_claimed() argument
72 atomic_set_masked(&plic->claimed[irq >> 5], 1 << (irq & 31), -!!level); in sifive_plic_set_claimed()
75 static uint32_t sifive_plic_claimed(SiFivePLICState *plic, uint32_t addrid) in sifive_plic_claimed() argument
78 uint32_t max_prio = plic->target_priority[addrid]; in sifive_plic_claimed()
82 for (i = 0; i < plic->bitfield_words; i++) { in sifive_plic_claimed()
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/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dsifive,plic-1.0.0.yaml5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
8 title: SiFive Platform-Level Interrupt Controller (PLIC)
12 Platform-Level Interrupt Controller (PLIC) high-level specification in
13 the RISC-V Privileged Architecture specification. The PLIC connects all
26 with priority below this threshold will not cause the PLIC to raise its
29 The PLIC supports both edge-triggered and level-triggered interrupts. For
30 edge-triggered interrupts, the RISC-V PLIC spec allows two responses to edges
31 seen while an interrupt handler is active; the PLIC may either queue them or
36 RZ/Five SoC (AX45MP AndesCore with a NCEPLIC100) and the T-HEAD C900 PLIC.
38 While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
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H A Driscv,cpu-intc.txt16 via the platform-level interrupt controller (PLIC).
21 entry, though external interrupt controllers (like the PLIC, for example) will
23 a PLIC interrupt property will typically list the HLICs for all present HARTs
/openbmc/qemu/hw/riscv/
H A Dopentitan.c130 object_initialize_child(obj, "plic", &s->plic, TYPE_SIFIVE_PLIC); in lowrisc_ibex_soc_init()
177 /* PLIC */ in lowrisc_ibex_soc_realize()
178 qdev_prop_set_string(DEVICE(&s->plic), "hart-config", "M"); in lowrisc_ibex_soc_realize()
179 qdev_prop_set_uint32(DEVICE(&s->plic), "num-sources", 180); in lowrisc_ibex_soc_realize()
180 qdev_prop_set_uint32(DEVICE(&s->plic), "num-priorities", 3); in lowrisc_ibex_soc_realize()
181 qdev_prop_set_uint32(DEVICE(&s->plic), "pending-base", 0x1000); in lowrisc_ibex_soc_realize()
182 qdev_prop_set_uint32(DEVICE(&s->plic), "enable-base", 0x2000); in lowrisc_ibex_soc_realize()
183 qdev_prop_set_uint32(DEVICE(&s->plic), "enable-stride", 32); in lowrisc_ibex_soc_realize()
184 qdev_prop_set_uint32(DEVICE(&s->plic), "context-base", 0x200000); in lowrisc_ibex_soc_realize()
185 qdev_prop_set_uint32(DEVICE(&s->plic), "context-stride", 8); in lowrisc_ibex_soc_realize()
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H A Dmicrochip_pfsoc.c12 * 1) PLIC (Platform Level Interrupt Controller)
277 /* create PLIC hart topology configuration string */ in microchip_pfsoc_soc_realize()
280 /* PLIC */ in microchip_pfsoc_soc_realize()
281 s->plic = sifive_plic_create(memmap[MICROCHIP_PFSOC_PLIC].base, in microchip_pfsoc_soc_realize()
300 qdev_get_gpio_in(DEVICE(s->plic), in microchip_pfsoc_soc_realize()
309 qdev_get_gpio_in(DEVICE(s->plic), in microchip_pfsoc_soc_realize()
342 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_EMMC_SD_IRQ)); in microchip_pfsoc_soc_realize()
347 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART0_IRQ), in microchip_pfsoc_soc_realize()
351 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART1_IRQ), in microchip_pfsoc_soc_realize()
355 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART2_IRQ), in microchip_pfsoc_soc_realize()
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H A Dsifive_e.c10 * 2) PLIC (Platform Level Interrupt Controller)
210 s->plic = sifive_plic_create(memmap[SIFIVE_E_DEV_PLIC].base, in sifive_e_soc_realize()
251 /* Connect GPIO interrupts to the PLIC */ in sifive_e_soc_realize()
254 qdev_get_gpio_in(DEVICE(s->plic), in sifive_e_soc_realize()
258 qdev_get_gpio_in(DEVICE(s->plic), in sifive_e_soc_realize()
262 serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART0_IRQ)); in sifive_e_soc_realize()
268 serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART1_IRQ)); in sifive_e_soc_realize()
H A Dsifive_u.c12 * 2) PLIC (Platform Level Interrupt Controller)
111 "sifive,plic-1.0.0", "riscv,plic0" in create_fdt()
826 /* create PLIC hart topology configuration string */ in sifive_u_soc_realize()
830 s->plic = sifive_plic_create(memmap[SIFIVE_U_DEV_PLIC].base, in sifive_u_soc_realize()
843 serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ)); in sifive_u_soc_realize()
845 serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ)); in sifive_u_soc_realize()
868 /* Connect GPIO interrupts to the PLIC */ in sifive_u_soc_realize()
871 qdev_get_gpio_in(DEVICE(s->plic), in sifive_u_soc_realize()
879 /* Connect PDMA interrupts to the PLIC */ in sifive_u_soc_realize()
882 qdev_get_gpio_in(DEVICE(s->plic), in sifive_u_soc_realize()
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/openbmc/linux/arch/riscv/boot/dts/microchip/
H A Dmpfs.dtsi195 interrupt-parent = <&plic>;
209 plic: interrupt-controller@c000000 { label
210 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
226 interrupt-parent = <&plic>;
277 interrupt-parent = <&plic>;
289 interrupt-parent = <&plic>;
301 interrupt-parent = <&plic>;
313 interrupt-parent = <&plic>;
325 interrupt-parent = <&plic>;
336 interrupt-parent = <&plic>;
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H A Dmpfs-icicle-kit-fabric.dtsi23 interrupt-parent = <&plic>;
38 interrupt-parent = <&plic>;
H A Dmpfs-polarberry-fabric.dtsi26 interrupt-parent = <&plic>;
H A Dmpfs-m100pfs-fabric.dtsi26 interrupt-parent = <&plic>;
/openbmc/linux/arch/riscv/boot/dts/allwinner/
H A Dsun20i-d1s.dtsi53 interrupt-parent = <&plic>;
63 plic: interrupt-controller@10000000 { label
64 compatible = "allwinner,sun20i-d1-plic",
65 "thead,c900-plic";
/openbmc/qemu/include/hw/intc/
H A Dsifive_plic.h2 * SiFive PLIC (Platform Level Interrupt Controller) interface
6 * This provides a RISC-V PLIC device
27 #define TYPE_SIFIVE_PLIC "riscv.sifive.plic"
/openbmc/linux/arch/riscv/boot/dts/renesas/
H A Dr9a07g043f.dtsi45 interrupt-parent = <&plic>;
47 plic: interrupt-controller@12c00000 { label
48 compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
/openbmc/linux/drivers/irqchip/
H A Dirq-sifive-plic.c6 #define pr_fmt(fmt) "plic: " fmt
24 * This driver implements a version of the RISC-V PLIC with the actual layout
29 * The largest number supported by devices marked as 'sifive,plic-1.0.0', is
191 .name = "SiFive PLIC",
206 .name = "SiFive PLIC",
542 * We can have multiple PLIC instances so setup cpuhp state in __plic_init()
549 "irqchip/sifive/plic:starting", in __plic_init()
579 IRQCHIP_DECLARE(sifive_plic, "sifive,plic-1.0.0", plic_init);
589 IRQCHIP_DECLARE(thead_c900_plic, "thead,c900-plic", plic_edge_init);
H A Dirq-riscv-intc.c82 * (such as PLIC, SBI IPI, CLINT, APLIC, IMSIC, etc) implement in riscv_intc_irq_eoi()
210 * interrupt controllers (such as PLIC, IMSIC and APLIC in riscv_intc_init()
/openbmc/linux/arch/riscv/boot/dts/starfive/
H A Djh7100.dtsi138 interrupt-parent = <&plic>;
150 plic: interrupt-controller@c000000 { label
151 compatible = "starfive,jh7100-plic", "sifive,plic-1.0.0";
/openbmc/linux/arch/riscv/boot/dts/thead/
H A Dth1520.dtsi139 interrupt-parent = <&plic>;
145 plic: interrupt-controller@ffd8000000 { label
146 compatible = "thead,th1520-plic", "thead,c900-plic";
/openbmc/linux/Documentation/devicetree/bindings/net/can/
H A Dmicrochip,mpfs-can.yaml43 interrupt-parent = <&plic>;
/openbmc/linux/Documentation/devicetree/bindings/usb/
H A Dmicrochip,mpfs-musb.yaml53 interrupt-parent = <&plic>;
/openbmc/u-boot/doc/
H A DREADME.AX2541 Platform Level Interrupt Controller (PLIC)
H A DREADME.qemu-riscv13 the VirtIO standard networking and block storage devices. It has CLINT, PLIC,
/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Dmicrochip,mpfs-spi.yaml55 interrupt-parent = <&plic>;
/openbmc/linux/Documentation/devicetree/bindings/i2c/
H A Dmicrochip,corei2c.yaml52 interrupt-parent = <&plic>;
/openbmc/qemu/include/hw/riscv/
H A Dshakti_c.h36 DeviceState *plic; member

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