1b3e77da0SLad Prabhakar// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2b3e77da0SLad Prabhakar/* 3b3e77da0SLad Prabhakar * Device Tree Source for the RZ/Five SoC 4b3e77da0SLad Prabhakar * 5b3e77da0SLad Prabhakar * Copyright (C) 2022 Renesas Electronics Corp. 6b3e77da0SLad Prabhakar */ 7b3e77da0SLad Prabhakar 8b3e77da0SLad Prabhakar#include <dt-bindings/interrupt-controller/irq.h> 9b3e77da0SLad Prabhakar 10b3e77da0SLad Prabhakar#define SOC_PERIPHERAL_IRQ(nr) (nr + 32) 11b3e77da0SLad Prabhakar 12b3e77da0SLad Prabhakar#include <arm64/renesas/r9a07g043.dtsi> 13b3e77da0SLad Prabhakar 14b3e77da0SLad Prabhakar/ { 15b3e77da0SLad Prabhakar cpus { 16b3e77da0SLad Prabhakar #address-cells = <1>; 17b3e77da0SLad Prabhakar #size-cells = <0>; 18b3e77da0SLad Prabhakar timebase-frequency = <12000000>; 19b3e77da0SLad Prabhakar 20b3e77da0SLad Prabhakar cpu0: cpu@0 { 21b3e77da0SLad Prabhakar compatible = "andestech,ax45mp", "riscv"; 22b3e77da0SLad Prabhakar device_type = "cpu"; 23*42d3345eSLad Prabhakar #cooling-cells = <2>; 24b3e77da0SLad Prabhakar reg = <0x0>; 25b3e77da0SLad Prabhakar status = "okay"; 26b3e77da0SLad Prabhakar riscv,isa = "rv64imafdc"; 27b3e77da0SLad Prabhakar mmu-type = "riscv,sv39"; 28b3e77da0SLad Prabhakar i-cache-size = <0x8000>; 29b3e77da0SLad Prabhakar i-cache-line-size = <0x40>; 30b3e77da0SLad Prabhakar d-cache-size = <0x8000>; 31b3e77da0SLad Prabhakar d-cache-line-size = <0x40>; 32b3e77da0SLad Prabhakar clocks = <&cpg CPG_CORE R9A07G043_CLK_I>; 33*42d3345eSLad Prabhakar operating-points-v2 = <&cluster0_opp>; 34b3e77da0SLad Prabhakar 35b3e77da0SLad Prabhakar cpu0_intc: interrupt-controller { 36b3e77da0SLad Prabhakar #interrupt-cells = <1>; 37b3e77da0SLad Prabhakar compatible = "riscv,cpu-intc"; 38b3e77da0SLad Prabhakar interrupt-controller; 39b3e77da0SLad Prabhakar }; 40b3e77da0SLad Prabhakar }; 41b3e77da0SLad Prabhakar }; 42b3e77da0SLad Prabhakar}; 43b3e77da0SLad Prabhakar 44b3e77da0SLad Prabhakar&soc { 45b3e77da0SLad Prabhakar interrupt-parent = <&plic>; 46b3e77da0SLad Prabhakar 47b3e77da0SLad Prabhakar plic: interrupt-controller@12c00000 { 48b3e77da0SLad Prabhakar compatible = "renesas,r9a07g043-plic", "andestech,nceplic100"; 49b3e77da0SLad Prabhakar #interrupt-cells = <2>; 50b3e77da0SLad Prabhakar #address-cells = <0>; 51b3e77da0SLad Prabhakar riscv,ndev = <511>; 52b3e77da0SLad Prabhakar interrupt-controller; 53b3e77da0SLad Prabhakar reg = <0x0 0x12c00000 0 0x400000>; 54b3e77da0SLad Prabhakar clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>; 55b3e77da0SLad Prabhakar power-domains = <&cpg>; 56b3e77da0SLad Prabhakar resets = <&cpg R9A07G043_NCEPLIC_ARESETN>; 57b3e77da0SLad Prabhakar interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>; 58b3e77da0SLad Prabhakar }; 59b3e77da0SLad Prabhakar}; 60